/**Function*************************************************************
Synopsis [Starts the simulation manager.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
Sim_Man_t * Sim_ManStart( Abc_Ntk_t * pNtk, int fLightweight )
{
Sim_Man_t * p;
// start the manager
p = ALLOC( Sim_Man_t, 1 );
memset( p, 0, sizeof(Sim_Man_t) );
p->pNtk = pNtk;
p->nInputs = Abc_NtkCiNum(p->pNtk);
p->nOutputs = Abc_NtkCoNum(p->pNtk);
// internal simulation information
p->nSimBits = 2048;
p->nSimWords = SIM_NUM_WORDS(p->nSimBits);
p->vSim0 = Sim_UtilInfoAlloc( Abc_NtkObjNumMax(pNtk), p->nSimWords, 0 );
p->fLightweight = fLightweight;
if (!p->fLightweight) {
p->vSim1 = Sim_UtilInfoAlloc( Abc_NtkObjNumMax(pNtk), p->nSimWords, 0 );
// support information
p->nSuppBits = Abc_NtkCiNum(pNtk);
p->nSuppWords = SIM_NUM_WORDS(p->nSuppBits);
p->vSuppStr = Sim_ComputeStrSupp( pNtk );
p->vSuppFun = Sim_UtilInfoAlloc( Abc_NtkCoNum(p->pNtk), p->nSuppWords, 1 );
// other data
p->pMmPat = Extra_MmFixedStart( sizeof(Sim_Pat_t) + p->nSuppWords * sizeof(unsigned) );
p->vFifo = Vec_PtrAlloc( 100 );
p->vDiffs = Vec_IntAlloc( 100 );
// allocate support targets (array of unresolved outputs for each input)
p->vSuppTargs = Vec_VecStart( p->nInputs );
}
return p;
}
/**Function*************************************************************
Synopsis [Finalizes the timing manager after setting arr/req times.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
void Abc_NtkTimeInitialize( Abc_Ntk_t * pNtk, Abc_Ntk_t * pNtkOld )
{
Abc_Obj_t * pObj;
Abc_Time_t ** ppTimes, * pTime;
int i;
assert( pNtkOld == NULL || pNtkOld->pManTime != NULL );
assert( pNtkOld == NULL || Abc_NtkCiNum(pNtk) == Abc_NtkCiNum(pNtkOld) );
assert( pNtkOld == NULL || Abc_NtkCoNum(pNtk) == Abc_NtkCoNum(pNtkOld) );
if ( pNtk->pManTime == NULL )
return;
Abc_ManTimeExpand( pNtk->pManTime, Abc_NtkObjNumMax(pNtk), 0 );
// set global defaults
if ( pNtkOld )
{
pNtk->pManTime->tArrDef = pNtkOld->pManTime->tArrDef;
pNtk->pManTime->tReqDef = pNtkOld->pManTime->tReqDef;
pNtk->AndGateDelay = pNtkOld->AndGateDelay;
}
// set the default timing
ppTimes = (Abc_Time_t **)pNtk->pManTime->vArrs->pArray;
Abc_NtkForEachCi( pNtk, pObj, i )
{
pTime = ppTimes[pObj->Id];
if ( Abc_MaxFloat(pTime->Fall, pTime->Rise) != -ABC_INFINITY )
continue;
*pTime = pNtkOld ? *Abc_NodeReadArrival(Abc_NtkCi(pNtkOld, i)) : pNtk->pManTime->tArrDef;
}
Map_Time_t * Abc_NtkMapCopyCoRequiredCon( Abc_Ntk_t * pNtk )
{
Map_Time_t * p; int i;
p = ABC_CALLOC( Map_Time_t, Abc_NtkCoNum(pNtk) );
for ( i = 0; i < Abc_NtkCoNum(pNtk); i++ )
p[i].Fall = p[i].Rise = p[i].Worst = Scl_Int2Flt( Scl_ConGetOutReq(i) );
return p;
}
Map_Time_t * Abc_NtkMapCopyCoRequired( Abc_Ntk_t * pNtk, Abc_Time_t * ppTimes )
{
Map_Time_t * p;
int i;
p = ABC_CALLOC( Map_Time_t, Abc_NtkCoNum(pNtk) );
for ( i = 0; i < Abc_NtkCoNum(pNtk); i++ )
{
p[i].Fall = ppTimes[i].Fall;
p[i].Rise = ppTimes[i].Rise;
p[i].Worst = Abc_MaxFloat( p[i].Fall, p[i].Rise );
}
ABC_FREE( ppTimes );
return p;
}
Abc_Ntk_t * Abc_NtkFromMap( Map_Man_t * pMan, Abc_Ntk_t * pNtk )
{
Abc_Ntk_t * pNtkNew;
Map_Node_t * pNodeMap;
Abc_Obj_t * pNode, * pNodeNew;
int i, nDupGates;
assert( Map_ManReadBufNum(pMan) == pNtk->nBarBufs );
// create the new network
pNtkNew = Abc_NtkStartFrom( pNtk, ABC_NTK_LOGIC, ABC_FUNC_MAP );
// make the mapper point to the new network
Map_ManCleanData( pMan );
Abc_NtkForEachCi( pNtk, pNode, i )
{
if ( i >= Abc_NtkCiNum(pNtk) - pNtk->nBarBufs )
break;
Map_NodeSetData( Map_ManReadInputs(pMan)[i], 1, (char *)pNode->pCopy );
}
Abc_NtkForEachCi( pNtk, pNode, i )
{
if ( i < Abc_NtkCiNum(pNtk) - pNtk->nBarBufs )
continue;
Map_NodeSetData( Map_ManReadBufs(pMan)[i - (Abc_NtkCiNum(pNtk) - pNtk->nBarBufs)], 1, (char *)pNode->pCopy );
}
// assign the mapping of the required phase to the POs
Abc_NtkForEachCo( pNtk, pNode, i )
{
if ( i < Abc_NtkCoNum(pNtk) - pNtk->nBarBufs )
continue;
pNodeMap = Map_ManReadBufDriver( pMan, i - (Abc_NtkCoNum(pNtk) - pNtk->nBarBufs) );
pNodeNew = Abc_NodeFromMap_rec( pNtkNew, Map_Regular(pNodeMap), !Map_IsComplement(pNodeMap) );
assert( !Abc_ObjIsComplement(pNodeNew) );
Abc_ObjAddFanin( pNode->pCopy, pNodeNew );
}
Abc_NtkForEachCo( pNtk, pNode, i )
{
if ( i >= Abc_NtkCoNum(pNtk) - pNtk->nBarBufs )
break;
pNodeMap = Map_ManReadOutputs(pMan)[i];
pNodeNew = Abc_NodeFromMap_rec( pNtkNew, Map_Regular(pNodeMap), !Map_IsComplement(pNodeMap) );
assert( !Abc_ObjIsComplement(pNodeNew) );
Abc_ObjAddFanin( pNode->pCopy, pNodeNew );
}
// decouple the PO driver nodes to reduce the number of levels
nDupGates = Abc_NtkLogicMakeSimpleCos( pNtkNew, 1 );
// if ( nDupGates && Map_ManReadVerbose(pMan) )
// printf( "Duplicated %d gates to decouple the CO drivers.\n", nDupGates );
return pNtkNew;
}
/**Function*************************************************************
Synopsis [Derives GIA manager together with the hierachy manager.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
Gia_Man_t * Abc_NtkTestTimDeriveGia( Abc_Ntk_t * pNtk, int fVerbose )
{
Gia_Man_t * pTemp;
Gia_Man_t * pGia = NULL;
Gia_Man_t * pHoles = NULL;
Tim_Man_t * pTim = NULL;
Vec_Int_t * vGiaCoLits, * vGiaCoLits2;
Vec_Flt_t * vArrTimes, * vReqTimes;
Abc_Obj_t * pObj, * pFanin;
int i, k, Entry, curPi, curPo, BoxUniqueId;
int nBoxFaninMax = 0;
assert( Abc_NtkIsTopo(pNtk) );
Abc_NtkFillTemp( pNtk );
// create white boxes
curPi = Abc_NtkCiNum(pNtk);
curPo = Abc_NtkCoNum(pNtk);
Abc_NtkForEachNode( pNtk, pObj, i )
{
pObj->fMarkA = Abc_NodeIsWhiteBox( pObj );
if ( !pObj->fMarkA )
continue;
nBoxFaninMax = Abc_MaxInt( nBoxFaninMax, Abc_ObjFaninNum(pObj) );
curPi++;
curPo += Abc_ObjFaninNum(pObj);
if ( fVerbose )
printf( "Selecting node %6d as white boxes with %d inputs and %d output.\n", i, Abc_ObjFaninNum(pObj), 1 );
}
void Abc_NtkTimeSetOutputLoad( Abc_Ntk_t * pNtk, int PoNum, float Rise, float Fall )
{
Abc_Time_t * pTime;
assert( PoNum >= 0 && PoNum < Abc_NtkCoNum(pNtk) );
if ( pNtk->pManTime == NULL )
pNtk->pManTime = Abc_ManTimeStart();
if ( pNtk->pManTime->tOutLoadDef.Rise == Rise && pNtk->pManTime->tOutLoadDef.Fall == Fall )
return;
if ( pNtk->pManTime->tOutLoad == NULL )
{
int i;
pNtk->pManTime->tOutLoad = ABC_CALLOC( Abc_Time_t, Abc_NtkCoNum(pNtk) );
for ( i = 0; i < Abc_NtkCoNum(pNtk); i++ )
pNtk->pManTime->tOutLoad[i] = pNtk->pManTime->tOutLoadDef;
}
pTime = pNtk->pManTime->tOutLoad + PoNum;
pTime->Rise = Rise;
pTime->Fall = Fall;
}
/**Function*************************************************************
Synopsis [Starts a new network using existing network as a model.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
Abc_Ntk_t * Abc_NtkStartFrom( Abc_Ntk_t * pNtk, Abc_NtkType_t Type, Abc_NtkFunc_t Func )
{
Abc_Ntk_t * pNtkNew;
Abc_Obj_t * pObj;
int fCopyNames, i;
if ( pNtk == NULL )
return NULL;
// decide whether to copy the names
fCopyNames = ( Type != ABC_NTK_NETLIST );
// start the network
pNtkNew = Abc_NtkAlloc( Type, Func, 1 );
// duplicate the name and the spec
pNtkNew->pName = Extra_UtilStrsav(pNtk->pName);
pNtkNew->pSpec = Extra_UtilStrsav(pNtk->pSpec);
// clean the node copy fields
Abc_NtkCleanCopy( pNtk );
// map the constant nodes
if ( Abc_NtkIsStrash(pNtk) && Abc_NtkIsStrash(pNtkNew) )
Abc_AigConst1(pNtk)->pCopy = Abc_AigConst1(pNtkNew);
// clone CIs/CIs/boxes
Abc_NtkForEachPi( pNtk, pObj, i )
Abc_NtkDupObj( pNtkNew, pObj, fCopyNames );
Abc_NtkForEachPo( pNtk, pObj, i )
Abc_NtkDupObj( pNtkNew, pObj, fCopyNames );
Abc_NtkForEachAssert( pNtk, pObj, i )
Abc_NtkDupObj( pNtkNew, pObj, fCopyNames );
Abc_NtkForEachBox( pNtk, pObj, i )
Abc_NtkDupBox( pNtkNew, pObj, fCopyNames );
// transfer the names
// Abc_NtkTrasferNames( pNtk, pNtkNew );
Abc_ManTimeDup( pNtk, pNtkNew );
// check that the CI/CO/latches are copied correctly
assert( Abc_NtkCiNum(pNtk) == Abc_NtkCiNum(pNtkNew) );
assert( Abc_NtkCoNum(pNtk) == Abc_NtkCoNum(pNtkNew) );
assert( Abc_NtkLatchNum(pNtk) == Abc_NtkLatchNum(pNtkNew) );
return pNtkNew;
}
Abc_NtkForEachCo( pNtk, pObj, i )
{
if ( !Abc_NodeIsTravIdCurrent(pObj) )
continue;
// get the result of quantification
if ( i == Abc_NtkCoNum(pNtk) - 1 )
{
pOutput = Abc_AigAnd( (Abc_Aig_t *)pMiter->pManFunc, pOutput, Abc_ObjChild0Data(pObj) );
pOutput = Abc_AigAnd( (Abc_Aig_t *)pMiter->pManFunc, pOutput, Abc_ObjChild0Copy(pObj) );
}
else
{
pNext = Abc_AigXor( (Abc_Aig_t *)pMiter->pManFunc, Abc_ObjChild0Copy(pObj), Abc_ObjChild0Data(pObj) );
pOutput = Abc_AigOr( (Abc_Aig_t *)pMiter->pManFunc, pOutput, pNext );
}
}
void Abc_NtkTimeSetDefaultOutputLoad( Abc_Ntk_t * pNtk, float Rise, float Fall )
{
if ( Rise == 0.0 && Fall == 0.0 )
return;
if ( pNtk->pManTime == NULL )
pNtk->pManTime = Abc_ManTimeStart();
pNtk->pManTime->tOutLoadDef.Rise = Rise;
pNtk->pManTime->tOutLoadDef.Fall = Fall;
if ( pNtk->pManTime->tOutLoad != NULL )
{
int i;
for ( i = 0; i < Abc_NtkCoNum(pNtk); i++ )
if ( pNtk->pManTime->tOutLoad[i].Rise == 0 && pNtk->pManTime->tOutLoad[i].Fall == 0 )
pNtk->pManTime->tOutLoad[i] = pNtk->pManTime->tOutLoadDef;
}
}
/**Function*************************************************************
Synopsis [Starts the simulation manager.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
Sym_Man_t * Sym_ManStart( Abc_Ntk_t * pNtk, int fVerbose )
{
Sym_Man_t * p;
int i, v;
// start the manager
p = ALLOC( Sym_Man_t, 1 );
memset( p, 0, sizeof(Sym_Man_t) );
p->pNtk = pNtk;
p->vNodes = Abc_NtkDfs( pNtk, 0 );
p->nInputs = Abc_NtkCiNum(p->pNtk);
p->nOutputs = Abc_NtkCoNum(p->pNtk);
// internal simulation information
p->nSimWords = SIM_NUM_WORDS(p->nInputs);
p->vSim = Sim_UtilInfoAlloc( Abc_NtkObjNumMax(pNtk), p->nSimWords, 0 );
// symmetry info for each output
p->vMatrSymms = Vec_PtrStart( p->nOutputs );
p->vMatrNonSymms = Vec_PtrStart( p->nOutputs );
p->vPairsTotal = Vec_IntStart( p->nOutputs );
p->vPairsSym = Vec_IntStart( p->nOutputs );
p->vPairsNonSym = Vec_IntStart( p->nOutputs );
for ( i = 0; i < p->nOutputs; i++ )
{
p->vMatrSymms->pArray[i] = Extra_BitMatrixStart( p->nInputs );
p->vMatrNonSymms->pArray[i] = Extra_BitMatrixStart( p->nInputs );
}
// temporary patterns
p->uPatRand = ALLOC( unsigned, p->nSimWords );
p->uPatCol = ALLOC( unsigned, p->nSimWords );
p->uPatRow = ALLOC( unsigned, p->nSimWords );
p->vVarsU = Vec_IntStart( 100 );
p->vVarsV = Vec_IntStart( 100 );
// compute supports
p->vSuppFun = Sim_ComputeFunSupp( pNtk, fVerbose );
p->vSupports = Vec_VecStart( p->nOutputs );
for ( i = 0; i < p->nOutputs; i++ )
for ( v = 0; v < p->nInputs; v++ )
if ( Sim_SuppFunHasVar( p->vSuppFun, i, v ) )
Vec_VecPush( p->vSupports, i, (void *)v );
return p;
}
/**Function*************************************************************
Synopsis [Derive BDD of the characteristic function.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
DdNode * Abc_ResBuildBdd( Abc_Ntk_t * pNtk, DdManager * dd )
{
Vec_Ptr_t * vNodes, * vBdds, * vLocals;
Abc_Obj_t * pObj, * pFanin;
DdNode * bFunc, * bPart, * bTemp, * bVar;
int i, k;
assert( Abc_NtkIsSopLogic(pNtk) );
assert( Abc_NtkCoNum(pNtk) <= 3 );
vBdds = Vec_PtrStart( Abc_NtkObjNumMax(pNtk) );
Abc_NtkForEachCi( pNtk, pObj, i )
Vec_PtrWriteEntry( vBdds, Abc_ObjId(pObj), Cudd_bddIthVar(dd, i) );
// create internal node BDDs
vNodes = Abc_NtkDfs( pNtk, 0 );
vLocals = Vec_PtrAlloc( 6 );
Vec_PtrForEachEntry( Abc_Obj_t *, vNodes, pObj, i )
{
if ( Abc_ObjFaninNum(pObj) == 0 )
{
bFunc = Cudd_NotCond( Cudd_ReadOne(dd), Abc_SopIsConst0((char *)pObj->pData) ); Cudd_Ref( bFunc );
Vec_PtrWriteEntry( vBdds, Abc_ObjId(pObj), bFunc );
continue;
}
Vec_PtrClear( vLocals );
Abc_ObjForEachFanin( pObj, pFanin, k )
Vec_PtrPush( vLocals, Vec_PtrEntry(vBdds, Abc_ObjId(pFanin)) );
bFunc = Abc_ConvertSopToBdd( dd, (char *)pObj->pData, (DdNode **)Vec_PtrArray(vLocals) ); Cudd_Ref( bFunc );
Vec_PtrWriteEntry( vBdds, Abc_ObjId(pObj), bFunc );
}
Vec_PtrFree( vLocals );
// create char function
bFunc = Cudd_ReadOne( dd ); Cudd_Ref( bFunc );
Abc_NtkForEachCo( pNtk, pObj, i )
{
bVar = Cudd_bddIthVar( dd, i + Abc_NtkCiNum(pNtk) );
bTemp = (DdNode *)Vec_PtrEntry( vBdds, Abc_ObjFaninId0(pObj) );
bPart = Cudd_bddXnor( dd, bTemp, bVar ); Cudd_Ref( bPart );
bFunc = Cudd_bddAnd( dd, bTemp = bFunc, bPart ); Cudd_Ref( bFunc );
Cudd_RecursiveDeref( dd, bTemp );
Cudd_RecursiveDeref( dd, bPart );
}
/**Function*************************************************************
Synopsis [Load the network into FPGA manager.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
Fpga_Man_t * Abc_NtkToFpga( Abc_Ntk_t * pNtk, int fRecovery, float * pSwitching, int fLatchPaths, int fVerbose )
{
Fpga_Man_t * pMan;
ProgressBar * pProgress;
Fpga_Node_t * pNodeFpga;
Vec_Ptr_t * vNodes;
Abc_Obj_t * pNode, * pFanin, * pPrev;
float * pfArrivals;
int i;
assert( Abc_NtkIsStrash(pNtk) );
// start the mapping manager and set its parameters
pMan = Fpga_ManCreate( Abc_NtkCiNum(pNtk), Abc_NtkCoNum(pNtk), fVerbose );
if ( pMan == NULL )
return NULL;
Fpga_ManSetAreaRecovery( pMan, fRecovery );
Fpga_ManSetOutputNames( pMan, Abc_NtkCollectCioNames(pNtk, 1) );
pfArrivals = Abc_NtkGetCiArrivalFloats(pNtk);
if ( fLatchPaths )
{
for ( i = 0; i < Abc_NtkPiNum(pNtk); i++ )
pfArrivals[i] = -FPGA_FLOAT_LARGE;
}
Fpga_ManSetInputArrivals( pMan, pfArrivals );
// create PIs and remember them in the old nodes
Abc_NtkCleanCopy( pNtk );
Abc_AigConst1(pNtk)->pCopy = (Abc_Obj_t *)Fpga_ManReadConst1(pMan);
Abc_NtkForEachCi( pNtk, pNode, i )
{
pNodeFpga = Fpga_ManReadInputs(pMan)[i];
pNode->pCopy = (Abc_Obj_t *)pNodeFpga;
if ( pSwitching )
Fpga_NodeSetSwitching( pNodeFpga, pSwitching[pNode->Id] );
}
/**Function*************************************************************
Synopsis [Transforms the AIG into nodes.]
Description [Threhold is the max number of nodes duplicated at a node.]
SideEffects []
SeeAlso []
***********************************************************************/
void Abc_NtkMultiInt( Abc_Ntk_t * pNtk, Abc_Ntk_t * pNtkNew )
{
ProgressBar * pProgress;
Abc_Obj_t * pNode, * pConst1, * pNodeNew;
int i;
// set the constant node
pConst1 = Abc_AigConst1(pNtk);
if ( Abc_ObjFanoutNum(pConst1) > 0 )
{
pNodeNew = Abc_NtkCreateNode( pNtkNew );
pNodeNew->pData = Cudd_ReadOne( pNtkNew->pManFunc ); Cudd_Ref( pNodeNew->pData );
pConst1->pCopy = pNodeNew;
}
// perform renoding for POs
pProgress = Extra_ProgressBarStart( stdout, Abc_NtkCoNum(pNtk) );
Abc_NtkForEachCo( pNtk, pNode, i )
{
Extra_ProgressBarUpdate( pProgress, i, NULL );
if ( Abc_ObjIsCi(Abc_ObjFanin0(pNode)) )
continue;
Abc_NtkMulti_rec( pNtkNew, Abc_ObjFanin0(pNode) );
}
/**Function*************************************************************
Synopsis [Load the network into manager.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
Map_Man_t * Abc_NtkToMap( Abc_Ntk_t * pNtk, double DelayTarget, int fRecovery, float * pSwitching, int fVerbose )
{
Map_Man_t * pMan;
Map_Node_t * pNodeMap;
Vec_Ptr_t * vNodes;
Abc_Obj_t * pNode, * pFanin, * pPrev;
int i;
assert( Abc_NtkIsStrash(pNtk) );
// start the mapping manager and set its parameters
pMan = Map_ManCreate( Abc_NtkPiNum(pNtk) + Abc_NtkLatchNum(pNtk) - pNtk->nBarBufs, Abc_NtkPoNum(pNtk) + Abc_NtkLatchNum(pNtk) - pNtk->nBarBufs, fVerbose );
if ( pMan == NULL )
return NULL;
Map_ManSetAreaRecovery( pMan, fRecovery );
Map_ManSetOutputNames( pMan, Abc_NtkCollectCioNames(pNtk, 1) );
Map_ManSetDelayTarget( pMan, (float)DelayTarget );
Map_ManSetInputArrivals( pMan, Abc_NtkMapCopyCiArrival(pNtk, Abc_NtkGetCiArrivalTimes(pNtk)) );
Map_ManSetOutputRequireds( pMan, Abc_NtkMapCopyCoRequired(pNtk, Abc_NtkGetCoRequiredTimes(pNtk)) );
// create PIs and remember them in the old nodes
Abc_NtkCleanCopy( pNtk );
Abc_AigConst1(pNtk)->pCopy = (Abc_Obj_t *)Map_ManReadConst1(pMan);
Abc_NtkForEachCi( pNtk, pNode, i )
{
if ( i == Abc_NtkCiNum(pNtk) - pNtk->nBarBufs )
break;
pNodeMap = Map_ManReadInputs(pMan)[i];
pNode->pCopy = (Abc_Obj_t *)pNodeMap;
if ( pSwitching )
Map_NodeSetSwitching( pNodeMap, pSwitching[pNode->Id] );
}
// load the AIG into the mapper
vNodes = Abc_AigDfsMap( pNtk );
Vec_PtrForEachEntry( Abc_Obj_t *, vNodes, pNode, i )
{
if ( Abc_ObjIsLatch(pNode) )
{
pFanin = Abc_ObjFanin0(pNode);
pNodeMap = Map_NodeBuf( pMan, Map_NotCond( Abc_ObjFanin0(pFanin)->pCopy, (int)Abc_ObjFaninC0(pFanin) ) );
Abc_ObjFanout0(pNode)->pCopy = (Abc_Obj_t *)pNodeMap;
continue;
}
assert( Abc_ObjIsNode(pNode) );
// add the node to the mapper
pNodeMap = Map_NodeAnd( pMan,
Map_NotCond( Abc_ObjFanin0(pNode)->pCopy, (int)Abc_ObjFaninC0(pNode) ),
Map_NotCond( Abc_ObjFanin1(pNode)->pCopy, (int)Abc_ObjFaninC1(pNode) ) );
assert( pNode->pCopy == NULL );
// remember the node
pNode->pCopy = (Abc_Obj_t *)pNodeMap;
if ( pSwitching )
Map_NodeSetSwitching( pNodeMap, pSwitching[pNode->Id] );
// set up the choice node
if ( Abc_AigNodeIsChoice( pNode ) )
for ( pPrev = pNode, pFanin = (Abc_Obj_t *)pNode->pData; pFanin; pPrev = pFanin, pFanin = (Abc_Obj_t *)pFanin->pData )
{
Map_NodeSetNextE( (Map_Node_t *)pPrev->pCopy, (Map_Node_t *)pFanin->pCopy );
Map_NodeSetRepr( (Map_Node_t *)pFanin->pCopy, (Map_Node_t *)pNode->pCopy );
}
}
assert( Map_ManReadBufNum(pMan) == pNtk->nBarBufs );
Vec_PtrFree( vNodes );
// set the primary outputs in the required phase
Abc_NtkForEachCo( pNtk, pNode, i )
{
if ( i == Abc_NtkCoNum(pNtk) - pNtk->nBarBufs )
break;
Map_ManReadOutputs(pMan)[i] = Map_NotCond( (Map_Node_t *)Abc_ObjFanin0(pNode)->pCopy, (int)Abc_ObjFaninC0(pNode) );
}
return pMan;
}
ABC_NAMESPACE_IMPL_START
////////////////////////////////////////////////////////////////////////
/// DECLARATIONS ///
////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////
/// FUNCTION DEFINITIONS ///
////////////////////////////////////////////////////////////////////////
/**Function*************************************************************
Synopsis [Starts the simulation manager.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
Sym_Man_t * Sym_ManStart( Abc_Ntk_t * pNtk, int fVerbose )
{
Sym_Man_t * p;
int i, v;
// start the manager
p = ABC_ALLOC( Sym_Man_t, 1 );
memset( p, 0, sizeof(Sym_Man_t) );
p->pNtk = pNtk;
p->vNodes = Abc_NtkDfs( pNtk, 0 );
p->nInputs = Abc_NtkCiNum(p->pNtk);
p->nOutputs = Abc_NtkCoNum(p->pNtk);
// internal simulation information
p->nSimWords = SIM_NUM_WORDS(p->nInputs);
p->vSim = Sim_UtilInfoAlloc( Abc_NtkObjNumMax(pNtk), p->nSimWords, 0 );
// symmetry info for each output
p->vMatrSymms = Vec_PtrStart( p->nOutputs );
p->vMatrNonSymms = Vec_PtrStart( p->nOutputs );
p->vPairsTotal = Vec_IntStart( p->nOutputs );
p->vPairsSym = Vec_IntStart( p->nOutputs );
p->vPairsNonSym = Vec_IntStart( p->nOutputs );
for ( i = 0; i < p->nOutputs; i++ )
{
p->vMatrSymms->pArray[i] = Extra_BitMatrixStart( p->nInputs );
p->vMatrNonSymms->pArray[i] = Extra_BitMatrixStart( p->nInputs );
}
// temporary patterns
p->uPatRand = ABC_ALLOC( unsigned, p->nSimWords );
p->uPatCol = ABC_ALLOC( unsigned, p->nSimWords );
p->uPatRow = ABC_ALLOC( unsigned, p->nSimWords );
p->vVarsU = Vec_IntStart( 100 );
p->vVarsV = Vec_IntStart( 100 );
// compute supports
p->vSuppFun = Sim_ComputeFunSupp( pNtk, fVerbose );
p->vSupports = Vec_VecStart( p->nOutputs );
for ( i = 0; i < p->nOutputs; i++ )
for ( v = 0; v < p->nInputs; v++ )
if ( Sim_SuppFunHasVar( p->vSuppFun, i, v ) )
Vec_VecPush( p->vSupports, i, (void *)(ABC_PTRUINT_T)v );
return p;
}
/**Function*************************************************************
Synopsis [Verifies sequential equivalence by fraiging followed by SAT.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
void Abc_NtkCecFraigPart( Abc_Ntk_t * pNtk1, Abc_Ntk_t * pNtk2, int nSeconds, int nPartSize, int fVerbose )
{
extern int Cmd_CommandExecute( void * pAbc, char * sCommand );
extern void * Abc_FrameGetGlobalFrame();
Prove_Params_t Params, * pParams = &Params;
Abc_Ntk_t * pMiter, * pMiterPart;
Abc_Obj_t * pObj;
int i, RetValue, Status, nOutputs;
// solve the CNF using the SAT solver
Prove_ParamsSetDefault( pParams );
pParams->nItersMax = 5;
// pParams->fVerbose = 1;
assert( nPartSize > 0 );
// get the miter of the two networks
pMiter = Abc_NtkMiter( pNtk1, pNtk2, 1, nPartSize );
if ( pMiter == NULL )
{
printf( "Miter computation has failed.\n" );
return;
}
RetValue = Abc_NtkMiterIsConstant( pMiter );
if ( RetValue == 0 )
{
printf( "Networks are NOT EQUIVALENT after structural hashing.\n" );
// report the error
pMiter->pModel = Abc_NtkVerifyGetCleanModel( pMiter, 1 );
Abc_NtkVerifyReportError( pNtk1, pNtk2, pMiter->pModel );
FREE( pMiter->pModel );
Abc_NtkDelete( pMiter );
return;
}
if ( RetValue == 1 )
{
printf( "Networks are equivalent after structural hashing.\n" );
Abc_NtkDelete( pMiter );
return;
}
Cmd_CommandExecute( Abc_FrameGetGlobalFrame(), "unset progressbar" );
// solve the problem iteratively for each output of the miter
Status = 1;
nOutputs = 0;
Abc_NtkForEachPo( pMiter, pObj, i )
{
if ( Abc_ObjFanin0(pObj) == Abc_AigConst1(pMiter) )
{
if ( Abc_ObjFaninC0(pObj) ) // complemented -> const 0
RetValue = 1;
else
RetValue = 0;
pMiterPart = NULL;
}
else
{
// get the cone of this output
pMiterPart = Abc_NtkCreateCone( pMiter, Abc_ObjFanin0(pObj), Abc_ObjName(pObj), 0 );
if ( Abc_ObjFaninC0(pObj) )
Abc_ObjXorFaninC( Abc_NtkPo(pMiterPart,0), 0 );
// solve the cone
// RetValue = Abc_NtkMiterProve( &pMiterPart, pParams );
RetValue = Abc_NtkIvyProve( &pMiterPart, pParams );
}
if ( RetValue == -1 )
{
printf( "Networks are undecided (resource limits is reached).\r" );
Status = -1;
}
else if ( RetValue == 0 )
{
int * pSimInfo = Abc_NtkVerifySimulatePattern( pMiterPart, pMiterPart->pModel );
if ( pSimInfo[0] != 1 )
printf( "ERROR in Abc_NtkMiterProve(): Generated counter-example is invalid.\n" );
else
printf( "Networks are NOT EQUIVALENT. \n" );
free( pSimInfo );
Status = 0;
break;
}
else
{
printf( "Finished part %d (out of %d)\r", i+1, Abc_NtkPoNum(pMiter) );
nOutputs += nPartSize;
}
// if ( pMiter->pModel )
// Abc_NtkVerifyReportError( pNtk1, pNtk2, pMiter->pModel );
if ( pMiterPart )
Abc_NtkDelete( pMiterPart );
}
Cmd_CommandExecute( Abc_FrameGetGlobalFrame(), "set progressbar" );
if ( Status == 1 )
printf( "Networks are equivalent. \n" );
else if ( Status == -1 )
printf( "Timed out after verifying %d outputs (out of %d).\n", nOutputs, Abc_NtkCoNum(pNtk1) );
Abc_NtkDelete( pMiter );
}
/**Function*************************************************************
Synopsis [Checks the integrity of the network.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
int Abc_NtkDoCheck( Abc_Ntk_t * pNtk )
{
Abc_Obj_t * pObj, * pNet, * pNode;
int i;
// check network types
if ( !Abc_NtkIsNetlist(pNtk) && !Abc_NtkIsLogic(pNtk) && !Abc_NtkIsStrash(pNtk) )
{
fprintf( stdout, "NetworkCheck: Unknown network type.\n" );
return 0;
}
if ( !Abc_NtkHasSop(pNtk) && !Abc_NtkHasBdd(pNtk) && !Abc_NtkHasAig(pNtk) && !Abc_NtkHasMapping(pNtk) && !Abc_NtkHasBlifMv(pNtk) && !Abc_NtkHasBlackbox(pNtk) )
{
fprintf( stdout, "NetworkCheck: Unknown functionality type.\n" );
return 0;
}
if ( Abc_NtkHasMapping(pNtk) )
{
if ( pNtk->pManFunc != Abc_FrameReadLibGen() )
{
fprintf( stdout, "NetworkCheck: The library of the mapped network is not the global library.\n" );
return 0;
}
}
if ( Abc_NtkHasOnlyLatchBoxes(pNtk) )
{
// check CI/CO numbers
if ( Abc_NtkPiNum(pNtk) + Abc_NtkLatchNum(pNtk) != Abc_NtkCiNum(pNtk) )
{
fprintf( stdout, "NetworkCheck: Number of CIs does not match number of PIs and latches.\n" );
fprintf( stdout, "One possible reason is that latches are added twice:\n" );
fprintf( stdout, "in procedure Abc_NtkCreateObj() and in the user's code.\n" );
return 0;
}
if ( Abc_NtkPoNum(pNtk) + Abc_NtkLatchNum(pNtk) != Abc_NtkCoNum(pNtk) )
{
fprintf( stdout, "NetworkCheck: Number of COs does not match number of POs, asserts, and latches.\n" );
fprintf( stdout, "One possible reason is that latches are added twice:\n" );
fprintf( stdout, "in procedure Abc_NtkCreateObj() and in the user's code.\n" );
return 0;
}
}
// check the names
if ( !Abc_NtkCheckNames( pNtk ) )
return 0;
// check PIs and POs
Abc_NtkCleanCopy( pNtk );
if ( !Abc_NtkCheckPis( pNtk ) )
return 0;
if ( !Abc_NtkCheckPos( pNtk ) )
return 0;
if ( Abc_NtkHasBlackbox(pNtk) )
return 1;
// check the connectivity of objects
Abc_NtkForEachObj( pNtk, pObj, i )
if ( !Abc_NtkCheckObj( pNtk, pObj ) )
return 0;
// if it is a netlist change nets and latches
if ( Abc_NtkIsNetlist(pNtk) )
{
if ( Abc_NtkNetNum(pNtk) == 0 )
fprintf( stdout, "NetworkCheck: Warning! Netlist has no nets.\n" );
// check the nets
Abc_NtkForEachNet( pNtk, pNet, i )
if ( !Abc_NtkCheckNet( pNtk, pNet ) )
return 0;
}
else
{
if ( Abc_NtkNetNum(pNtk) != 0 )