Esempio n. 1
0
/*-----------------------------------------------------------------------------
 * Function:	 initdram
 * Description:  Configures SDRAM memory banks for DDR operation.
 *		 Auto Memory Configuration option reads the DDR SDRAM EEPROMs
 *		 via the IIC bus and then configures the DDR SDRAM memory
 *		 banks appropriately. If Auto Memory Configuration is
 *		 not used, it is assumed that no DIMM is plugged
 *-----------------------------------------------------------------------------*/
phys_size_t initdram(int board_type)
{
	unsigned char const iic0_dimm_addr[] = SPD_EEPROM_ADDRESS;
	unsigned long dimm_ranks[MAXDIMMS];
	unsigned long ranks;
	unsigned long rows;
	unsigned long banks;
	unsigned long cols;
	unsigned long width;
	unsigned long const sdram_freq = get_bus_freq(0);
	unsigned long const num_dimm_banks = sizeof(iic0_dimm_addr);	/* on board dimm banks */
	unsigned long cas_latency = 0;	/* to quiet initialization warning */
	unsigned long dram_size;

	debug("\nEntering initdram()\n");

	/*------------------------------------------------------------------
	 * Stop the DDR-SDRAM controller.
	 *-----------------------------------------------------------------*/
	mtsdram(DDR0_02, DDR0_02_START_ENCODE(0));

	/*
	 * Make sure I2C controller is initialized
	 * before continuing.
	 */
	/* switch to correct I2C bus */
	I2C_SET_BUS(CONFIG_SYS_SPD_BUS_NUM);
	i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);

	/*------------------------------------------------------------------
	 * Clear out the serial presence detect buffers.
	 * Perform IIC reads from the dimm.  Fill in the spds.
	 * Check to see if the dimm slots are populated
	 *-----------------------------------------------------------------*/
	get_spd_info(dimm_ranks, &ranks, iic0_dimm_addr, num_dimm_banks);

	/*------------------------------------------------------------------
	 * Check the frequency supported for the dimms plugged.
	 *-----------------------------------------------------------------*/
	check_frequency(dimm_ranks, iic0_dimm_addr, num_dimm_banks, sdram_freq);

	/*------------------------------------------------------------------
	 * Check and get size information.
	 *-----------------------------------------------------------------*/
	get_dimm_size(dimm_ranks, iic0_dimm_addr, num_dimm_banks, &rows, &banks,
		      &cols, &width);

	/*------------------------------------------------------------------
	 * Check the voltage type for the dimms plugged.
	 *-----------------------------------------------------------------*/
	check_voltage_type(dimm_ranks, iic0_dimm_addr, num_dimm_banks);

	/*------------------------------------------------------------------
	 * Program registers for SDRAM controller.
	 *-----------------------------------------------------------------*/
	mtsdram(DDR0_00, DDR0_00_DLL_INCREMENT_ENCODE(0x19) |
		DDR0_00_DLL_START_POINT_DECODE(0x0A));

	mtsdram(DDR0_01, DDR0_01_PLB0_DB_CS_LOWER_ENCODE(0x01) |
		DDR0_01_PLB0_DB_CS_UPPER_ENCODE(0x00) |
		DDR0_01_INT_MASK_ENCODE(0xFF));

	program_ddr0_03(dimm_ranks, iic0_dimm_addr, num_dimm_banks, sdram_freq,
			rows, &cas_latency);

	program_ddr0_04(dimm_ranks, iic0_dimm_addr, num_dimm_banks, sdram_freq);

	program_ddr0_05(dimm_ranks, iic0_dimm_addr, num_dimm_banks, sdram_freq);

	program_ddr0_06(dimm_ranks, iic0_dimm_addr, num_dimm_banks, sdram_freq);

	/*
	 * TODO: tFAW not found in SPD.  Value of 13 taken from Sequoia
	 * board SDRAM, but may be overly conservative.
	 */
	mtsdram(DDR0_07, DDR0_07_NO_CMD_INIT_ENCODE(0) |
		DDR0_07_TFAW_ENCODE(13) |
		DDR0_07_AUTO_REFRESH_MODE_ENCODE(1) |
		DDR0_07_AREFRESH_ENCODE(0));

	mtsdram(DDR0_08, DDR0_08_WRLAT_ENCODE(cas_latency - 1) |
		DDR0_08_TCPD_ENCODE(200) | DDR0_08_DQS_N_EN_ENCODE(0) |
		DDR0_08_DDRII_ENCODE(1));

	mtsdram(DDR0_09, DDR0_09_OCD_ADJUST_PDN_CS_0_ENCODE(0x00) |
		DDR0_09_RTT_0_ENCODE(0x1) |
		DDR0_09_WR_DQS_SHIFT_BYPASS_ENCODE(0x1D) |
		DDR0_09_WR_DQS_SHIFT_ENCODE(DQS_OUT_SHIFT - 0x20));

	program_ddr0_10(dimm_ranks, ranks);

	program_ddr0_11(sdram_freq);

	mtsdram(DDR0_12, DDR0_12_TCKE_ENCODE(3));

	mtsdram(DDR0_14, DDR0_14_DLL_BYPASS_MODE_ENCODE(0) |
		DDR0_14_REDUC_ENCODE(width <= 40 ? 1 : 0) |
		DDR0_14_REG_DIMM_ENABLE_ENCODE(0));

	mtsdram(DDR0_17, DDR0_17_DLL_DQS_DELAY_0_ENCODE(DLL_DQS_DELAY));

	mtsdram(DDR0_18, DDR0_18_DLL_DQS_DELAY_4_ENCODE(DLL_DQS_DELAY) |
		DDR0_18_DLL_DQS_DELAY_3_ENCODE(DLL_DQS_DELAY) |
		DDR0_18_DLL_DQS_DELAY_2_ENCODE(DLL_DQS_DELAY) |
		DDR0_18_DLL_DQS_DELAY_1_ENCODE(DLL_DQS_DELAY));

	mtsdram(DDR0_19, DDR0_19_DLL_DQS_DELAY_8_ENCODE(DLL_DQS_DELAY) |
		DDR0_19_DLL_DQS_DELAY_7_ENCODE(DLL_DQS_DELAY) |
		DDR0_19_DLL_DQS_DELAY_6_ENCODE(DLL_DQS_DELAY) |
		DDR0_19_DLL_DQS_DELAY_5_ENCODE(DLL_DQS_DELAY));

	mtsdram(DDR0_20, DDR0_20_DLL_DQS_BYPASS_3_ENCODE(DLL_DQS_BYPASS) |
		DDR0_20_DLL_DQS_BYPASS_2_ENCODE(DLL_DQS_BYPASS) |
		DDR0_20_DLL_DQS_BYPASS_1_ENCODE(DLL_DQS_BYPASS) |
		DDR0_20_DLL_DQS_BYPASS_0_ENCODE(DLL_DQS_BYPASS));

	mtsdram(DDR0_21, DDR0_21_DLL_DQS_BYPASS_7_ENCODE(DLL_DQS_BYPASS) |
		DDR0_21_DLL_DQS_BYPASS_6_ENCODE(DLL_DQS_BYPASS) |
		DDR0_21_DLL_DQS_BYPASS_5_ENCODE(DLL_DQS_BYPASS) |
		DDR0_21_DLL_DQS_BYPASS_4_ENCODE(DLL_DQS_BYPASS));

	program_ddr0_22(dimm_ranks, iic0_dimm_addr, num_dimm_banks, width);

	mtsdram(DDR0_23, DDR0_23_ODT_RD_MAP_CS0_ENCODE(0x0) |
		DDR0_23_FWC_ENCODE(0));

	program_ddr0_24(ranks);

	program_ddr0_26(sdram_freq);

	program_ddr0_27(sdram_freq);

	mtsdram(DDR0_28, DDR0_28_EMRS3_DATA_ENCODE(0x0000) |
		DDR0_28_EMRS2_DATA_ENCODE(0x0000));

	mtsdram(DDR0_31, DDR0_31_XOR_CHECK_BITS_ENCODE(0x0000));

	mtsdram(DDR0_42, DDR0_42_ADDR_PINS_DECODE(14 - rows) |
		DDR0_42_CASLAT_LIN_GATE_ENCODE(2 * cas_latency));

	program_ddr0_43(dimm_ranks, iic0_dimm_addr, num_dimm_banks, sdram_freq,
			cols, banks);

	program_ddr0_44(dimm_ranks, iic0_dimm_addr, num_dimm_banks, sdram_freq);

	denali_sdram_register_dump();

	dram_size = (width >= 64) ? 8 : 4;
	dram_size *= 1 << cols;
	dram_size *= banks;
	dram_size *= 1 << rows;
	dram_size *= ranks;
	debug("dram_size = %lu\n", dram_size);

	/* Start the SDRAM controler */
	mtsdram(DDR0_02, DDR0_02_START_ENCODE(1));
	denali_wait_for_dlllock();

#if defined(CONFIG_DDR_DATA_EYE)
	/*
	 * Map the first 1 MiB of memory in the TLB, and perform the data eye
	 * search.
	 */
	program_tlb(0, CONFIG_SYS_SDRAM_BASE, TLB_1MB_SIZE, TLB_WORD2_I_ENABLE);
	denali_core_search_data_eye();
	denali_sdram_register_dump();
	remove_tlb(CONFIG_SYS_SDRAM_BASE, TLB_1MB_SIZE);
#endif

#if defined(CONFIG_ZERO_SDRAM) || defined(CONFIG_DDR_ECC)
	program_tlb(0, CONFIG_SYS_SDRAM_BASE, dram_size, 0);
	sync();
	/* Zero the memory */
	debug("Zeroing SDRAM...");
#if defined(CONFIG_SYS_MEM_TOP_HIDE)
	dcbz_area(CONFIG_SYS_SDRAM_BASE, dram_size - CONFIG_SYS_MEM_TOP_HIDE);
#else
#error Please define CONFIG_SYS_MEM_TOP_HIDE (see README) in your board config file
#endif
	/* Write modified dcache lines back to memory */
	clean_dcache_range(CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_SDRAM_BASE + dram_size - CONFIG_SYS_MEM_TOP_HIDE);
	debug("Completed\n");
	sync();
	remove_tlb(CONFIG_SYS_SDRAM_BASE, dram_size);

#if defined(CONFIG_DDR_ECC)
	/*
	 * If ECC is enabled, clear and enable interrupts
	 */
	if (is_ecc_enabled()) {
		u32 val;

		sync();
		/* Clear error status */
		mfsdram(DDR0_00, val);
		mtsdram(DDR0_00, val | DDR0_00_INT_ACK_ALL);
		/* Set 'int_mask' parameter to functionnal value */
		mfsdram(DDR0_01, val);
		mtsdram(DDR0_01, (val & ~DDR0_01_INT_MASK_MASK) |
			DDR0_01_INT_MASK_ALL_OFF);
#if defined(CONFIG_DDR_DATA_EYE)
		/*
		 * Running denali_core_search_data_eye() when ECC is enabled
		 * causes non-ECC machine checks.  This clears them.
		 */
		print_mcsr();
		mtspr(SPRN_MCSR, mfspr(SPRN_MCSR));
		print_mcsr();
#endif
		sync();
	}
#endif /* defined(CONFIG_DDR_ECC) */
#endif /* defined(CONFIG_ZERO_SDRAM) || defined(CONFIG_DDR_ECC) */

	program_tlb(0, CONFIG_SYS_SDRAM_BASE, dram_size, MY_TLB_WORD2_I_ENABLE);
	return dram_size;
}
Esempio n. 2
0
/*************************************************************************
 *
 * initdram -- 440EPx's DDR controller is a DENALI Core
 *
 ************************************************************************/
phys_size_t initdram (int board_type)
{
	unsigned char data[2];
	unsigned int chip, v, t, i, x, sz, ms, rr, rf, st;
	unsigned long speed;
	unsigned char mt, bl, cl, rk, tmp; /* memory type, burst length, cas latency, ranks */
	unsigned char map[3] = { SPD_TAC0, SPD_TAC1, SPD_TAC2 };
#ifdef DEBUG
	unsigned int j;
#endif

	chip = SPD_EEPROM_ADDRESS;

	debug("dram: about to probe chip 0x%x\n", chip);

	if(check_sane_spd(chip)){
		printf("dram: nonexistent or unusable spd eeprom\n");
		hang();
	}

#ifdef DEBUG
	debug("dram: raw");
	for(j = 0; j < 64; j++){
		if(i2c_read(chip, j, 1, data, 1) == 0){
			debug("%c%02x", (j % 16) ? ' ' : '\n', data[0]);
		}
	}
	debug("\n");
#endif

	/* rushed dump from spd to ddr controller, calculations hardwired from sequoia and generally iffy */

	if(i2c_read(chip, SPD_MEMORY_TYPE, 1, data, 1) != 0){
		return 0;
	}
	mt = data[0];

	switch(mt){
		case SPD_MEMORY_TYPE_DDR2_SDRAM :
			debug("dram: ddr2 memory\n");
			break;
		/* case SPD_MEMORY_TYPE_DDR_SDRAM  : */
		default :
			printf("dram: unsupported memory type 0x%x\n", mt);
			return 0;
	}

	speed = get_bus_freq(0);
	debug("dram: bus speed %luHz\n", speed);

	if(i2c_read(chip, SPD_REFRESH_RATE, 1, data, 1) != 0){
		return 0;
	}
	rr = decode_refresh(data[0]);
	debug("dram: refresh rate %ups\n", rr);

	xmtsdram(DDR0_02, DDR0_02_START_OFF);
	mfsdram(DDR0_02, ms);
	/* gives us the maximum dimensions the controller can do, used later */
	debug("dram: controller caps 0x%08x\n", ms);

	/* calibration values as recommended */
	xmtsdram(DDR0_00, DDR0_00_DLL_INCREMENT_ENCODE(0x19) | DDR0_00_DLL_START_POINT_ENCODE(0xa));

	/* set as required, possibly could set up interrupt masks */
	xmtsdram(DDR0_01, DDR0_01_PLB0_DB_CS_LOWER_ENCODE(0x1) | DDR0_01_PLB0_DB_CS_UPPER_ENCODE(0));

	v = 0;
	v |= DDR0_03_INITAREF_ENCODE(0x2); /* WARNING: no idea how many autorefresh commands needed during initialisation */
	if(i2c_read(chip, SPD_BURST_LENGTHS, 1, data, 1) != 0){
		return 0;
	}
	bl = ((mt != SPD_MEMORY_TYPE_DDR2_SDRAM) && (data[0] & SPD_BURST_LENGTH_8)) ? 8 : 4;
	debug("dram: burst length caps=0x%x, chosen=%d\n", data[0], bl);
	v |= DDR0_03_BSTLEN_ENCODE((bl == 8) ? 0x3 : 0x2);
	if(i2c_read(chip, SPD_CAS_LATENCIES, 1, data, 1) != 0){
		return 0;
	}
	cl = 0;
	tmp = data[0];
	debug("dram: latency choices 0x%x\n", tmp);
	/* could use a less agressive mode by quitting for a lower x */
	for(i = 7, x = 0; (i >= 2) && (x < 3); i--){
		if(tmp & (0x1 << i)){
			debug("dram: can do cl=%d\n", i);
			if(i2c_read(chip, map[x] + 1, 1, data, 1) != 0){
				return 0;
			}
			t = ps2cycles(speed, (((data[0] >> 4) & 0xf) * 100) + ((data[0] & 0xf) * 10), "minclock");
			if(t > 0){
				debug("dram: clock too fast for cl-%d\n", x);
				break;
			}
			cl = i;
			x++;
		}
	}