int8 platform_init(void)
{
int8 ret8;
uint32 retu32;
uint8 tx_size[8]={2, 2, 2, 2, 2, 2, 2, 2}; // Device default memory setting
uint8 rx_size[8]={2, 2, 2, 2, 2, 2, 2, 2};
RCC_Configuration(); // Configure the system clocks
GPIO_Configuration(); // Configure GPIO Pin setting
NVIC_Configuration(); // Configure the vector table
retu32 = SysTick_Config(SystemCoreClock/SYSTICK_HZ); // SysTick Configuration - 1ms
if(retu32 != 0) return RET_NOK;
ret8 = wizpf_uart_init(WIZ_USART1);
if(ret8 != RET_OK) return RET_NOK;
ret8 = wizspi_init(WIZ_SPI1);
if(ret8 != RET_OK) {
ERR("wizspi_init fail");
return RET_NOK;
}
device_HW_reset();
DEVICE_INIT_WITH_MEMCHK(tx_size, rx_size);
wizpf_led_set(WIZ_LED1, VAL_ON); // LED3 and LED4 On by default
wizpf_led_set(WIZ_LED2, VAL_ON);
return RET_OK;
}
int8 platform_init(usart_param *up)
{
int8 ret8;
uint32 retu32;
usart_param up_tmp;
uint8 tx_size[8]={2, 2, 2, 2, 2, 2, 2, 2}; // Device default memory setting
uint8 rx_size[8]={2, 2, 2, 2, 2, 2, 2, 2};
RCC_Configuration(); // Configure the system clocks
GPIO_Configuration(); // Configure GPIO Pin setting
NVIC_Configuration(); // Configure the vector table
retu32 = SysTick_Config(SystemCoreClock/SYSTICK_HZ); // SysTick Configuration - 1ms
if(retu32 != 0) return RET_NOK;
if(up == NULL) {
WIZPF_USART_SET_PARAM(&up_tmp, UBR_115200, UWL_8, UST_1, UPB_NO, UFC_NO);
up = &up_tmp;
}
ret8 = wizpf_usart_init(WIZ_USART1, up);
if(ret8 != RET_OK) return RET_NOK;
//ret8 = wizspi_init(WIZ_SPI1);
ret8 = wizspi_init(WIZ_SPI2); // For W5500 FPGA board
if(ret8 != RET_OK) {
ERR("wizspi_init fail");
return RET_NOK;
}
device_HW_reset();
DEVICE_INIT_WITH_MEMCHK(tx_size, rx_size);
wizpf_led_set(WIZ_LED1, VAL_ON); // LED3 and LED4 On by default
wizpf_led_set(WIZ_LED2, VAL_ON);
return RET_OK;
}