Esempio n. 1
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	}

	rv = 0;
out:
	return rv;
}

/*
 * Configuration table for pins used for same functions on both TWR-K70F120M
 * and K70-SOM. The LCD signals are excluded from this tables, because they may
 * change depending on the LCD type.
 */
static const struct kinetis_gpio_pin_config common_iomux[] = {
#if defined(CONFIG_I2C_GPIO) || defined(CONFIG_I2C_GPIO_MODULE)
	/* E.18 = GPIO (for I2C_SDA) */
	{{KINETIS_GPIO_PORT_E, 18}, KINETIS_GPIO_CONFIG_MUX(1)},
	/* E.19 = GPIO (for I2C_SCL) */
	{{KINETIS_GPIO_PORT_E, 19}, KINETIS_GPIO_CONFIG_MUX(1)},
#endif /* defined(CONFIG_I2C_GPIO) || defined(CONFIG_I2C_GPIO_MODULE) */

#if defined(CONFIG_USB_EHCI_MXC) || defined(CONFIG_USB_EHCI_MXC_MODULE)
	/* A.6 = ULPI_CLK */
	{{KINETIS_GPIO_PORT_A, 6}, KINETIS_GPIO_CONFIG_MUX(2)},
	/* A.7 = ULPI_DIR */
	{{KINETIS_GPIO_PORT_A, 7}, KINETIS_GPIO_CONFIG_MUX(2)},
	/* A.8 = ULPI_NXT */
	{{KINETIS_GPIO_PORT_A, 8}, KINETIS_GPIO_CONFIG_MUX(2)},
	/* A.9 = ULPI_STP */
	{{KINETIS_GPIO_PORT_A, 9}, KINETIS_GPIO_CONFIG_MUX(2)},
	/* A.10 = ULPI_DATA0 */
	{{KINETIS_GPIO_PORT_A, 10}, KINETIS_GPIO_CONFIG_MUX(2)},
Esempio n. 2
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 * GPIO pin configuration table for TWR-K70F120M
 *
 * This table does not list all GPIO pins that will be configured. See also
 * the code in `gpio_init()` and in the drivers (for example, the UART driver).
 */
static const struct kinetis_gpio_pin_config twr_k70f120m_gpio[] = {
#ifdef CONFIG_MCFFEC
	/* A.5 = RMII0_RXER */
	/*
	 * The pull-down resistor is not really necessary here, because this
	 * pin is always connected to the PHY (it is not connected by default
	 * on the TWR-K60N512 board.)
	 */
	{{KINETIS_GPIO_PORT_A,  5}, KINETIS_GPIO_CONFIG_PULLDOWN(4)},
	/* A.12 = RMII0_RXD1 */
	{{KINETIS_GPIO_PORT_A, 12}, KINETIS_GPIO_CONFIG_MUX(4)},
	/* A.13 = RMII0_RXD0 */
	{{KINETIS_GPIO_PORT_A, 13}, KINETIS_GPIO_CONFIG_MUX(4)},
	/* A.14 = RMII0_CRS_DV */
	{{KINETIS_GPIO_PORT_A, 14}, KINETIS_GPIO_CONFIG_MUX(4)},
	/* A.15 = RMII0_TXEN */
	{{KINETIS_GPIO_PORT_A, 15}, KINETIS_GPIO_CONFIG_MUX(4)},
	/* A.16 = RMII0_TXD0 */
	{{KINETIS_GPIO_PORT_A, 16}, KINETIS_GPIO_CONFIG_MUX(4)},
	/* A.17 = RMII0_TXD1 */
	{{KINETIS_GPIO_PORT_A, 17}, KINETIS_GPIO_CONFIG_MUX(4)},
	/* B.0 = RMII0_MDIO */
	{{KINETIS_GPIO_PORT_B,  0}, KINETIS_GPIO_CONFIG_MUX(4)},
	/* B.1 = RMII0_MDC */
	{{KINETIS_GPIO_PORT_B,  1}, KINETIS_GPIO_CONFIG_MUX(4)},
#endif /* CONFIG_MCFFEC */