void __init imx27_init_early(void) { mxc_set_cpu_type(MXC_CPU_MX27); mxc_arch_reset_init(MX27_IO_ADDRESS(MX27_WDOG_BASE_ADDR)); imx_iomuxv1_init(MX27_IO_ADDRESS(MX27_GPIO_BASE_ADDR), MX27_NUM_GPIO_PORT); }
static int mx27_suspend_enter(suspend_state_t state) { u32 cscr; switch (state) { case PM_SUSPEND_MEM: /* Clear MPEN and SPEN to disable MPLL/SPLL */ cscr = imx_readl(MX27_IO_ADDRESS(MX27_CCM_BASE_ADDR)); cscr &= 0xFFFFFFFC; imx_writel(cscr, MX27_IO_ADDRESS(MX27_CCM_BASE_ADDR)); /* Executes WFI */ cpu_do_idle(); break; default: return -EINVAL; } return 0; }
int mx27_initialize_usb_hw(int port, unsigned int flags) { unsigned int v; v = readl(MX27_IO_ADDRESS(MX27_USB_BASE_ADDR + USBCTRL_OTGBASE_OFFSET)); switch (port) { case 0: /* OTG port */ v &= ~(MX27_OTG_SIC_MASK | MX27_OTG_PM_BIT); v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX27_OTG_SIC_SHIFT; if (!(flags & MXC_EHCI_POWER_PINS_ENABLED)) v |= MX27_OTG_PM_BIT; break; case 1: /* H1 port */ v &= ~(MX27_H1_SIC_MASK | MX27_H1_PM_BIT | MX27_H1_DT_BIT); v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX27_H1_SIC_SHIFT; if (!(flags & MXC_EHCI_POWER_PINS_ENABLED)) v |= MX27_H1_PM_BIT; if (!(flags & MXC_EHCI_TTL_ENABLED)) v |= MX27_H1_DT_BIT; break; case 2: /* H2 port */ v &= ~(MX27_H2_SIC_MASK | MX27_H2_PM_BIT | MX27_H2_DT_BIT); v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX27_H2_SIC_SHIFT; if (!(flags & MXC_EHCI_POWER_PINS_ENABLED)) v |= MX27_H2_PM_BIT; if (!(flags & MXC_EHCI_TTL_ENABLED)) v |= MX27_H2_DT_BIT; break; default: return -EINVAL; } writel(v, MX27_IO_ADDRESS(MX27_USB_BASE_ADDR + USBCTRL_OTGBASE_OFFSET)); return 0; }
static int mxc_audmux_v1_init(void) { #ifdef CONFIG_MACH_MX21 if (cpu_is_mx21()) audmux_base = MX21_IO_ADDRESS(MX21_AUDMUX_BASE_ADDR); else #endif #ifdef CONFIG_MACH_MX27 if (cpu_is_mx27()) audmux_base = MX27_IO_ADDRESS(MX27_AUDMUX_BASE_ADDR); else #endif (void)0; return 0; }
void __init imx27_soc_init(void) { mxc_arch_reset_init(MX27_IO_ADDRESS(MX27_WDOG_BASE_ADDR)); mxc_device_init(); /* i.mx27 has the i.mx21 type gpio */ mxc_register_gpio("imx21-gpio", 0, MX27_GPIO1_BASE_ADDR, SZ_256, MX27_INT_GPIO, 0); mxc_register_gpio("imx21-gpio", 1, MX27_GPIO2_BASE_ADDR, SZ_256, MX27_INT_GPIO, 0); mxc_register_gpio("imx21-gpio", 2, MX27_GPIO3_BASE_ADDR, SZ_256, MX27_INT_GPIO, 0); mxc_register_gpio("imx21-gpio", 3, MX27_GPIO4_BASE_ADDR, SZ_256, MX27_INT_GPIO, 0); mxc_register_gpio("imx21-gpio", 4, MX27_GPIO5_BASE_ADDR, SZ_256, MX27_INT_GPIO, 0); mxc_register_gpio("imx21-gpio", 5, MX27_GPIO6_BASE_ADDR, SZ_256, MX27_INT_GPIO, 0); pinctrl_provide_dummies(); imx_add_imx_dma("imx27-dma", MX27_DMA_BASE_ADDR, MX27_INT_DMACH0, 0); /* No ERR irq */ /* imx27 has the imx21 type audmux */ platform_device_register_simple("imx21-audmux", 0, imx27_audmux_res, ARRAY_SIZE(imx27_audmux_res)); imx27_pm_init(); }
static int imx_iomuxv1_init(void) { #ifdef CONFIG_ARCH_MX1 if (cpu_is_mx1()) { imx_iomuxv1_baseaddr = MX1_IO_ADDRESS(MX1_GPIO_BASE_ADDR); imx_iomuxv1_numports = MX1_NUM_GPIO_PORT; } else #endif #ifdef CONFIG_MACH_MX21 if (cpu_is_mx21()) { imx_iomuxv1_baseaddr = MX21_IO_ADDRESS(MX21_GPIO_BASE_ADDR); imx_iomuxv1_numports = MX21_NUM_GPIO_PORT; } else #endif #ifdef CONFIG_MACH_MX27 if (cpu_is_mx27()) { imx_iomuxv1_baseaddr = MX27_IO_ADDRESS(MX27_GPIO_BASE_ADDR); imx_iomuxv1_numports = MX27_NUM_GPIO_PORT; } else #endif return -ENODEV; return 0; }
/* On pcm038 there's a sram attached to CS1, we enable the chipselect here and * setup other stuffs to access the sram. */ static void __init pcm038_init_sram(void) { __raw_writel(0x0000d843, MX27_IO_ADDRESS(MX27_WEIM_CSCRxU(1))); __raw_writel(0x22252521, MX27_IO_ADDRESS(MX27_WEIM_CSCRxL(1))); __raw_writel(0x22220a00, MX27_IO_ADDRESS(MX27_WEIM_CSCRxA(1))); }
int mxc_initialize_usb_hw(int port, unsigned int flags) { unsigned int v; #if defined(CONFIG_ARCH_MX25) if (cpu_is_mx25()) { v = readl(MX25_IO_ADDRESS(MX25_OTG_BASE_ADDR + USBCTRL_OTGBASE_OFFSET)); switch (port) { case 0: /* OTG port */ v &= ~(MX35_OTG_SIC_MASK | MX35_OTG_PM_BIT); v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX35_OTG_SIC_SHIFT; if (!(flags & MXC_EHCI_POWER_PINS_ENABLED)) v |= MX35_OTG_PM_BIT; break; case 1: /* H1 port */ v &= ~(MX35_H1_SIC_MASK | MX35_H1_PM_BIT | MX35_H1_TLL_BIT | MX35_H1_USBTE_BIT | MX35_H1_IPPUE_DOWN_BIT | MX35_H1_IPPUE_UP_BIT); v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX35_H1_SIC_SHIFT; if (!(flags & MXC_EHCI_POWER_PINS_ENABLED)) v |= MX35_H1_PM_BIT; if (!(flags & MXC_EHCI_TTL_ENABLED)) v |= MX35_H1_TLL_BIT; if (flags & MXC_EHCI_INTERNAL_PHY) v |= MX35_H1_USBTE_BIT; if (flags & MXC_EHCI_IPPUE_DOWN) v |= MX35_H1_IPPUE_DOWN_BIT; if (flags & MXC_EHCI_IPPUE_UP) v |= MX35_H1_IPPUE_UP_BIT; break; default: return -EINVAL; } writel(v, MX25_IO_ADDRESS(MX25_OTG_BASE_ADDR + USBCTRL_OTGBASE_OFFSET)); return 0; } #endif /* CONFIG_ARCH_MX25 */ #if defined(CONFIG_ARCH_MX3) if (cpu_is_mx31()) { v = readl(MX31_IO_ADDRESS(MX31_OTG_BASE_ADDR + USBCTRL_OTGBASE_OFFSET)); switch (port) { case 0: /* OTG port */ v &= ~(MX31_OTG_SIC_MASK | MX31_OTG_PM_BIT); v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX31_OTG_SIC_SHIFT; if (!(flags & MXC_EHCI_POWER_PINS_ENABLED)) v |= MX31_OTG_PM_BIT; break; case 1: /* H1 port */ v &= ~(MX31_H1_SIC_MASK | MX31_H1_PM_BIT | MX31_H1_DT_BIT); v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX31_H1_SIC_SHIFT; if (!(flags & MXC_EHCI_POWER_PINS_ENABLED)) v |= MX31_H1_PM_BIT; if (!(flags & MXC_EHCI_TTL_ENABLED)) v |= MX31_H1_DT_BIT; break; case 2: /* H2 port */ v &= ~(MX31_H2_SIC_MASK | MX31_H2_PM_BIT | MX31_H2_DT_BIT); v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX31_H2_SIC_SHIFT; if (!(flags & MXC_EHCI_POWER_PINS_ENABLED)) v |= MX31_H2_PM_BIT; if (!(flags & MXC_EHCI_TTL_ENABLED)) v |= MX31_H2_DT_BIT; break; default: return -EINVAL; } writel(v, MX31_IO_ADDRESS(MX31_OTG_BASE_ADDR + USBCTRL_OTGBASE_OFFSET)); return 0; } if (cpu_is_mx35()) { v = readl(MX35_IO_ADDRESS(MX35_OTG_BASE_ADDR + USBCTRL_OTGBASE_OFFSET)); switch (port) { case 0: /* OTG port */ v &= ~(MX35_OTG_SIC_MASK | MX35_OTG_PM_BIT); v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX35_OTG_SIC_SHIFT; if (!(flags & MXC_EHCI_POWER_PINS_ENABLED)) v |= MX35_OTG_PM_BIT; break; case 1: /* H1 port */ v &= ~(MX35_H1_SIC_MASK | MX35_H1_PM_BIT | MX35_H1_TLL_BIT | MX35_H1_USBTE_BIT | MX35_H1_IPPUE_DOWN_BIT | MX35_H1_IPPUE_UP_BIT); v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX35_H1_SIC_SHIFT; if (!(flags & MXC_EHCI_POWER_PINS_ENABLED)) v |= MX35_H1_PM_BIT; if (!(flags & MXC_EHCI_TTL_ENABLED)) v |= MX35_H1_TLL_BIT; if (flags & MXC_EHCI_INTERNAL_PHY) v |= MX35_H1_USBTE_BIT; if (flags & MXC_EHCI_IPPUE_DOWN) v |= MX35_H1_IPPUE_DOWN_BIT; if (flags & MXC_EHCI_IPPUE_UP) v |= MX35_H1_IPPUE_UP_BIT; break; default: return -EINVAL; } writel(v, MX35_IO_ADDRESS(MX35_OTG_BASE_ADDR + USBCTRL_OTGBASE_OFFSET)); return 0; } #endif /* CONFIG_ARCH_MX3 */ #ifdef CONFIG_MACH_MX27 if (cpu_is_mx27()) { /* On i.MX27 we can use the i.MX31 USBCTRL bits, they * are identical */ v = readl(MX27_IO_ADDRESS(MX27_OTG_BASE_ADDR + USBCTRL_OTGBASE_OFFSET)); switch (port) { case 0: /* OTG port */ v &= ~(MX31_OTG_SIC_MASK | MX31_OTG_PM_BIT); v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX31_OTG_SIC_SHIFT; if (!(flags & MXC_EHCI_POWER_PINS_ENABLED)) v |= MX31_OTG_PM_BIT; break; case 1: /* H1 port */ v &= ~(MX31_H1_SIC_MASK | MX31_H1_PM_BIT | MX31_H1_DT_BIT); v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX31_H1_SIC_SHIFT; if (!(flags & MXC_EHCI_POWER_PINS_ENABLED)) v |= MX31_H1_PM_BIT; if (!(flags & MXC_EHCI_TTL_ENABLED)) v |= MX31_H1_DT_BIT; break; case 2: /* H2 port */ v &= ~(MX31_H2_SIC_MASK | MX31_H2_PM_BIT | MX31_H2_DT_BIT); v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX31_H2_SIC_SHIFT; if (!(flags & MXC_EHCI_POWER_PINS_ENABLED)) v |= MX31_H2_PM_BIT; if (!(flags & MXC_EHCI_TTL_ENABLED)) v |= MX31_H2_DT_BIT; break; default: return -EINVAL; } writel(v, MX27_IO_ADDRESS(MX27_OTG_BASE_ADDR + USBCTRL_OTGBASE_OFFSET)); return 0; } #endif /* CONFIG_MACH_MX27 */ #ifdef CONFIG_ARCH_MX51 if (cpu_is_mx51()) { void __iomem *usb_base; u32 usbotg_base; u32 usbother_base; int ret = 0; usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K); switch (port) { case 0: /* OTG port */ usbotg_base = usb_base + MXC_OTG_OFFSET; break; case 1: /* Host 1 port */ usbotg_base = usb_base + MXC_H1_OFFSET; break; default: printk(KERN_ERR"%s no such port %d\n", __func__, port); ret = -ENOENT; goto error; } usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET; switch (port) { case 0: /*OTG port */ if (flags & MXC_EHCI_INTERNAL_PHY) { v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET); if (flags & MXC_EHCI_POWER_PINS_ENABLED) v |= (MXC_OTG_PHYCTRL_OC_DIS_BIT | MXC_OTG_UCTRL_OPM_BIT); /* OC/USBPWR is not used */ else v &= ~(MXC_OTG_PHYCTRL_OC_DIS_BIT | MXC_OTG_UCTRL_OPM_BIT); /* OC/USBPWR is used */ __raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET); v = __raw_readl(usbother_base + MXC_USBCTRL_OFFSET); if (flags & MXC_EHCI_WAKEUP_ENABLED) v |= MXC_OTG_UCTRL_OWIE_BIT;/* OTG wakeup enable */ else v &= ~MXC_OTG_UCTRL_OWIE_BIT;/* OTG wakeup disable */ __raw_writel(v, usbother_base + MXC_USBCTRL_OFFSET); } break; case 1: /* Host 1 */ /*Host ULPI */ v = __raw_readl(usbother_base + MXC_USBCTRL_OFFSET); if (flags & MXC_EHCI_WAKEUP_ENABLED) v &= ~(MXC_H1_UCTRL_H1WIE_BIT | MXC_H1_UCTRL_H1UIE_BIT);/* HOST1 wakeup/ULPI intr disable */ else v &= ~(MXC_H1_UCTRL_H1WIE_BIT | MXC_H1_UCTRL_H1UIE_BIT);/* HOST1 wakeup/ULPI intr disable */ if (flags & MXC_EHCI_POWER_PINS_ENABLED) v &= ~MXC_H1_UCTRL_H1PM_BIT; /* HOST1 power mask used*/ else v |= MXC_H1_UCTRL_H1PM_BIT; /* HOST1 power mask used*/ __raw_writel(v, usbother_base + MXC_USBCTRL_OFFSET); v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET); if (flags & MXC_EHCI_POWER_PINS_ENABLED) v &= ~MXC_H1_OC_DIS_BIT; /* OC is used */ else v |= MXC_H1_OC_DIS_BIT; /* OC is not used */ __raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET); v = __raw_readl(usbotg_base + MXC_USBCMD_OFFSET); if (flags & MXC_EHCI_ITC_NO_THRESHOLD) /* Interrupt Threshold Control:Immediate (no threshold) */ v &= MXC_UCMD_ITC_NO_THRESHOLD_MASK; __raw_writel(v, usbotg_base + MXC_USBCMD_OFFSET); break; } error: iounmap(usb_base); return ret; } #endif printk(KERN_WARNING "%s() unable to setup USBCONTROL for this CPU\n", __func__); return -EINVAL; }
void __init mx27_init_irq(void) { mxc_init_irq(MX27_IO_ADDRESS(MX27_AVIC_BASE_ADDR)); }
void __init mx27_init_irq(void) { mxc_init_irq(MX27_IO_ADDRESS(MX27_AVIC_BASE_ADDR)); mxc_gpio_init(imx27_gpio_ports, ARRAY_SIZE(imx27_gpio_ports)); }