Esempio n. 1
0
int SPIBus::SendDataBit(int b)
{
	clearSCK();		//si assicura che SCK low
	bitMOSI(b);
	WaitUsec(shot_delay);
	setSCK();		//AT90s latch data bit now!
	WaitUsec(shot_delay);
	clearSCK();

	return OK;
}
Esempio n. 2
0
// ritorna un numero negativo se c'e` un errore, altrimenti 0 o 1
int SPIBus::RecDataBit()
{
	register UBYTE b;

	clearSCK();		//si assicura SCK low
	WaitUsec(shot_delay);
	setSCK();
	WaitUsec(shot_delay);
	b = getMISO();
	clearSCK();

	return b;
}
Esempio n. 3
0
/*
 *	ATA (soft) reset
 */
EXPORT	void	ataReset(DrvTab *drv)
{
	UW	iob = drv->IOB;
	UW	reg, tm;
	BOOL	master;

	/* Set it to drive 0 */
	ataSetDrive(drv, 0);

	/* Check the existence of drive 0 (Master) */
	master = (InB(REG_DRVHEAD) == 0xff && InB(REG_STS) == 0xff) ?
							FALSE : TRUE;

	/* Reset pulse output */
	reg = (drv->d.pcc.IOConf[0] & IOC_IO2_NONE)? REG_DEVCTL : REG_DEVCTL2;
	OutB(reg, dcSRST);
	WaitUsec(20);				/* Wait for "20 usec" */
	OutB(reg, dcNORM);

	/* Wait until it becomes ready status:
			Firstly set it to drive 1 when there is no "Master" */
	for (tm = 0;;) {
		if (master == TRUE || ataSetDrive(drv, 0x100) == E_OK) {
			if ((ataStatusIn(drv) & stBSY) == 0) break;
		}
		if (drv->Spec.pccard && ataStatusIn(drv) == 0xff) break;
							/* There is no card */
		if (sdChkTmout(&tm, RESET_TMO, 10)) break;
	}
	/* Set Drive (Master & Slave) to the reset status */
	if (drv->Top != NULL) drv = drv->Top;
	for (; drv != NULL; drv = drv->Next) drv->Reset = TRUE;
}
Esempio n. 4
0
/*
 *	Status check
 */
LOCAL	W	ataChkSts(DrvTab *drv, UB chk, UB ok)
{
	UW	iob = drv->IOB;
	W	i;

	for (i = 0; i < STATUS_TMO; i += 10, WaitUsec(10)) {
		if ((InB(REG_STS) & chk) == ok) return E_OK;
	}
	return ERR_DATABUSY;
}
Esempio n. 5
0
/*
 *	Drive setting
 */
EXPORT	ER	ataSetDrive(DrvTab *drv, W drvno)
{
	UW	iob = drv->IOB;
	UB	dno;

	if (drvno < 0) drvno = drv->DrvNo;

	OutB(REG_DRVHEAD, dno = drDRV(drvno));
	WaitUsec(4);		/* Waiting is necessary depending on drive */
	if (InB(REG_DRVHEAD) == dno) return E_OK;
	return ERR_NOPORT;
}