void gp_ir_visitor::insert_phi(ir_phi* ir, unsigned num_sources)
{
lima_gp_ir_phi_node_t* phi = lima_gp_ir_phi_node_create(num_sources);
lima_gp_ir_reg_t* dest = lima_gp_ir_reg_create(this->prog);
dest->size = ir->dest->type->vector_elements;
phi->dest = dest;
_mesa_hash_table_insert(this->var_to_reg, _mesa_hash_pointer(ir->dest),
ir->dest, dest);
_mesa_hash_table_insert(this->phi_to_phi, _mesa_hash_pointer(ir), ir, phi);
ptrset_add(&this->cur_block->phi_nodes, phi);
}
void GLAPIENTRY
_mesa_VDPAUGetSurfaceivNV(GLintptr surface, GLenum pname, GLsizei bufSize,
GLsizei *length, GLint *values)
{
struct vdp_surface *surf = (struct vdp_surface *)surface;
GET_CURRENT_CONTEXT(ctx);
if (!ctx->vdpDevice || !ctx->vdpGetProcAddress || !ctx->vdpSurfaces) {
_mesa_error(ctx, GL_INVALID_OPERATION, "VDPAUGetSurfaceivNV");
return;
}
if (!_mesa_set_search(ctx->vdpSurfaces, _mesa_hash_pointer(surf), surf)) {
_mesa_error(ctx, GL_INVALID_VALUE, "VDPAUGetSurfaceivNV");
return;
}
if (pname != GL_SURFACE_STATE_NV) {
_mesa_error(ctx, GL_INVALID_ENUM, "VDPAUGetSurfaceivNV");
return;
}
if (bufSize < 1) {
_mesa_error(ctx, GL_INVALID_VALUE, "VDPAUGetSurfaceivNV");
return;
}
values[0] = surf->state;
if (length != NULL)
*length = 1;
}
void GLAPIENTRY
_mesa_VDPAUSurfaceAccessNV(GLintptr surface, GLenum access)
{
struct vdp_surface *surf = (struct vdp_surface *)surface;
GET_CURRENT_CONTEXT(ctx);
if (!ctx->vdpDevice || !ctx->vdpGetProcAddress || !ctx->vdpSurfaces) {
_mesa_error(ctx, GL_INVALID_OPERATION, "VDPAUSurfaceAccessNV");
return;
}
if (!_mesa_set_search(ctx->vdpSurfaces, _mesa_hash_pointer(surf), surf)) {
_mesa_error(ctx, GL_INVALID_VALUE, "VDPAUSurfaceAccessNV");
return;
}
if (access != GL_READ_ONLY && access != GL_WRITE_ONLY &&
access != GL_READ_WRITE) {
_mesa_error(ctx, GL_INVALID_VALUE, "VDPAUSurfaceAccessNV");
return;
}
if (surf->state == GL_SURFACE_MAPPED_NV) {
_mesa_error(ctx, GL_INVALID_OPERATION, "VDPAUSurfaceAccessNV");
return;
}
surf->access = access;
}
void GLAPIENTRY
_mesa_VDPAUUnregisterSurfaceNV(GLintptr surface)
{
struct vdp_surface *surf = (struct vdp_surface *)surface;
struct set_entry *entry;
int i;
GET_CURRENT_CONTEXT(ctx);
if (!ctx->vdpDevice || !ctx->vdpGetProcAddress || !ctx->vdpSurfaces) {
_mesa_error(ctx, GL_INVALID_OPERATION, "VDPAUUnregisterSurfaceNV");
return;
}
/* according to the spec it's ok when this is zero */
if (surface == 0)
return;
entry = _mesa_set_search(ctx->vdpSurfaces, _mesa_hash_pointer(surf), surf);
if (!entry) {
_mesa_error(ctx, GL_INVALID_VALUE, "VDPAUUnregisterSurfaceNV");
return;
}
for (i = 0; i < MAX_TEXTURES; i++) {
if (surf->textures[i]) {
surf->textures[i]->Immutable = GL_FALSE;
_mesa_reference_texobj(&surf->textures[i], NULL);
}
}
_mesa_set_remove(ctx->vdpSurfaces, entry);
free(surf);
}
ir_variable_refcount_entry *
ir_variable_refcount_visitor::get_variable_entry(ir_variable *var)
{
assert(var);
struct hash_entry *e = _mesa_hash_table_search(this->ht,
_mesa_hash_pointer(var),
var);
if (e)
return (ir_variable_refcount_entry *)e->data;
ir_variable_refcount_entry *entry = new ir_variable_refcount_entry(var);
assert(entry->referenced_count == 0);
_mesa_hash_table_insert(this->ht, _mesa_hash_pointer(var), var, entry);
return entry;
}
static int
_mesa_validate_sync(struct gl_context *ctx, struct gl_sync_object *syncObj)
{
return (syncObj != NULL)
&& _mesa_set_search(ctx->Shared->SyncObjects,
_mesa_hash_pointer(syncObj),
syncObj) != NULL
&& (syncObj->Type == GL_SYNC_FENCE)
&& !syncObj->DeletePending;
}
ir_visitor_status gp_ir_visitor::visit_enter(ir_loop* ir)
{
_mesa_hash_table_insert(this->loop_beginning_to_block,
_mesa_hash_pointer(ir), ir, this->cur_block);
lima_gp_ir_block_t* loop_header = lima_gp_ir_block_create();
lima_gp_ir_prog_insert(loop_header, this->cur_block);
this->cur_block = loop_header;
//we create after_loop and append it after loop_header, but we *do not* set
//this->cur_block - any additional blocks in the loop will go in between
//loop_header and after_loop
lima_gp_ir_block_t* after_loop = lima_gp_ir_block_create();
lima_gp_ir_prog_insert(after_loop, this->cur_block);
lima_gp_ir_block_t* old_break_block = this->break_block;
lima_gp_ir_block_t* old_continue_block = this->continue_block;
this->break_block = after_loop;
this->continue_block = loop_header;
visit_list_elements(this, &ir->begin_phi_nodes, false);
visit_list_elements(this, &ir->body_instructions);
_mesa_hash_table_insert(this->loop_end_to_block,
_mesa_hash_pointer(ir), ir, this->cur_block);
lima_gp_ir_branch_node_t* branch =
lima_gp_ir_branch_node_create(lima_gp_ir_op_branch_uncond);
branch->dest = loop_header;
lima_gp_ir_block_insert_end(this->cur_block, &branch->root_node);
this->break_block = old_break_block;
this->continue_block = old_continue_block;
this->cur_block = after_loop;
visit_list_elements(this, &ir->end_phi_nodes, false);
return visit_continue_with_parent;
}
ir_variable_refcount_entry *
ir_variable_refcount_visitor::find_variable_entry(ir_variable *var)
{
assert(var);
struct hash_entry *e = _mesa_hash_table_search(this->ht,
_mesa_hash_pointer(var),
var);
if (e)
return (ir_variable_refcount_entry *)e->data;
return NULL;
}
void GLAPIENTRY
_mesa_VDPAUMapSurfacesNV(GLsizei numSurfaces, const GLintptr *surfaces)
{
GET_CURRENT_CONTEXT(ctx);
int i;
if (!ctx->vdpDevice || !ctx->vdpGetProcAddress || !ctx->vdpSurfaces) {
_mesa_error(ctx, GL_INVALID_OPERATION, "VDPAUUnmapSurfacesNV");
return;
}
for (i = 0; i < numSurfaces; ++i) {
struct vdp_surface *surf = (struct vdp_surface *)surfaces[i];
if (!_mesa_set_search(ctx->vdpSurfaces, _mesa_hash_pointer(surf), surf)) {
_mesa_error(ctx, GL_INVALID_VALUE, "VDPAUSurfaceAccessNV");
return;
}
if (surf->state == GL_SURFACE_MAPPED_NV) {
_mesa_error(ctx, GL_INVALID_OPERATION, "VDPAUSurfaceAccessNV");
return;
}
}
for (i = 0; i < numSurfaces; ++i) {
struct vdp_surface *surf = (struct vdp_surface *)surfaces[i];
unsigned numTextureNames = surf->output ? 1 : 4;
unsigned j;
for (j = 0; j < numTextureNames; ++j) {
struct gl_texture_object *tex = surf->textures[j];
struct gl_texture_image *image;
_mesa_lock_texture(ctx, tex);
image = _mesa_get_tex_image(ctx, tex, surf->target, 0);
if (!image) {
_mesa_error(ctx, GL_OUT_OF_MEMORY, "VDPAUMapSurfacesNV");
_mesa_unlock_texture(ctx, tex);
return;
}
ctx->Driver.FreeTextureImageBuffer(ctx, image);
ctx->Driver.VDPAUMapSurface(ctx, surf->target, surf->access,
surf->output, tex, image,
surf->vdpSurface, j);
_mesa_unlock_texture(ctx, tex);
}
surf->state = GL_SURFACE_MAPPED_NV;
}
}
void gp_ir_visitor::rewrite_phi_jump_srcs(lima_gp_ir_phi_node_t* phi,
exec_list* srcs, unsigned start)
{
unsigned i = start;
foreach_list(node, srcs)
{
ir_phi_jump_src* src = (ir_phi_jump_src*) node;
struct hash_entry* entry =
_mesa_hash_table_search(this->loop_jump_to_block,
_mesa_hash_pointer(src->jump), src->jump);
lima_gp_ir_block_t* pred = (lima_gp_ir_block_t*) entry->data;
this->rewrite_phi_source(&phi->sources[i], pred, src->src);
i++;
}
ir_visitor_status gp_ir_visitor::visit(ir_loop_jump* ir)
{
_mesa_hash_table_insert(this->loop_jump_to_block, _mesa_hash_pointer(ir),
ir, this->cur_block);
lima_gp_ir_branch_node_t* branch =
lima_gp_ir_branch_node_create(lima_gp_ir_op_branch_uncond);
if (ir->mode == ir_loop_jump::jump_break)
branch->dest = this->break_block;
else
branch->dest = this->continue_block;
lima_gp_ir_block_insert_end(this->cur_block, &branch->root_node);
return visit_continue;
}
void gp_ir_visitor::rewrite_phi_source(lima_gp_ir_phi_node_src_t* src,
lima_gp_ir_block_t* block,
ir_variable* var)
{
if (var)
{
struct hash_entry* entry =
_mesa_hash_table_search(this->var_to_reg, _mesa_hash_pointer(var),
var);
src->reg = (lima_gp_ir_reg_t*) entry->data;
}
else
src->reg = NULL;
src->pred = block;
}
GLsync GLAPIENTRY
_mesa_FenceSync(GLenum condition, GLbitfield flags)
{
GET_CURRENT_CONTEXT(ctx);
struct gl_sync_object *syncObj;
ASSERT_OUTSIDE_BEGIN_END_WITH_RETVAL(ctx, 0);
if (condition != GL_SYNC_GPU_COMMANDS_COMPLETE) {
_mesa_error(ctx, GL_INVALID_ENUM, "glFenceSync(condition=0x%x)",
condition);
return 0;
}
if (flags != 0) {
_mesa_error(ctx, GL_INVALID_VALUE, "glFenceSync(flags=0x%x)",
condition);
return 0;
}
syncObj = ctx->Driver.NewSyncObject(ctx, GL_SYNC_FENCE);
if (syncObj != NULL) {
syncObj->Type = GL_SYNC_FENCE;
/* The name is not currently used, and it is never visible to
* applications. If sync support is extended to provide support for
* NV_fence, this field will be used. We'll also need to add an object
* ID hashtable.
*/
syncObj->Name = 1;
syncObj->RefCount = 1;
syncObj->DeletePending = GL_FALSE;
syncObj->SyncCondition = condition;
syncObj->Flags = flags;
syncObj->StatusFlag = 0;
ctx->Driver.FenceSync(ctx, syncObj, condition, flags);
_glthread_LOCK_MUTEX(ctx->Shared->Mutex);
_mesa_set_add(ctx->Shared->SyncObjects,
_mesa_hash_pointer(syncObj),
syncObj);
_glthread_UNLOCK_MUTEX(ctx->Shared->Mutex);
return (GLsync) syncObj;
}
return NULL;
}
GLboolean GLAPIENTRY
_mesa_VDPAUIsSurfaceNV(GLintptr surface)
{
struct vdp_surface *surf = (struct vdp_surface *)surface;
GET_CURRENT_CONTEXT(ctx);
if (!ctx->vdpDevice || !ctx->vdpGetProcAddress || !ctx->vdpSurfaces) {
_mesa_error(ctx, GL_INVALID_OPERATION, "VDPAUIsSurfaceNV");
return false;
}
if (!_mesa_set_search(ctx->vdpSurfaces, _mesa_hash_pointer(surf), surf)) {
return false;
}
return true;
}
void
_mesa_unref_sync_object(struct gl_context *ctx, struct gl_sync_object *syncObj)
{
struct set_entry *entry;
_glthread_LOCK_MUTEX(ctx->Shared->Mutex);
syncObj->RefCount--;
if (syncObj->RefCount == 0) {
entry = _mesa_set_search(ctx->Shared->SyncObjects,
_mesa_hash_pointer(syncObj),
syncObj);
assert (entry != NULL);
_mesa_set_remove(ctx->Shared->SyncObjects, entry);
_glthread_UNLOCK_MUTEX(ctx->Shared->Mutex);
ctx->Driver.DeleteSyncObject(ctx, syncObj);
} else {
_glthread_UNLOCK_MUTEX(ctx->Shared->Mutex);
}
}
int
iris_bo_busy(struct iris_bo *bo)
{
struct iris_bufmgr *bufmgr = bo->bufmgr;
struct drm_i915_gem_busy busy = { .handle = bo->gem_handle };
int ret = drm_ioctl(bufmgr->fd, DRM_IOCTL_I915_GEM_BUSY, &busy);
if (ret == 0) {
bo->idle = !busy.busy;
return busy.busy;
}
return false;
}
int
iris_bo_madvise(struct iris_bo *bo, int state)
{
struct drm_i915_gem_madvise madv = {
.handle = bo->gem_handle,
.madv = state,
.retained = 1,
};
drm_ioctl(bo->bufmgr->fd, DRM_IOCTL_I915_GEM_MADVISE, &madv);
return madv.retained;
}
/* drop the oldest entries that have been purged by the kernel */
static void
iris_bo_cache_purge_bucket(struct iris_bufmgr *bufmgr,
struct bo_cache_bucket *bucket)
{
list_for_each_entry_safe(struct iris_bo, bo, &bucket->head, head) {
if (iris_bo_madvise(bo, I915_MADV_DONTNEED))
break;
list_del(&bo->head);
bo_free(bo);
}
}
static struct iris_bo *
bo_calloc(void)
{
struct iris_bo *bo = calloc(1, sizeof(*bo));
if (bo) {
bo->hash = _mesa_hash_pointer(bo);
}
return bo;
}
static struct iris_bo *
bo_alloc_internal(struct iris_bufmgr *bufmgr,
const char *name,
uint64_t size,
enum iris_memory_zone memzone,
unsigned flags,
uint32_t tiling_mode,
uint32_t stride)
{
struct iris_bo *bo;
unsigned int page_size = getpagesize();
int ret;
struct bo_cache_bucket *bucket;
bool alloc_from_cache;
uint64_t bo_size;
bool zeroed = false;
if (flags & BO_ALLOC_ZEROED)
zeroed = true;
if ((flags & BO_ALLOC_COHERENT) && !bufmgr->has_llc) {
bo_size = MAX2(ALIGN(size, page_size), page_size);
bucket = NULL;
goto skip_cache;
}
/* Round the allocated size up to a power of two number of pages. */
bucket = bucket_for_size(bufmgr, size);
/* If we don't have caching at this size, don't actually round the
* allocation up.
*/
if (bucket == NULL) {
bo_size = MAX2(ALIGN(size, page_size), page_size);
} else {
bo_size = bucket->size;
}
mtx_lock(&bufmgr->lock);
/* Get a buffer out of the cache if available */
retry:
alloc_from_cache = false;
if (bucket != NULL && !list_empty(&bucket->head)) {
/* If the last BO in the cache is idle, then reuse it. Otherwise,
* allocate a fresh buffer to avoid stalling.
*/
bo = LIST_ENTRY(struct iris_bo, bucket->head.next, head);
if (!iris_bo_busy(bo)) {
alloc_from_cache = true;
list_del(&bo->head);
}
if (alloc_from_cache) {
if (!iris_bo_madvise(bo, I915_MADV_WILLNEED)) {
bo_free(bo);
iris_bo_cache_purge_bucket(bufmgr, bucket);
goto retry;
}
if (bo_set_tiling_internal(bo, tiling_mode, stride)) {
bo_free(bo);
goto retry;
}
if (zeroed) {
void *map = iris_bo_map(NULL, bo, MAP_WRITE | MAP_RAW);
if (!map) {
bo_free(bo);
goto retry;
}
memset(map, 0, bo_size);
}
}
}
if (alloc_from_cache) {
/* If the cached BO isn't in the right memory zone, free the old
* memory and assign it a new address.
*/
if (memzone != iris_memzone_for_address(bo->gtt_offset)) {
vma_free(bufmgr, bo->gtt_offset, bo->size);
bo->gtt_offset = 0ull;
}
} else {
skip_cache:
bo = bo_calloc();
if (!bo)
goto err;
bo->size = bo_size;
bo->idle = true;
struct drm_i915_gem_create create = { .size = bo_size };
/* All new BOs we get from the kernel are zeroed, so we don't need to
* worry about that here.
*/
ret = drm_ioctl(bufmgr->fd, DRM_IOCTL_I915_GEM_CREATE, &create);
if (ret != 0) {
free(bo);
goto err;
}
bo->gem_handle = create.handle;
bo->bufmgr = bufmgr;
bo->tiling_mode = I915_TILING_NONE;
bo->swizzle_mode = I915_BIT_6_SWIZZLE_NONE;
bo->stride = 0;
if (bo_set_tiling_internal(bo, tiling_mode, stride))
goto err_free;
/* Calling set_domain() will allocate pages for the BO outside of the
* struct mutex lock in the kernel, which is more efficient than waiting
* to create them during the first execbuf that uses the BO.
*/
struct drm_i915_gem_set_domain sd = {
.handle = bo->gem_handle,
.read_domains = I915_GEM_DOMAIN_CPU,
.write_domain = 0,
};
if (drm_ioctl(bo->bufmgr->fd, DRM_IOCTL_I915_GEM_SET_DOMAIN, &sd) != 0)
goto err_free;
}
bo->name = name;
p_atomic_set(&bo->refcount, 1);
bo->reusable = bucket && bufmgr->bo_reuse;
bo->cache_coherent = bufmgr->has_llc;
bo->index = -1;
bo->kflags = EXEC_OBJECT_SUPPORTS_48B_ADDRESS | EXEC_OBJECT_PINNED;
/* By default, capture all driver-internal buffers like shader kernels,
* surface states, dynamic states, border colors, and so on.
*/
if (memzone < IRIS_MEMZONE_OTHER)
bo->kflags |= EXEC_OBJECT_CAPTURE;
if (bo->gtt_offset == 0ull) {
bo->gtt_offset = vma_alloc(bufmgr, memzone, bo->size, 1);
if (bo->gtt_offset == 0ull)
goto err_free;
}
mtx_unlock(&bufmgr->lock);
if ((flags & BO_ALLOC_COHERENT) && !bo->cache_coherent) {
struct drm_i915_gem_caching arg = {
.handle = bo->gem_handle,
.caching = 1,
};
if (drm_ioctl(bufmgr->fd, DRM_IOCTL_I915_GEM_SET_CACHING, &arg) == 0) {
bo->cache_coherent = true;
bo->reusable = false;
}
}
DBG("bo_create: buf %d (%s) (%s memzone) %llub\n", bo->gem_handle,
bo->name, memzone_name(memzone), (unsigned long long) size);
return bo;
err_free:
bo_free(bo);
err:
mtx_unlock(&bufmgr->lock);
return NULL;
}
struct iris_bo *
iris_bo_alloc(struct iris_bufmgr *bufmgr,
const char *name,
uint64_t size,
enum iris_memory_zone memzone)
{
return bo_alloc_internal(bufmgr, name, size, memzone,
0, I915_TILING_NONE, 0);
}
struct iris_bo *
iris_bo_alloc_tiled(struct iris_bufmgr *bufmgr, const char *name,
uint64_t size, enum iris_memory_zone memzone,
uint32_t tiling_mode, uint32_t pitch, unsigned flags)
{
return bo_alloc_internal(bufmgr, name, size, memzone,
flags, tiling_mode, pitch);
}
struct iris_bo *
iris_bo_create_userptr(struct iris_bufmgr *bufmgr, const char *name,
void *ptr, size_t size,
enum iris_memory_zone memzone)
{
struct iris_bo *bo;
bo = bo_calloc();
if (!bo)
return NULL;
struct drm_i915_gem_userptr arg = {
.user_ptr = (uintptr_t)ptr,
.user_size = size,
};
if (drm_ioctl(bufmgr->fd, DRM_IOCTL_I915_GEM_USERPTR, &arg))
goto err_free;
bo->gem_handle = arg.handle;
/* Check the buffer for validity before we try and use it in a batch */
struct drm_i915_gem_set_domain sd = {
.handle = bo->gem_handle,
.read_domains = I915_GEM_DOMAIN_CPU,
};
if (drm_ioctl(bufmgr->fd, DRM_IOCTL_I915_GEM_SET_DOMAIN, &sd))
goto err_close;
bo->name = name;
bo->size = size;
bo->map_cpu = ptr;
bo->bufmgr = bufmgr;
bo->kflags = EXEC_OBJECT_SUPPORTS_48B_ADDRESS | EXEC_OBJECT_PINNED;
bo->gtt_offset = vma_alloc(bufmgr, memzone, size, 1);
if (bo->gtt_offset == 0ull)
goto err_close;
p_atomic_set(&bo->refcount, 1);
bo->userptr = true;
bo->cache_coherent = true;
bo->index = -1;
bo->idle = true;
return bo;
err_close:
drm_ioctl(bufmgr->fd, DRM_IOCTL_GEM_CLOSE, &bo->gem_handle);
err_free:
free(bo);
return NULL;
}
/**
* Returns a iris_bo wrapping the given buffer object handle.
*
* This can be used when one application needs to pass a buffer object
* to another.
*/
struct iris_bo *
iris_bo_gem_create_from_name(struct iris_bufmgr *bufmgr,
const char *name, unsigned int handle)
{
struct iris_bo *bo;
/* At the moment most applications only have a few named bo.
* For instance, in a DRI client only the render buffers passed
* between X and the client are named. And since X returns the
* alternating names for the front/back buffer a linear search
* provides a sufficiently fast match.
*/
mtx_lock(&bufmgr->lock);
bo = hash_find_bo(bufmgr->name_table, handle);
if (bo) {
iris_bo_reference(bo);
goto out;
}
struct drm_gem_open open_arg = { .name = handle };
int ret = drm_ioctl(bufmgr->fd, DRM_IOCTL_GEM_OPEN, &open_arg);
if (ret != 0) {
DBG("Couldn't reference %s handle 0x%08x: %s\n",
name, handle, strerror(errno));
bo = NULL;
goto out;
}
/* Now see if someone has used a prime handle to get this
* object from the kernel before by looking through the list
* again for a matching gem_handle
*/
bo = hash_find_bo(bufmgr->handle_table, open_arg.handle);
if (bo) {
iris_bo_reference(bo);
goto out;
}
bo = bo_calloc();
if (!bo)
goto out;
p_atomic_set(&bo->refcount, 1);
bo->size = open_arg.size;
bo->gtt_offset = 0;
bo->bufmgr = bufmgr;
bo->gem_handle = open_arg.handle;
bo->name = name;
bo->global_name = handle;
bo->reusable = false;
bo->external = true;
bo->kflags = EXEC_OBJECT_SUPPORTS_48B_ADDRESS | EXEC_OBJECT_PINNED;
bo->gtt_offset = vma_alloc(bufmgr, IRIS_MEMZONE_OTHER, bo->size, 1);
_mesa_hash_table_insert(bufmgr->handle_table, &bo->gem_handle, bo);
_mesa_hash_table_insert(bufmgr->name_table, &bo->global_name, bo);
struct drm_i915_gem_get_tiling get_tiling = { .handle = bo->gem_handle };
ret = drm_ioctl(bufmgr->fd, DRM_IOCTL_I915_GEM_GET_TILING, &get_tiling);
if (ret != 0)
goto err_unref;
bo->tiling_mode = get_tiling.tiling_mode;
bo->swizzle_mode = get_tiling.swizzle_mode;
/* XXX stride is unknown */
DBG("bo_create_from_handle: %d (%s)\n", handle, bo->name);
out:
mtx_unlock(&bufmgr->lock);
return bo;
err_unref:
bo_free(bo);
mtx_unlock(&bufmgr->lock);
return NULL;
}
static void
bo_free(struct iris_bo *bo)
{
struct iris_bufmgr *bufmgr = bo->bufmgr;
if (bo->map_cpu && !bo->userptr) {
VG_NOACCESS(bo->map_cpu, bo->size);
munmap(bo->map_cpu, bo->size);
}
if (bo->map_wc) {
VG_NOACCESS(bo->map_wc, bo->size);
munmap(bo->map_wc, bo->size);
}
if (bo->map_gtt) {
VG_NOACCESS(bo->map_gtt, bo->size);
munmap(bo->map_gtt, bo->size);
}
if (bo->external) {
struct hash_entry *entry;
if (bo->global_name) {
entry = _mesa_hash_table_search(bufmgr->name_table, &bo->global_name);
_mesa_hash_table_remove(bufmgr->name_table, entry);
}
entry = _mesa_hash_table_search(bufmgr->handle_table, &bo->gem_handle);
_mesa_hash_table_remove(bufmgr->handle_table, entry);
}
/* Close this object */
struct drm_gem_close close = { .handle = bo->gem_handle };
int ret = drm_ioctl(bufmgr->fd, DRM_IOCTL_GEM_CLOSE, &close);
if (ret != 0) {
DBG("DRM_IOCTL_GEM_CLOSE %d failed (%s): %s\n",
bo->gem_handle, bo->name, strerror(errno));
}
vma_free(bo->bufmgr, bo->gtt_offset, bo->size);
free(bo);
}
/** Frees all cached buffers significantly older than @time. */
static void
cleanup_bo_cache(struct iris_bufmgr *bufmgr, time_t time)
{
int i;
if (bufmgr->time == time)
return;
for (i = 0; i < bufmgr->num_buckets; i++) {
struct bo_cache_bucket *bucket = &bufmgr->cache_bucket[i];
list_for_each_entry_safe(struct iris_bo, bo, &bucket->head, head) {
if (time - bo->free_time <= 1)
break;
list_del(&bo->head);
bo_free(bo);
}
}
bufmgr->time = time;
}
static void
bo_unreference_final(struct iris_bo *bo, time_t time)
{
struct iris_bufmgr *bufmgr = bo->bufmgr;
struct bo_cache_bucket *bucket;
DBG("bo_unreference final: %d (%s)\n", bo->gem_handle, bo->name);
bucket = NULL;
if (bo->reusable)
bucket = bucket_for_size(bufmgr, bo->size);
/* Put the buffer into our internal cache for reuse if we can. */
if (bucket && iris_bo_madvise(bo, I915_MADV_DONTNEED)) {
bo->free_time = time;
bo->name = NULL;
list_addtail(&bo->head, &bucket->head);
} else {
bo_free(bo);
}
}
void
iris_bo_unreference(struct iris_bo *bo)
{
if (bo == NULL)
return;
assert(p_atomic_read(&bo->refcount) > 0);
if (atomic_add_unless(&bo->refcount, -1, 1)) {
struct iris_bufmgr *bufmgr = bo->bufmgr;
struct timespec time;
clock_gettime(CLOCK_MONOTONIC, &time);
mtx_lock(&bufmgr->lock);
if (p_atomic_dec_zero(&bo->refcount)) {
bo_unreference_final(bo, time.tv_sec);
cleanup_bo_cache(bufmgr, time.tv_sec);
}
mtx_unlock(&bufmgr->lock);
}
}
static void
bo_wait_with_stall_warning(struct pipe_debug_callback *dbg,
struct iris_bo *bo,
const char *action)
{
bool busy = dbg && !bo->idle;
double elapsed = unlikely(busy) ? -get_time() : 0.0;
iris_bo_wait_rendering(bo);
if (unlikely(busy)) {
elapsed += get_time();
if (elapsed > 1e-5) /* 0.01ms */ {
perf_debug(dbg, "%s a busy \"%s\" BO stalled and took %.03f ms.\n",
action, bo->name, elapsed * 1000);
}
}
}
static void
print_flags(unsigned flags)
{
if (flags & MAP_READ)
DBG("READ ");
if (flags & MAP_WRITE)
DBG("WRITE ");
if (flags & MAP_ASYNC)
DBG("ASYNC ");
if (flags & MAP_PERSISTENT)
DBG("PERSISTENT ");
if (flags & MAP_COHERENT)
DBG("COHERENT ");
if (flags & MAP_RAW)
DBG("RAW ");
DBG("\n");
}
static void *
iris_bo_map_cpu(struct pipe_debug_callback *dbg,
struct iris_bo *bo, unsigned flags)
{
struct iris_bufmgr *bufmgr = bo->bufmgr;
/* We disallow CPU maps for writing to non-coherent buffers, as the
* CPU map can become invalidated when a batch is flushed out, which
* can happen at unpredictable times. You should use WC maps instead.
*/
assert(bo->cache_coherent || !(flags & MAP_WRITE));
if (!bo->map_cpu) {
DBG("iris_bo_map_cpu: %d (%s)\n", bo->gem_handle, bo->name);
struct drm_i915_gem_mmap mmap_arg = {
.handle = bo->gem_handle,
.size = bo->size,
};
int ret = drm_ioctl(bufmgr->fd, DRM_IOCTL_I915_GEM_MMAP, &mmap_arg);
if (ret != 0) {
DBG("%s:%d: Error mapping buffer %d (%s): %s .\n",
__FILE__, __LINE__, bo->gem_handle, bo->name, strerror(errno));
return NULL;
}
void *map = (void *) (uintptr_t) mmap_arg.addr_ptr;
VG_DEFINED(map, bo->size);
if (p_atomic_cmpxchg(&bo->map_cpu, NULL, map)) {
VG_NOACCESS(map, bo->size);
munmap(map, bo->size);
}
}
assert(bo->map_cpu);
DBG("iris_bo_map_cpu: %d (%s) -> %p, ", bo->gem_handle, bo->name,
bo->map_cpu);
print_flags(flags);
if (!(flags & MAP_ASYNC)) {
bo_wait_with_stall_warning(dbg, bo, "CPU mapping");
}
if (!bo->cache_coherent && !bo->bufmgr->has_llc) {
/* If we're reusing an existing CPU mapping, the CPU caches may
* contain stale data from the last time we read from that mapping.
* (With the BO cache, it might even be data from a previous buffer!)
* Even if it's a brand new mapping, the kernel may have zeroed the
* buffer via CPU writes.
*
* We need to invalidate those cachelines so that we see the latest
* contents, and so long as we only read from the CPU mmap we do not
* need to write those cachelines back afterwards.
*
* On LLC, the emprical evidence suggests that writes from the GPU
* that bypass the LLC (i.e. for scanout) do *invalidate* the CPU
* cachelines. (Other reads, such as the display engine, bypass the
* LLC entirely requiring us to keep dirty pixels for the scanout
* out of any cache.)
*/
gen_invalidate_range(bo->map_cpu, bo->size);
}
return bo->map_cpu;
}
static void *
iris_bo_map_wc(struct pipe_debug_callback *dbg,
struct iris_bo *bo, unsigned flags)
{
struct iris_bufmgr *bufmgr = bo->bufmgr;
if (!bo->map_wc) {
DBG("iris_bo_map_wc: %d (%s)\n", bo->gem_handle, bo->name);
struct drm_i915_gem_mmap mmap_arg = {
.handle = bo->gem_handle,
.size = bo->size,
.flags = I915_MMAP_WC,
};
int ret = drm_ioctl(bufmgr->fd, DRM_IOCTL_I915_GEM_MMAP, &mmap_arg);
if (ret != 0) {
DBG("%s:%d: Error mapping buffer %d (%s): %s .\n",
__FILE__, __LINE__, bo->gem_handle, bo->name, strerror(errno));
return NULL;
}
void *map = (void *) (uintptr_t) mmap_arg.addr_ptr;
VG_DEFINED(map, bo->size);
if (p_atomic_cmpxchg(&bo->map_wc, NULL, map)) {
VG_NOACCESS(map, bo->size);
munmap(map, bo->size);
}
}
assert(bo->map_wc);
DBG("iris_bo_map_wc: %d (%s) -> %p\n", bo->gem_handle, bo->name, bo->map_wc);
print_flags(flags);
if (!(flags & MAP_ASYNC)) {
bo_wait_with_stall_warning(dbg, bo, "WC mapping");
}
return bo->map_wc;
}
/**
* Perform an uncached mapping via the GTT.
*
* Write access through the GTT is not quite fully coherent. On low power
* systems especially, like modern Atoms, we can observe reads from RAM before
* the write via GTT has landed. A write memory barrier that flushes the Write
* Combining Buffer (i.e. sfence/mfence) is not sufficient to order the later
* read after the write as the GTT write suffers a small delay through the GTT
* indirection. The kernel uses an uncached mmio read to ensure the GTT write
* is ordered with reads (either by the GPU, WB or WC) and unconditionally
* flushes prior to execbuf submission. However, if we are not informing the
* kernel about our GTT writes, it will not flush before earlier access, such
* as when using the cmdparser. Similarly, we need to be careful if we should
* ever issue a CPU read immediately following a GTT write.
*
* Telling the kernel about write access also has one more important
* side-effect. Upon receiving notification about the write, it cancels any
* scanout buffering for FBC/PSR and friends. Later FBC/PSR is then flushed by
* either SW_FINISH or DIRTYFB. The presumption is that we never write to the
* actual scanout via a mmaping, only to a backbuffer and so all the FBC/PSR
* tracking is handled on the buffer exchange instead.
*/
static void *
iris_bo_map_gtt(struct pipe_debug_callback *dbg,
struct iris_bo *bo, unsigned flags)
{
struct iris_bufmgr *bufmgr = bo->bufmgr;
/* Get a mapping of the buffer if we haven't before. */
if (bo->map_gtt == NULL) {
DBG("bo_map_gtt: mmap %d (%s)\n", bo->gem_handle, bo->name);
struct drm_i915_gem_mmap_gtt mmap_arg = { .handle = bo->gem_handle };
/* Get the fake offset back... */
int ret = drm_ioctl(bufmgr->fd, DRM_IOCTL_I915_GEM_MMAP_GTT, &mmap_arg);
if (ret != 0) {
DBG("%s:%d: Error preparing buffer map %d (%s): %s .\n",
__FILE__, __LINE__, bo->gem_handle, bo->name, strerror(errno));
return NULL;
}
/* and mmap it. */
void *map = mmap(0, bo->size, PROT_READ | PROT_WRITE,
MAP_SHARED, bufmgr->fd, mmap_arg.offset);
if (map == MAP_FAILED) {
DBG("%s:%d: Error mapping buffer %d (%s): %s .\n",
__FILE__, __LINE__, bo->gem_handle, bo->name, strerror(errno));
return NULL;
}
/* We don't need to use VALGRIND_MALLOCLIKE_BLOCK because Valgrind will
* already intercept this mmap call. However, for consistency between
* all the mmap paths, we mark the pointer as defined now and mark it
* as inaccessible afterwards.
*/
VG_DEFINED(map, bo->size);
if (p_atomic_cmpxchg(&bo->map_gtt, NULL, map)) {
VG_NOACCESS(map, bo->size);
munmap(map, bo->size);
}
}
assert(bo->map_gtt);
DBG("bo_map_gtt: %d (%s) -> %p, ", bo->gem_handle, bo->name, bo->map_gtt);
print_flags(flags);
if (!(flags & MAP_ASYNC)) {
bo_wait_with_stall_warning(dbg, bo, "GTT mapping");
}
return bo->map_gtt;
}
static bool
can_map_cpu(struct iris_bo *bo, unsigned flags)
{
if (bo->cache_coherent)
return true;
/* Even if the buffer itself is not cache-coherent (such as a scanout), on
* an LLC platform reads always are coherent (as they are performed via the
* central system agent). It is just the writes that we need to take special
* care to ensure that land in main memory and not stick in the CPU cache.
*/
if (!(flags & MAP_WRITE) && bo->bufmgr->has_llc)
return true;
/* If PERSISTENT or COHERENT are set, the mmapping needs to remain valid
* across batch flushes where the kernel will change cache domains of the
* bo, invalidating continued access to the CPU mmap on non-LLC device.
*
* Similarly, ASYNC typically means that the buffer will be accessed via
* both the CPU and the GPU simultaneously. Batches may be executed that
* use the BO even while it is mapped. While OpenGL technically disallows
* most drawing while non-persistent mappings are active, we may still use
* the GPU for blits or other operations, causing batches to happen at
* inconvenient times.
*
* If RAW is set, we expect the caller to be able to handle a WC buffer
* more efficiently than the involuntary clflushes.
*/
if (flags & (MAP_PERSISTENT | MAP_COHERENT | MAP_ASYNC | MAP_RAW))
return false;
return !(flags & MAP_WRITE);
}
void *
iris_bo_map(struct pipe_debug_callback *dbg,
struct iris_bo *bo, unsigned flags)
{
if (bo->tiling_mode != I915_TILING_NONE && !(flags & MAP_RAW))
return iris_bo_map_gtt(dbg, bo, flags);
void *map;
if (can_map_cpu(bo, flags))
map = iris_bo_map_cpu(dbg, bo, flags);
else
map = iris_bo_map_wc(dbg, bo, flags);
/* Allow the attempt to fail by falling back to the GTT where necessary.
*
* Not every buffer can be mmaped directly using the CPU (or WC), for
* example buffers that wrap stolen memory or are imported from other
* devices. For those, we have little choice but to use a GTT mmapping.
* However, if we use a slow GTT mmapping for reads where we expected fast
* access, that order of magnitude difference in throughput will be clearly
* expressed by angry users.
*
* We skip MAP_RAW because we want to avoid map_gtt's fence detiling.
*/
if (!map && !(flags & MAP_RAW)) {
perf_debug(dbg, "Fallback GTT mapping for %s with access flags %x\n",
bo->name, flags);
map = iris_bo_map_gtt(dbg, bo, flags);
}
return map;
}
/** Waits for all GPU rendering with the object to have completed. */
void
iris_bo_wait_rendering(struct iris_bo *bo)
{
/* We require a kernel recent enough for WAIT_IOCTL support.
* See intel_init_bufmgr()
*/
iris_bo_wait(bo, -1);
}
/**
* Waits on a BO for the given amount of time.
*
* @bo: buffer object to wait for
* @timeout_ns: amount of time to wait in nanoseconds.
* If value is less than 0, an infinite wait will occur.
*
* Returns 0 if the wait was successful ie. the last batch referencing the
* object has completed within the allotted time. Otherwise some negative return
* value describes the error. Of particular interest is -ETIME when the wait has
* failed to yield the desired result.
*
* Similar to iris_bo_wait_rendering except a timeout parameter allows
* the operation to give up after a certain amount of time. Another subtle
* difference is the internal locking semantics are different (this variant does
* not hold the lock for the duration of the wait). This makes the wait subject
* to a larger userspace race window.
*
* The implementation shall wait until the object is no longer actively
* referenced within a batch buffer at the time of the call. The wait will
* not guarantee that the buffer is re-issued via another thread, or an flinked
* handle. Userspace must make sure this race does not occur if such precision
* is important.
*
* Note that some kernels have broken the inifite wait for negative values
* promise, upgrade to latest stable kernels if this is the case.
*/
int
iris_bo_wait(struct iris_bo *bo, int64_t timeout_ns)
{
struct iris_bufmgr *bufmgr = bo->bufmgr;
/* If we know it's idle, don't bother with the kernel round trip */
if (bo->idle && !bo->external)
return 0;
struct drm_i915_gem_wait wait = {
.bo_handle = bo->gem_handle,
.timeout_ns = timeout_ns,
};
int ret = drm_ioctl(bufmgr->fd, DRM_IOCTL_I915_GEM_WAIT, &wait);
if (ret != 0)
return -errno;
bo->idle = true;
return ret;
}
void
iris_bufmgr_destroy(struct iris_bufmgr *bufmgr)
{
mtx_destroy(&bufmgr->lock);
/* Free any cached buffer objects we were going to reuse */
for (int i = 0; i < bufmgr->num_buckets; i++) {
struct bo_cache_bucket *bucket = &bufmgr->cache_bucket[i];
list_for_each_entry_safe(struct iris_bo, bo, &bucket->head, head) {
list_del(&bo->head);
bo_free(bo);
}
}
_mesa_hash_table_destroy(bufmgr->name_table, NULL);
_mesa_hash_table_destroy(bufmgr->handle_table, NULL);
for (int z = 0; z < IRIS_MEMZONE_COUNT; z++) {
if (z != IRIS_MEMZONE_BINDER)
util_vma_heap_finish(&bufmgr->vma_allocator[z]);
}
free(bufmgr);
}
static int
bo_set_tiling_internal(struct iris_bo *bo, uint32_t tiling_mode,
uint32_t stride)
{
struct iris_bufmgr *bufmgr = bo->bufmgr;
struct drm_i915_gem_set_tiling set_tiling;
int ret;
if (bo->global_name == 0 &&
tiling_mode == bo->tiling_mode && stride == bo->stride)
return 0;
memset(&set_tiling, 0, sizeof(set_tiling));
do {
/* set_tiling is slightly broken and overwrites the
* input on the error path, so we have to open code
* drm_ioctl.
*/
set_tiling.handle = bo->gem_handle;
set_tiling.tiling_mode = tiling_mode;
set_tiling.stride = stride;
ret = ioctl(bufmgr->fd, DRM_IOCTL_I915_GEM_SET_TILING, &set_tiling);
} while (ret == -1 && (errno == EINTR || errno == EAGAIN));
if (ret == -1)
return -errno;
bo->tiling_mode = set_tiling.tiling_mode;
bo->swizzle_mode = set_tiling.swizzle_mode;
bo->stride = set_tiling.stride;
return 0;
}
int
iris_bo_get_tiling(struct iris_bo *bo, uint32_t *tiling_mode,
uint32_t *swizzle_mode)
{
*tiling_mode = bo->tiling_mode;
*swizzle_mode = bo->swizzle_mode;
return 0;
}
struct iris_bo *
iris_bo_import_dmabuf(struct iris_bufmgr *bufmgr, int prime_fd)
{
uint32_t handle;
struct iris_bo *bo;
mtx_lock(&bufmgr->lock);
int ret = drmPrimeFDToHandle(bufmgr->fd, prime_fd, &handle);
if (ret) {
DBG("import_dmabuf: failed to obtain handle from fd: %s\n",
strerror(errno));
mtx_unlock(&bufmgr->lock);
return NULL;
}
/*
* See if the kernel has already returned this buffer to us. Just as
* for named buffers, we must not create two bo's pointing at the same
* kernel object
*/
bo = hash_find_bo(bufmgr->handle_table, handle);
if (bo) {
iris_bo_reference(bo);
goto out;
}
bo = bo_calloc();
if (!bo)
goto out;
p_atomic_set(&bo->refcount, 1);
/* Determine size of bo. The fd-to-handle ioctl really should
* return the size, but it doesn't. If we have kernel 3.12 or
* later, we can lseek on the prime fd to get the size. Older
* kernels will just fail, in which case we fall back to the
* provided (estimated or guess size). */
ret = lseek(prime_fd, 0, SEEK_END);
if (ret != -1)
bo->size = ret;
bo->bufmgr = bufmgr;
bo->gem_handle = handle;
_mesa_hash_table_insert(bufmgr->handle_table, &bo->gem_handle, bo);
bo->name = "prime";
bo->reusable = false;
bo->external = true;
bo->kflags = EXEC_OBJECT_SUPPORTS_48B_ADDRESS | EXEC_OBJECT_PINNED;
bo->gtt_offset = vma_alloc(bufmgr, IRIS_MEMZONE_OTHER, bo->size, 1);
struct drm_i915_gem_get_tiling get_tiling = { .handle = bo->gem_handle };
if (drm_ioctl(bufmgr->fd, DRM_IOCTL_I915_GEM_GET_TILING, &get_tiling))
goto err;
bo->tiling_mode = get_tiling.tiling_mode;
bo->swizzle_mode = get_tiling.swizzle_mode;
/* XXX stride is unknown */
out:
mtx_unlock(&bufmgr->lock);
return bo;
err:
bo_free(bo);
mtx_unlock(&bufmgr->lock);
return NULL;
}
static void
iris_bo_make_external_locked(struct iris_bo *bo)
{
if (!bo->external) {
_mesa_hash_table_insert(bo->bufmgr->handle_table, &bo->gem_handle, bo);
bo->external = true;
}
}
static void
iris_bo_make_external(struct iris_bo *bo)
{
struct iris_bufmgr *bufmgr = bo->bufmgr;
if (bo->external)
return;
mtx_lock(&bufmgr->lock);
iris_bo_make_external_locked(bo);
mtx_unlock(&bufmgr->lock);
}
int
iris_bo_export_dmabuf(struct iris_bo *bo, int *prime_fd)
{
struct iris_bufmgr *bufmgr = bo->bufmgr;
iris_bo_make_external(bo);
if (drmPrimeHandleToFD(bufmgr->fd, bo->gem_handle,
DRM_CLOEXEC, prime_fd) != 0)
return -errno;
bo->reusable = false;
return 0;
}
uint32_t
iris_bo_export_gem_handle(struct iris_bo *bo)
{
iris_bo_make_external(bo);
return bo->gem_handle;
}
int
iris_bo_flink(struct iris_bo *bo, uint32_t *name)
{
struct iris_bufmgr *bufmgr = bo->bufmgr;
if (!bo->global_name) {
struct drm_gem_flink flink = { .handle = bo->gem_handle };
if (drm_ioctl(bufmgr->fd, DRM_IOCTL_GEM_FLINK, &flink))
return -errno;
mtx_lock(&bufmgr->lock);
if (!bo->global_name) {
iris_bo_make_external_locked(bo);
bo->global_name = flink.name;
_mesa_hash_table_insert(bufmgr->name_table, &bo->global_name, bo);
}
mtx_unlock(&bufmgr->lock);
bo->reusable = false;
}
*name = bo->global_name;
return 0;
}
static void
add_bucket(struct iris_bufmgr *bufmgr, int size)
{
unsigned int i = bufmgr->num_buckets;
assert(i < ARRAY_SIZE(bufmgr->cache_bucket));
list_inithead(&bufmgr->cache_bucket[i].head);
bufmgr->cache_bucket[i].size = size;
bufmgr->num_buckets++;
assert(bucket_for_size(bufmgr, size) == &bufmgr->cache_bucket[i]);
assert(bucket_for_size(bufmgr, size - 2048) == &bufmgr->cache_bucket[i]);
assert(bucket_for_size(bufmgr, size + 1) != &bufmgr->cache_bucket[i]);
}
static void
init_cache_buckets(struct iris_bufmgr *bufmgr)
{
uint64_t size, cache_max_size = 64 * 1024 * 1024;
/* OK, so power of two buckets was too wasteful of memory.
* Give 3 other sizes between each power of two, to hopefully
* cover things accurately enough. (The alternative is
* probably to just go for exact matching of sizes, and assume
* that for things like composited window resize the tiled
* width/height alignment and rounding of sizes to pages will
* get us useful cache hit rates anyway)
*/
add_bucket(bufmgr, PAGE_SIZE);
add_bucket(bufmgr, PAGE_SIZE * 2);
add_bucket(bufmgr, PAGE_SIZE * 3);
/* Initialize the linked lists for BO reuse cache. */
for (size = 4 * PAGE_SIZE; size <= cache_max_size; size *= 2) {
add_bucket(bufmgr, size);
add_bucket(bufmgr, size + size * 1 / 4);
add_bucket(bufmgr, size + size * 2 / 4);
add_bucket(bufmgr, size + size * 3 / 4);
}
}
static GLintptr
register_surface(struct gl_context *ctx, GLboolean isOutput,
const GLvoid *vdpSurface, GLenum target,
GLsizei numTextureNames, const GLuint *textureNames)
{
struct vdp_surface *surf;
int i;
if (!ctx->vdpDevice || !ctx->vdpGetProcAddress || !ctx->vdpSurfaces) {
_mesa_error(ctx, GL_INVALID_OPERATION, "VDPAURegisterSurfaceNV");
return (GLintptr)NULL;
}
if (target != GL_TEXTURE_2D && target != GL_TEXTURE_RECTANGLE) {
_mesa_error(ctx, GL_INVALID_ENUM, "VDPAURegisterSurfaceNV");
return (GLintptr)NULL;
}
if (target == GL_TEXTURE_RECTANGLE && !ctx->Extensions.NV_texture_rectangle) {
_mesa_error(ctx, GL_INVALID_ENUM, "VDPAURegisterSurfaceNV");
return (GLintptr)NULL;
}
surf = CALLOC_STRUCT( vdp_surface );
if (surf == NULL) {
_mesa_error_no_memory("VDPAURegisterSurfaceNV");
return (GLintptr)NULL;
}
surf->vdpSurface = vdpSurface;
surf->target = target;
surf->access = GL_READ_WRITE;
surf->state = GL_SURFACE_REGISTERED_NV;
surf->output = isOutput;
for (i = 0; i < numTextureNames; ++i) {
struct gl_texture_object *tex;
tex = _mesa_lookup_texture(ctx, textureNames[i]);
if (tex == NULL) {
free(surf);
_mesa_error(ctx, GL_INVALID_OPERATION,
"VDPAURegisterSurfaceNV(texture ID not found)");
return (GLintptr)NULL;
}
_mesa_lock_texture(ctx, tex);
if (tex->Immutable) {
_mesa_unlock_texture(ctx, tex);
free(surf);
_mesa_error(ctx, GL_INVALID_OPERATION,
"VDPAURegisterSurfaceNV(texture is immutable)");
return (GLintptr)NULL;
}
if (tex->Target == 0)
tex->Target = target;
else if (tex->Target != target) {
_mesa_unlock_texture(ctx, tex);
free(surf);
_mesa_error(ctx, GL_INVALID_OPERATION,
"VDPAURegisterSurfaceNV(target mismatch)");
return (GLintptr)NULL;
}
/* This will disallow respecifying the storage. */
tex->Immutable = GL_TRUE;
_mesa_unlock_texture(ctx, tex);
_mesa_reference_texobj(&surf->textures[i], tex);
}
_mesa_set_add(ctx->vdpSurfaces, _mesa_hash_pointer(surf), surf);
return (GLintptr)surf;
}