/**
* Commutation timer hardware initialization.
*/
void comm_tim_init(void)
{
NVIC_InitTypeDef nvic;
TIM_TimeBaseInitTypeDef tim_base;
TIM_OCInitTypeDef tim_oc;
comm_tim_data.freq = 65535;
(void)gpc_setup_reg(GPROT_COMM_TIM_FREQ_REG_ADDR, &(comm_tim_data.freq));
/* TIM2 clock enable */
RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM2, ENABLE);
/* Enable the TIM2 gloabal interrupt */
nvic.NVIC_IRQChannel = TIM2_IRQn;
nvic.NVIC_IRQChannelPreemptionPriority = 0;
nvic.NVIC_IRQChannelSubPriority = 1;
nvic.NVIC_IRQChannelCmd = ENABLE;
NVIC_Init(&nvic);
/* TIM2 time base configuration */
tim_base.TIM_Period = 65535;
tim_base.TIM_Prescaler = 0;
tim_base.TIM_ClockDivision = 0;
tim_base.TIM_CounterMode = TIM_CounterMode_Up;
tim_base.TIM_RepetitionCounter = 0;
TIM_TimeBaseInit(TIM2, &tim_base);
/* TIM2 prescaler configuration */
TIM_PrescalerConfig(TIM2, 4, TIM_PSCReloadMode_Immediate);
/* TIM2 Output Compare Timing Mode configuration: Channel1 */
tim_oc.TIM_OCMode = TIM_OCMode_Timing;
tim_oc.TIM_OutputState = TIM_OutputState_Enable;
tim_oc.TIM_Pulse = comm_tim_data.freq;
tim_oc.TIM_OCPolarity = TIM_OCPolarity_High;
/* Not necessary for TIM2 because it is not an advanced timer
* but we are trying to make lint happy here.
*/
tim_oc.TIM_OutputNState = TIM_OutputNState_Disable;
tim_oc.TIM_OCNPolarity = TIM_OCNPolarity_High;
tim_oc.TIM_OCIdleState = TIM_OCIdleState_Set;
tim_oc.TIM_OCNIdleState = TIM_OCNIdleState_Set;
TIM_OC1Init(TIM2, &tim_oc);
TIM_OC1PreloadConfig(TIM2, TIM_OCPreload_Disable);
/* TIM2 Capture Compare 1 IT enable */
TIM_ITConfig(TIM2, TIM_IT_CC1, ENABLE);
/* TIM2 Update IT enable */
TIM_ITConfig(TIM2, TIM_IT_Update, ENABLE);
TIM_Cmd(TIM2, ENABLE);
comm_tim_reset();
}
/**
* Commutation timer hardware initialization.
*/
void comm_tim_init(void)
{
comm_tim_data.freq = 65535;
(void)gpc_setup_reg(GPROT_COMM_TIM_FREQ_REG_ADDR, &(comm_tim_data.freq));
/* TIM2 clock enable */
rcc_peripheral_enable_clock(&RCC_APB1ENR, RCC_APB1ENR_TIM2EN);
/* Enable the TIM2 gloabal interrupt. */
nvic_enable_irq(NVIC_TIM2_IRQ);
/* Reset TIM2 peripheral. */
timer_reset(TIM2);
/* TIM2 time base configuration */
timer_set_mode(TIM2, TIM_CR1_CKD_CK_INT,
TIM_CR1_CMS_EDGE,
TIM_CR1_DIR_UP);
/* Set prescaler value */
timer_set_prescaler(TIM2, 4);
/* Disable preload. */
timer_disable_preload(TIM2);
/* Set continous mode. */
timer_continuous_mode(TIM2);
/* Set period to maximum */
timer_set_period(TIM2, 65535);
/* Disable outputs. */
timer_disable_oc_output(TIM2, TIM_OC1);
timer_disable_oc_output(TIM2, TIM_OC2);
timer_disable_oc_output(TIM2, TIM_OC3);
timer_disable_oc_output(TIM2, TIM_OC4);
/* TIM2 Output Compare Timing Mode configuration: Channel1 */
timer_disable_oc_clear(TIM2, TIM_OC1);
timer_disable_oc_preload(TIM2, TIM_OC1);
timer_set_oc_slow_mode(TIM2, TIM_OC1);
timer_set_oc_mode(TIM2, TIM_OC1, TIM_OCM_FROZEN);
//timer_set_oc_polarity_high(TIM2, TIM_OC1);
/* Set initial capture compare value for OC1 */
timer_set_oc_value(TIM2, TIM_OC1, comm_tim_data.freq);
/* ARR reload enable */
timer_disable_preload(TIM2);
/* Counter enable */
timer_enable_counter(TIM2);
/* TIM2 Capture Compare 1 IT enable */
timer_enable_irq(TIM2, TIM_DIER_CC1IE);
/* TIM2 Update IT enable */
timer_enable_irq(TIM2, TIM_DIER_UIE);
comm_tim_reset();
}
