/*
* Create the appropriate control structures to manage
* a new EHCI host controller.
*
* Excerpts from linux ehci fsl driver.
*/
int ehci_hcd_init(int index, enum usb_init_type init,
struct ehci_hccr **hccr, struct ehci_hcor **hcor)
{
struct usb_ehci *ehci = NULL;
const char *phy_type = NULL;
size_t len;
char current_usb_controller[5];
#ifdef CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
char usb_phy[5];
usb_phy[0] = '\0';
#endif
if (has_erratum_a007075()) {
/*
* A 5ms delay is needed after applying soft-reset to the
* controller to let external ULPI phy come out of reset.
* This delay needs to be added before re-initializing
* the controller after soft-resetting completes
*/
mdelay(5);
}
memset(current_usb_controller, '\0', 5);
snprintf(current_usb_controller, sizeof(current_usb_controller),
"usb%d", index+1);
switch (index) {
case 0:
ehci = (struct usb_ehci *)CONFIG_SYS_FSL_USB1_ADDR;
break;
case 1:
ehci = (struct usb_ehci *)CONFIG_SYS_FSL_USB2_ADDR;
break;
default:
printf("ERROR: wrong controller index!!\n");
return -EINVAL;
};
*hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength);
*hcor = (struct ehci_hcor *)((uint32_t) *hccr +
HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
/* Set to Host mode */
setbits_le32(&ehci->usbmode, CM_HOST);
out_be32(&ehci->snoop1, SNOOP_SIZE_2GB);
out_be32(&ehci->snoop2, 0x80000000 | SNOOP_SIZE_2GB);
/* Init phy */
if (hwconfig_sub(current_usb_controller, "phy_type"))
phy_type = hwconfig_subarg(current_usb_controller,
"phy_type", &len);
else
phy_type = getenv("usb_phy_type");
if (!phy_type) {
#ifdef CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
/* if none specified assume internal UTMI */
strcpy(usb_phy, "utmi");
phy_type = usb_phy;
#else
printf("WARNING: USB phy type not defined !!\n");
return -1;
#endif
}
if (!strncmp(phy_type, "utmi", 4)) {
#if defined(CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY)
clrsetbits_be32(&ehci->control, CONTROL_REGISTER_W1C_MASK,
PHY_CLK_SEL_UTMI);
clrsetbits_be32(&ehci->control, CONTROL_REGISTER_W1C_MASK,
UTMI_PHY_EN);
udelay(1000); /* delay required for PHY Clk to appear */
#endif
out_le32(&(*hcor)->or_portsc[0], PORT_PTS_UTMI);
clrsetbits_be32(&ehci->control, CONTROL_REGISTER_W1C_MASK,
USB_EN);
} else {
clrsetbits_be32(&ehci->control, CONTROL_REGISTER_W1C_MASK,
PHY_CLK_SEL_ULPI);
clrsetbits_be32(&ehci->control, UTMI_PHY_EN |
CONTROL_REGISTER_W1C_MASK, USB_EN);
udelay(1000); /* delay required for PHY Clk to appear */
if (!usb_phy_clk_valid(ehci))
return -EINVAL;
out_le32(&(*hcor)->or_portsc[0], PORT_PTS_ULPI);
}
out_be32(&ehci->prictrl, 0x0000000c);
out_be32(&ehci->age_cnt_limit, 0x00000040);
out_be32(&ehci->sictrl, 0x00000001);
in_le32(&ehci->usbmode);
if (has_erratum_a007798())
set_txfifothresh(ehci, TXFIFOTHRESH);
if (has_erratum_a004477()) {
/*
* When reset is issued while any ULPI transaction is ongoing
* then it may result to corruption of ULPI Function Control
* Register which eventually causes phy clock to enter low
* power mode which stops the clock. Thus delay is required
* before reset to let ongoing ULPI transaction complete.
*/
udelay(1);
}
return 0;
}
static int prototype_board(void)
{
if (hwconfig_subarg("board", "rev", NULL))
return hwconfig_subarg_cmp("board", "rev", "prototype");
return 1;
}
