static void gen6_draw_wm_depth(struct ilo_render *r, const struct ilo_state_vector *vec, struct ilo_render_draw_session *session) { /* 3DSTATE_DEPTH_BUFFER and 3DSTATE_CLEAR_PARAMS */ if (DIRTY(FB) || r->batch_bo_changed) { const struct ilo_zs_surface *zs; uint32_t clear_params; if (vec->fb.state.zsbuf) { const struct ilo_surface_cso *surface = (const struct ilo_surface_cso *) vec->fb.state.zsbuf; const struct ilo_texture_slice *slice = ilo_texture_get_slice(ilo_texture(surface->base.texture), surface->base.u.tex.level, surface->base.u.tex.first_layer); assert(!surface->is_rt); zs = &surface->u.zs; clear_params = slice->clear_value; } else { zs = &vec->fb.null_zs; clear_params = 0; } if (ilo_dev_gen(r->dev) == ILO_GEN(6)) { gen6_wa_pre_non_pipelined(r); gen6_wa_pre_depth(r); } gen6_3DSTATE_DEPTH_BUFFER(r->builder, zs, false); gen6_3DSTATE_HIER_DEPTH_BUFFER(r->builder, zs); gen6_3DSTATE_STENCIL_BUFFER(r->builder, zs); gen6_3DSTATE_CLEAR_PARAMS(r->builder, clear_params); } }
void ilo_blitter_rectlist_resolve_z(struct ilo_blitter *blitter, struct pipe_resource *res, unsigned level, unsigned slice) { struct ilo_texture *tex = ilo_texture(res); struct pipe_depth_stencil_alpha_state dsa_state; const struct ilo_texture_slice *s = ilo_texture_get_slice(tex, level, slice); if (!ilo_image_can_enable_aux(&tex->image, level)) return; /* * From the Sandy Bridge PRM, volume 2 part 1, page 314: * * "Depth Test Enable must be enabled with the Depth Test Function set * to NEVER. Depth Buffer Write Enable must be enabled. Stencil Test * Enable and Stencil Buffer Write Enable must be disabled." */ memset(&dsa_state, 0, sizeof(dsa_state)); dsa_state.depth.writemask = true; dsa_state.depth.enabled = true; dsa_state.depth.func = PIPE_FUNC_NEVER; ilo_blitter_set_invariants(blitter); ilo_blitter_set_op(blitter, ILO_BLITTER_RECTLIST_RESOLVE_Z); ilo_blitter_set_dsa(blitter, &dsa_state); ilo_blitter_set_clear_values(blitter, s->clear_value, 0); ilo_blitter_set_fb_from_resource(blitter, res, res->format, level, slice); ilo_blitter_set_uses(blitter, ILO_BLITTER_USE_DSA | ILO_BLITTER_USE_FB_DEPTH); hiz_emit_rectlist(blitter); }
static void gen7_draw_wm(struct ilo_render *r, const struct ilo_state_vector *vec, struct ilo_render_draw_session *session) { const union ilo_shader_cso *cso = ilo_shader_get_kernel_cso(vec->fs); const uint32_t kernel_offset = ilo_shader_get_kernel_offset(vec->fs); /* 3DSTATE_WM */ if (DIRTY(FS) || (session->rs_delta.dirty & ILO_STATE_RASTER_3DSTATE_WM)) gen7_3DSTATE_WM(r->builder, &vec->rasterizer->rs, &cso->ps); /* 3DSTATE_BINDING_TABLE_POINTERS_PS */ if (session->binding_table_fs_changed) { gen7_3DSTATE_BINDING_TABLE_POINTERS_PS(r->builder, r->state.wm.BINDING_TABLE_STATE); } /* 3DSTATE_SAMPLER_STATE_POINTERS_PS */ if (session->sampler_fs_changed) { gen7_3DSTATE_SAMPLER_STATE_POINTERS_PS(r->builder, r->state.wm.SAMPLER_STATE); } /* 3DSTATE_CONSTANT_PS */ if (session->pcb_fs_changed) { gen7_3DSTATE_CONSTANT_PS(r->builder, &r->state.wm.PUSH_CONSTANT_BUFFER, &r->state.wm.PUSH_CONSTANT_BUFFER_size, 1); } /* 3DSTATE_PS */ if (DIRTY(FS) || r->instruction_bo_changed) { if (r->hw_ctx_changed) gen7_wa_pre_3dstate_ps_max_threads(r); gen7_3DSTATE_PS(r->builder, &cso->ps, kernel_offset); } /* 3DSTATE_SCISSOR_STATE_POINTERS */ if (session->scissor_changed) { gen6_3DSTATE_SCISSOR_STATE_POINTERS(r->builder, r->state.SCISSOR_RECT); } { const bool emit_3dstate_ps = (DIRTY(FS) || DIRTY(BLEND)); const bool emit_3dstate_depth_buffer = (DIRTY(FB) || DIRTY(DSA) || r->state_bo_changed); if (ilo_dev_gen(r->dev) == ILO_GEN(7)) { /* XXX what is the best way to know if this workaround is needed? */ if (emit_3dstate_ps || session->pcb_fs_changed || session->viewport_changed || session->binding_table_fs_changed || session->sampler_fs_changed || session->cc_changed || session->blend_changed || session->dsa_changed) gen7_wa_post_ps_and_later(r); } if (emit_3dstate_depth_buffer) gen7_wa_pre_depth(r); } /* 3DSTATE_DEPTH_BUFFER and 3DSTATE_CLEAR_PARAMS */ if (DIRTY(FB) || r->batch_bo_changed) { const struct ilo_state_zs *zs; uint32_t clear_params; if (vec->fb.state.zsbuf) { const struct ilo_surface_cso *surface = (const struct ilo_surface_cso *) vec->fb.state.zsbuf; const struct ilo_texture_slice *slice = ilo_texture_get_slice(ilo_texture(surface->base.texture), surface->base.u.tex.level, surface->base.u.tex.first_layer); assert(!surface->is_rt); zs = &surface->u.zs; clear_params = slice->clear_value; } else { zs = &vec->fb.null_zs; clear_params = 0; } gen6_3DSTATE_DEPTH_BUFFER(r->builder, zs); gen6_3DSTATE_HIER_DEPTH_BUFFER(r->builder, zs); gen6_3DSTATE_STENCIL_BUFFER(r->builder, zs); gen7_3DSTATE_CLEAR_PARAMS(r->builder, clear_params); } }
void ilo_blit_resolve_slices_for_hiz(struct ilo_context *ilo, struct pipe_resource *res, unsigned level, unsigned first_slice, unsigned num_slices, unsigned resolve_flags) { struct ilo_texture *tex = ilo_texture(res); const unsigned any_reader = ILO_TEXTURE_RENDER_READ | ILO_TEXTURE_BLT_READ | ILO_TEXTURE_CPU_READ; const unsigned other_writers = ILO_TEXTURE_BLT_WRITE | ILO_TEXTURE_CPU_WRITE; unsigned i; assert(tex->base.target != PIPE_BUFFER && ilo_image_can_enable_aux(&tex->image, level)); if (resolve_flags & ILO_TEXTURE_RENDER_WRITE) { /* * When ILO_TEXTURE_RENDER_WRITE is set, there can be no reader. We * need to perform a HiZ Buffer Resolve in case the resource was * previously written by another writer, unless this is a clear. * * When slices have different clear values, we perform a Depth Buffer * Resolve on all slices not sharing the clear value of the first slice. * After resolving, those slices do not use 3DSTATE_CLEAR_PARAMS and can * be made to have the same clear value as the first slice does. This * way, * * - 3DSTATE_CLEAR_PARAMS can be set to the clear value of any slice * - we will not resolve unnecessarily next time this function is * called * * Since slice clear value is the value the slice is cleared to when * ILO_TEXTURE_CLEAR is set, the bit needs to be unset. */ assert(!(resolve_flags & (other_writers | any_reader))); if (!(resolve_flags & ILO_TEXTURE_CLEAR)) { const uint32_t first_clear_value = ilo_texture_get_slice(tex, level, first_slice)->clear_value; bool set_clear_value = false; for (i = 0; i < num_slices; i++) { const struct ilo_texture_slice *slice = ilo_texture_get_slice(tex, level, first_slice + i); if (slice->flags & other_writers) { ilo_blitter_rectlist_resolve_hiz(ilo->blitter, res, level, first_slice + i); } else if (slice->clear_value != first_clear_value && (slice->flags & ILO_TEXTURE_RENDER_WRITE)) { ilo_blitter_rectlist_resolve_z(ilo->blitter, res, level, first_slice + i); set_clear_value = true; } } if (set_clear_value) { /* ILO_TEXTURE_CLEAR will be cleared later */ ilo_texture_set_slice_clear_value(tex, level, first_slice, num_slices, first_clear_value); } } } else if ((resolve_flags & any_reader) || ((resolve_flags & other_writers) && !(resolve_flags & ILO_TEXTURE_CLEAR))) { /* * When there is at least a reader or writer, we need to perform a * Depth Buffer Resolve in case the resource was previously written * by ILO_TEXTURE_RENDER_WRITE. */ for (i = 0; i < num_slices; i++) { const struct ilo_texture_slice *slice = ilo_texture_get_slice(tex, level, first_slice + i); if (slice->flags & ILO_TEXTURE_RENDER_WRITE) { ilo_blitter_rectlist_resolve_z(ilo->blitter, &tex->base, level, first_slice + i); } } } }
static void gen8_draw_wm(struct ilo_render *r, const struct ilo_state_vector *vec, struct ilo_render_draw_session *session) { const union ilo_shader_cso *cso = ilo_shader_get_kernel_cso(vec->fs); const uint32_t kernel_offset = ilo_shader_get_kernel_offset(vec->fs); /* 3DSTATE_WM */ if (session->rs_delta.dirty & ILO_STATE_RASTER_3DSTATE_WM) gen8_3DSTATE_WM(r->builder, &vec->rasterizer->rs); if (session->cc_delta.dirty & ILO_STATE_CC_3DSTATE_WM_DEPTH_STENCIL) gen8_3DSTATE_WM_DEPTH_STENCIL(r->builder, &vec->blend->cc); /* 3DSTATE_WM_HZ_OP and 3DSTATE_WM_CHROMAKEY */ if (r->hw_ctx_changed) { gen8_disable_3DSTATE_WM_HZ_OP(r->builder); gen8_3DSTATE_WM_CHROMAKEY(r->builder); } /* 3DSTATE_BINDING_TABLE_POINTERS_PS */ if (session->binding_table_fs_changed) { gen7_3DSTATE_BINDING_TABLE_POINTERS_PS(r->builder, r->state.wm.BINDING_TABLE_STATE); } /* 3DSTATE_SAMPLER_STATE_POINTERS_PS */ if (session->sampler_fs_changed) { gen7_3DSTATE_SAMPLER_STATE_POINTERS_PS(r->builder, r->state.wm.SAMPLER_STATE); } /* 3DSTATE_CONSTANT_PS */ if (session->pcb_fs_changed) { gen7_3DSTATE_CONSTANT_PS(r->builder, &r->state.wm.PUSH_CONSTANT_BUFFER, &r->state.wm.PUSH_CONSTANT_BUFFER_size, 1); } /* 3DSTATE_PS */ if (DIRTY(FS) || r->instruction_bo_changed) gen8_3DSTATE_PS(r->builder, &cso->ps, kernel_offset); /* 3DSTATE_PS_EXTRA */ if (DIRTY(FS)) gen8_3DSTATE_PS_EXTRA(r->builder, &cso->ps); /* 3DSTATE_PS_BLEND */ if (session->cc_delta.dirty & ILO_STATE_CC_3DSTATE_PS_BLEND) gen8_3DSTATE_PS_BLEND(r->builder, &vec->blend->cc); /* 3DSTATE_SCISSOR_STATE_POINTERS */ if (session->scissor_changed) { gen6_3DSTATE_SCISSOR_STATE_POINTERS(r->builder, r->state.SCISSOR_RECT); } /* 3DSTATE_DEPTH_BUFFER and 3DSTATE_CLEAR_PARAMS */ if (DIRTY(FB) || r->batch_bo_changed) { const struct ilo_state_zs *zs; uint32_t clear_params; if (vec->fb.state.zsbuf) { const struct ilo_surface_cso *surface = (const struct ilo_surface_cso *) vec->fb.state.zsbuf; const struct ilo_texture_slice *slice = ilo_texture_get_slice(ilo_texture(surface->base.texture), surface->base.u.tex.level, surface->base.u.tex.first_layer); assert(!surface->is_rt); zs = &surface->u.zs; clear_params = slice->clear_value; } else { zs = &vec->fb.null_zs; clear_params = 0; } gen8_wa_pre_depth(r); gen6_3DSTATE_DEPTH_BUFFER(r->builder, zs); gen6_3DSTATE_HIER_DEPTH_BUFFER(r->builder, zs); gen6_3DSTATE_STENCIL_BUFFER(r->builder, zs); gen7_3DSTATE_CLEAR_PARAMS(r->builder, clear_params); } }
/** * Return the offset (in bytes) to a slice within the bo. * * The returned offset is aligned to tile size. Since slices are not * guaranteed to start at tile boundaries, the X and Y offsets (in pixels) * from the tile origin to the slice are also returned. X offset is always a * multiple of 4 and Y offset is always a multiple of 2. */ unsigned ilo_texture_get_slice_offset(const struct ilo_texture *tex, unsigned level, unsigned slice, unsigned *x_offset, unsigned *y_offset) { const struct ilo_texture_slice *s = ilo_texture_get_slice(tex, level, slice); unsigned tile_w, tile_h, tile_size, row_size; unsigned x, y, slice_offset; /* see the Sandy Bridge PRM, volume 1 part 2, page 24 */ switch (tex->tiling) { case INTEL_TILING_NONE: /* W-tiled */ if (tex->bo_format == PIPE_FORMAT_S8_UINT) { tile_w = 64; tile_h = 64; } else { tile_w = 1; tile_h = 1; } break; case INTEL_TILING_X: tile_w = 512; tile_h = 8; break; case INTEL_TILING_Y: tile_w = 128; tile_h = 32; break; default: assert(!"unknown tiling"); tile_w = 1; tile_h = 1; break; } tile_size = tile_w * tile_h; row_size = tex->bo_stride * tile_h; /* in bytes */ x = s->x / tex->block_width * tex->bo_cpp; y = s->y / tex->block_height; slice_offset = row_size * (y / tile_h) + tile_size * (x / tile_w); /* * Since tex->bo_stride is a multiple of tile_w, slice_offset should be * aligned at this point. */ assert(slice_offset % tile_size == 0); /* * because of the possible values of align_i and align_j in * tex_layout_init_alignments(), x_offset is guaranteed to be a multiple of * 4 and y_offset is guaranteed to be a multiple of 2. */ if (x_offset) { /* in pixels */ x = (x % tile_w) / tex->bo_cpp * tex->block_width; assert(x % 4 == 0); *x_offset = x; } if (y_offset) { /* in pixels */ y = (y % tile_h) * tex->block_height; assert(y % 2 == 0); *y_offset = y; } return slice_offset; }
static void gen8_draw_wm(struct ilo_render *r, const struct ilo_state_vector *vec, struct ilo_render_draw_session *session) { /* 3DSTATE_WM */ if (DIRTY(FS) || DIRTY(RASTERIZER)) gen8_3DSTATE_WM(r->builder, vec->fs, vec->rasterizer); if (DIRTY(DSA)) gen8_3DSTATE_WM_DEPTH_STENCIL(r->builder, vec->dsa); /* 3DSTATE_WM_HZ_OP and 3DSTATE_WM_CHROMAKEY */ if (r->hw_ctx_changed) { gen8_disable_3DSTATE_WM_HZ_OP(r->builder); gen8_3DSTATE_WM_CHROMAKEY(r->builder); } /* 3DSTATE_BINDING_TABLE_POINTERS_PS */ if (session->binding_table_fs_changed) { gen7_3DSTATE_BINDING_TABLE_POINTERS_PS(r->builder, r->state.wm.BINDING_TABLE_STATE); } /* 3DSTATE_SAMPLER_STATE_POINTERS_PS */ if (session->sampler_fs_changed) { gen7_3DSTATE_SAMPLER_STATE_POINTERS_PS(r->builder, r->state.wm.SAMPLER_STATE); } /* 3DSTATE_CONSTANT_PS */ if (session->pcb_fs_changed) { gen7_3DSTATE_CONSTANT_PS(r->builder, &r->state.wm.PUSH_CONSTANT_BUFFER, &r->state.wm.PUSH_CONSTANT_BUFFER_size, 1); } /* 3DSTATE_PS */ if (DIRTY(FS) || r->instruction_bo_changed) gen8_3DSTATE_PS(r->builder, vec->fs); /* 3DSTATE_PS_EXTRA */ if (DIRTY(FS) || DIRTY(DSA) || DIRTY(BLEND)) { const bool cc_may_kill = (vec->dsa->dw_blend_alpha || vec->blend->alpha_to_coverage); gen8_3DSTATE_PS_EXTRA(r->builder, vec->fs, cc_may_kill, false); } /* 3DSTATE_PS_BLEND */ if (DIRTY(BLEND) || DIRTY(FB) || DIRTY(DSA)) gen8_3DSTATE_PS_BLEND(r->builder, vec->blend, &vec->fb, vec->dsa); /* 3DSTATE_SCISSOR_STATE_POINTERS */ if (session->scissor_changed) { gen6_3DSTATE_SCISSOR_STATE_POINTERS(r->builder, r->state.SCISSOR_RECT); } /* 3DSTATE_DEPTH_BUFFER and 3DSTATE_CLEAR_PARAMS */ if (DIRTY(FB) || r->batch_bo_changed) { const struct ilo_zs_surface *zs; uint32_t clear_params; if (vec->fb.state.zsbuf) { const struct ilo_surface_cso *surface = (const struct ilo_surface_cso *) vec->fb.state.zsbuf; const struct ilo_texture_slice *slice = ilo_texture_get_slice(ilo_texture(surface->base.texture), surface->base.u.tex.level, surface->base.u.tex.first_layer); assert(!surface->is_rt); zs = &surface->u.zs; clear_params = slice->clear_value; } else { zs = &vec->fb.null_zs; clear_params = 0; } gen8_wa_pre_depth(r); gen6_3DSTATE_DEPTH_BUFFER(r->builder, zs, false); gen6_3DSTATE_HIER_DEPTH_BUFFER(r->builder, zs); gen6_3DSTATE_STENCIL_BUFFER(r->builder, zs); gen7_3DSTATE_CLEAR_PARAMS(r->builder, clear_params); } }