Esempio n. 1
0
static int omap_interrupt( SIM_HBA *hba, int irq, int resp_type, uint32_t *resp )
{
	SIM_MMC_EXT		*ext;
	omap_ext_t		*oext;
	uint32_t		sts;
	int				intr;
	uintptr_t		base;

	ext		= (SIM_MMC_EXT *)hba->ext;
	oext	= (omap_ext_t *)ext->handle;
	base	= oext->mmc_base;
	intr	= 0;

	sts = in32( base + OMAP_MMCHS_STAT );
	sts &= in32( base + OMAP_MMCHS_IE ) | INTR_ERRI;
	out32( base + OMAP_MMCHS_STAT, sts );

	if( sts & INTR_ERRI ) {	// Any errors ?
//		mmc_slogf( hba, _SLOGC_SIM_MMC, _SLOG_ERROR, 1, "%s:  status %x", __FUNCTION__, sts );
		omap_dump( hba );
		intr |= MMC_INTR_ERROR | MMC_INTR_COMMAND;
		if( sts & INTR_ADMAE ) {	// ADMA error
			mmc_slogf( hba, _SLOGC_SIM_MMC, _SLOG_ERROR, 1, "%s:  ADMAES %x", __FUNCTION__, in32( base + OMAP_MMCHS_ADMAES ) );
		}

		if( sts & INTR_DTO ) {
			intr |= MMC_ERR_DATA_TO;
			omap_reset( hba, SYSCTL_SRD );
			omap_reset( hba, SYSCTL_SRC );
		}
		if( sts & INTR_DCRC ) {
			intr |= MMC_ERR_DATA_CRC;
		}
		if( sts & INTR_DEB ) {
			intr |= MMC_ERR_DATA_END;
		}
		if( sts & INTR_CTO ) {
			intr |= MMC_ERR_CMD_TO;
			omap_reset( hba, SYSCTL_SRC );
		}
		if( sts & INTR_CCRC ) {
			intr |= MMC_ERR_CMD_CRC;
		}
		if( sts & INTR_CEB ) {
			intr |= MMC_ERR_CMD_END;
		}
		if( sts & INTR_CIE ) {
			intr |= MMC_ERR_CMD_IDX;
		}
		if( sts & INTR_ACE ) {
			mmc_slogf( hba, _SLOGC_SIM_MMC, _SLOG_ERROR, 1, "%s: AC12 Error %x", __FUNCTION__, in32( base + OMAP_MMCHS_AC12 ) );
			intr |= MMC_ERR_DATA_TO | MMC_INTR_ERROR;
			omap_reset( hba, SYSCTL_SRD );
			omap_reset( hba, SYSCTL_SRC );
		}
	}
	else {
		if( sts & INTR_CC ) {
			intr |= MMC_INTR_COMMAND;
			if( resp ) {
				if( resp_type & MMC_RSP_136 ) {
					resp[3] = in32( base + OMAP_MMCHS_RSP76 );
					resp[2] = in32( base + OMAP_MMCHS_RSP54 );
					resp[1] = in32( base + OMAP_MMCHS_RSP32 );
					resp[0] = in32( base + OMAP_MMCHS_RSP10 );
				}
				else if( resp_type & MMC_RSP_PRESENT ) {
					resp[0] = in32( base + OMAP_MMCHS_RSP10 );
				}
			}

				// Busy check?
			if( resp_type & MMC_RSP_BUSY ) {
				if( omap_waitmask( hba, OMAP_MMCHS_PSTATE, PSTATE_DLA, 0, 500000 ) ) {
					intr |= MMC_ERR_CMD_TO | MMC_INTR_ERROR;
					mmc_slogf( hba, _SLOGC_SIM_MMC, _SLOG_ERROR, 1, "%s:  busy check time out", __FUNCTION__ );
				}
			}
		}

		if( sts & ( INTR_TC | INTR_BWR | INTR_BRR ) ) {
			if( sts & INTR_TC ) {
				intr |= MMC_INTR_DATA;
			}
			if( sts & INTR_BRR ) {
				intr |= MMC_INTR_RBRDY;
			}
			if( sts & INTR_BWR ) {
				intr |= MMC_INTR_WBRDY;
			}
		}
	}

	if( intr ) {
		out32( base + OMAP_MMCHS_IE, 0 );
	}

	return( intr );
}
void *omap3_init(void *hdl, char *options)
{
	omap3_spi_t	*dev;
	uintptr_t	base;
	int		i;
	uint32_t        reg;	
	dev = calloc(1, sizeof(omap3_spi_t));

	if (dev == NULL)
		return NULL;
		
	//Set defaults
	dev->pbase = OMAP3_SPI1_BASE;
	dev->irq_spi = OMAP3_SPI_SPI1_INTR;
	dev->clock = OMAP3_SPI_INPUT_CLOCK;
	dev->channel_num = 1;
	dev->force = 0;
	dev->edmapbase = DM816x_EDMA_BASE;
	dev->irq_edma = 0;	/* We use interrupt of receive channel   */
	dev->edma = 0;
	dev->num_cs = 1;
	dev->cs_delay = 0;
	dev->edma_tx_chid = dev->edma_rx_chid = -1;
	if (omap3_options(dev, options))
		goto fail0;

	/*
     	* Map in SPI registers
	*/
	if ((base = mmap_device_io(OMAP3_SPI_REGLEN, dev->pbase)) == (uintptr_t)MAP_FAILED)
		goto fail0;
	dev->vbase = base;
	
	/* Reset the SPI interface
	 * and wait for the reset to complete
	 */
	set_port(base + OMAP3_MCSPI_SYS_CONFIG, OMAP3_MCSPI_CONFIG_SOFT_RESET, OMAP3_MCSPI_CONFIG_SOFT_RESET);
	while ( !(in32(base + OMAP3_MCSPI_SYS_CONFIG) & 1)) {
		nanospin_ns(20);
	} 

	/*Set Master mode -- single channel mode*/
	out32((base + OMAP3_MCSPI_MODCTRL_OFFSET), (in32(base + OMAP3_MCSPI_MODCTRL_OFFSET) & OMAP3_MCSPI_MODCTRL_MASTER_SEL)|OMAP3_MCSPI_MODCTRL_MULTI_CH_SEL);
	 
    /*
	 * Calculate all device configuration here
	 */
	for (i = 0; i < dev->num_cs; i++){ //we have just one device defined in the driver till now....
		devctrl[i] = omap3_cfg(dev, &devlist[i].cfg);
		if(dev->force){
			/* if we need to set the default CSx level to other than defaul low, we need to kick it*/
			out32((base + OMAP3_MCSPI_CH1_CONFIG_OFFSET + 0x14 * i), devctrl[i]|SPI_COMM_TX_RX <<12);
			set_port(base + OMAP3_MCSPI_CH1_CTRL_OFFSET+0x14*i, OMAP3_MCSPI_CHANNEL_ENABLE, OMAP3_MCSPI_CHANNEL_ENABLE);
			/* force CS */
			set_port((base + OMAP3_MCSPI_CH1_CONFIG_OFFSET + 0x14*i),OMAP3_MCSPI_FORCE_MODE_ONE, OMAP3_MCSPI_FORCE_MODE_ONE);
			delay(1);
			/*un force CS */
			set_port((base + OMAP3_MCSPI_CH1_CONFIG_OFFSET + 0x14*i),OMAP3_MCSPI_FORCE_MODE_ONE, 0);
			set_port(base + OMAP3_MCSPI_CH1_CTRL_OFFSET+0x14*i, OMAP3_MCSPI_CHANNEL_ENABLE, 0);
		}
	}

	/*
	 * Attach SPI interrupt
	 */
	if (omap3_attach_intr(dev))
		goto fail1;
	
	dev->spi.hdl = hdl;

	/* Clear the appropriate Interrupts if any*/
	reg= in32(base + OMAP3_MCSPI_IRQ_STATUS_OFFSET) ;
  	out32((base + OMAP3_MCSPI_IRQ_STATUS_OFFSET), reg);

	if (dev->edma) {
		if (omap3_init_edma(dev))	dev->edma=0;

		/*
		 * Attach SDMA interrupt
	 	*/
		if (omap3_edma_attach_intr(dev)){
			printf("%s(%d): omap3_edma_attach_intr failed\n", __func__, __LINE__);
			goto fail2;
		}

	}
   	return dev;
	
fail2:
	munmap_device_memory ((void *)dev->edmavbase, DM6446_EDMA_SIZE); 
fail1:
	munmap_device_io(dev->vbase, OMAP3_SPI_REGLEN);
fail0:
	free(dev);
	return NULL;
}
Esempio n. 3
0
/*
 * Override weak is_pci_host()
 *
 * This routine is called to determine if a pci scan should be
 * performed. With various hardware environments (especially cPCI and
 * PPMC) it's insufficient to depend on the state of the arbiter enable
 * bit in the strap register, or generic host/adapter assumptions.
 *
 * Rather than hard-code a bad assumption in the general 440 code, the
 * 440 pci code requires the board to decide at runtime.
 *
 * Return 0 for adapter mode, non-zero for host (monarch) mode.
 */
int is_pci_host(struct pci_controller *hose)
{
	return ((in32(CONFIG_SYS_GPIO_BASE + 0x1C) & 0x00000800) == 0);
}
Esempio n. 4
0
int emac4xx_miiphy_read (char *devname, unsigned char addr,
		unsigned char reg, unsigned short *value)
{
	unsigned long sta_reg;	/* STA scratch area */
	unsigned long i;
	unsigned long emac_reg;


	emac_reg = miiphy_getemac_offset ();
	/* see if it is ready for 1000 nsec */
	i = 0;

	/* see if it is ready for  sec */
	while ((in32 (EMAC_STACR + emac_reg) & EMAC_STACR_OC) == EMAC_STACR_OC_MASK) {
		udelay (7);
		if (i > 5) {
#ifdef ET_DEBUG
			sta_reg = in32 (EMAC_STACR + emac_reg);
			printf ("read : EMAC_STACR=0x%0x\n", sta_reg);	/* test-only */
			printf ("read err 1\n");
#endif
			return -1;
		}
		i++;
	}
	sta_reg = reg;		/* reg address */
	/* set clock (50Mhz) and read flags */
#if defined(CONFIG_440GX) || defined(CONFIG_440SPE) || \
    defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
#if defined(CONFIG_IBM_EMAC4_V4)      /* EMAC4 V4 changed bit setting */
		sta_reg = (sta_reg & ~EMAC_STACR_OP_MASK) | EMAC_STACR_READ;
#else
		sta_reg |= EMAC_STACR_READ;
#endif
#else
	sta_reg = (sta_reg | EMAC_STACR_READ) & ~EMAC_STACR_CLK_100MHZ;
#endif

#if defined(CONFIG_PHY_CLK_FREQ) && !defined(CONFIG_440GX) && \
    !defined(CONFIG_440SP) && !defined(CONFIG_440SPE) && \
    !defined(CONFIG_440EPX) && !defined(CONFIG_440GRX)
	sta_reg = sta_reg | CONFIG_PHY_CLK_FREQ;
#endif
	sta_reg = sta_reg | (addr << 5);	/* Phy address */
	sta_reg = sta_reg | EMAC_STACR_OC_MASK;	/* new IBM emac v4 */
	out32 (EMAC_STACR + emac_reg, sta_reg);
#ifdef ET_DEBUG
	printf ("a2: write: EMAC_STACR=0x%0x\n", sta_reg);	/* test-only */
#endif

	sta_reg = in32 (EMAC_STACR + emac_reg);
#ifdef ET_DEBUG
		printf ("a21: read : EMAC_STACR=0x%0x\n", sta_reg);	/* test-only */
#endif
	i = 0;
	while ((sta_reg & EMAC_STACR_OC) == EMAC_STACR_OC_MASK) {
		udelay (7);
		if (i > 5) {
			return -1;
		}
		i++;
		sta_reg = in32 (EMAC_STACR + emac_reg);
#ifdef ET_DEBUG
		printf ("a22: read : EMAC_STACR=0x%0x\n", sta_reg);	/* test-only */
#endif
	}
	if ((sta_reg & EMAC_STACR_PHYE) != 0) {
		return -1;
	}

	*value = *(short *) (&sta_reg);
	return 0;


}				/* phy_read */
Esempio n. 5
0
int pci_440_init (struct pci_controller *hose)
{
	int reg_num = 0;

#ifndef CONFIG_DISABLE_PISE_TEST
	/*--------------------------------------------------------------------------+
	 * The PCI initialization sequence enable bit must be set ... if not abort
	 * pci setup since updating the bit requires chip reset.
	 *--------------------------------------------------------------------------*/
#if defined(CONFIG_440GX) || defined(CONFIG_440SP) || defined(CONFIG_440SPE)
	unsigned long strap;

	mfsdr(sdr_sdstp1,strap);
	if ((strap & SDR0_SDSTP1_PISE_MASK) == 0) {
		printf("PCI: SDR0_STRP1[PISE] not set.\n");
		printf("PCI: Configuration aborted.\n");
		return -1;
	}
#elif defined(CONFIG_440GP)
	unsigned long strap;

	strap = mfdcr(cpc0_strp1);
	if ((strap & CPC0_STRP1_PISE_MASK) == 0) {
		printf("PCI: CPC0_STRP1[PISE] not set.\n");
		printf("PCI: Configuration aborted.\n");
		return -1;
	}
#endif
#endif /* CONFIG_DISABLE_PISE_TEST */

	/*--------------------------------------------------------------------------+
	 * PCI controller init
	 *--------------------------------------------------------------------------*/
	hose->first_busno = 0;
	hose->last_busno = 0;

	/* PCI I/O space */
	pci_set_region(hose->regions + reg_num++,
		       0x00000000,
		       PCIX0_IOBASE,
		       0x10000,
		       PCI_REGION_IO);

	/* PCI memory space */
	pci_set_region(hose->regions + reg_num++,
		       CONFIG_SYS_PCI_TARGBASE,
		       CONFIG_SYS_PCI_MEMBASE,
#ifdef CONFIG_SYS_PCI_MEMSIZE
		       CONFIG_SYS_PCI_MEMSIZE,
#else
		       0x10000000,
#endif
		       PCI_REGION_MEM );

#if defined(CONFIG_PCI_SYS_MEM_BUS) && defined(CONFIG_PCI_SYS_MEM_PHYS) && \
	defined(CONFIG_PCI_SYS_MEM_SIZE)
	/* System memory space */
	pci_set_region(hose->regions + reg_num++,
		       CONFIG_PCI_SYS_MEM_BUS,
		       CONFIG_PCI_SYS_MEM_PHYS,
		       CONFIG_PCI_SYS_MEM_SIZE,
		       PCI_REGION_MEM | PCI_REGION_SYS_MEMORY );
#endif

	hose->region_count = reg_num;

	pci_setup_indirect(hose, PCIX0_CFGADR, PCIX0_CFGDATA);

	/* Let board change/modify hose & do initial checks */
	if (pci_pre_init (hose) == 0) {
		printf("PCI: Board-specific initialization failed.\n");
		printf("PCI: Configuration aborted.\n");
		return -1;
	}

	pci_register_hose( hose );

	/*--------------------------------------------------------------------------+
	 * PCI target init
	 *--------------------------------------------------------------------------*/
#if defined(CONFIG_SYS_PCI_TARGET_INIT)
	pci_target_init(hose);                /* Let board setup pci target */
#else
	out16r( PCIX0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID );
	out16r( PCIX0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_ID );
	out16r( PCIX0_CLS, 0x00060000 ); /* Bridge, host bridge */
#endif

#if defined(CONFIG_440GX) || defined(CONFIG_440SPE) || \
    defined(CONFIG_460EX) || defined(CONFIG_460GT)
	out32r( PCIX0_BRDGOPT1, 0x04000060 );               /* PLB Rq pri highest   */
	out32r( PCIX0_BRDGOPT2, in32(PCIX0_BRDGOPT2) | 0x83 ); /* Enable host config, clear Timeout, ensure int src1  */
#elif defined(PCIX0_BRDGOPT1)
	out32r( PCIX0_BRDGOPT1, 0x10000060 );               /* PLB Rq pri highest   */
	out32r( PCIX0_BRDGOPT2, in32(PCIX0_BRDGOPT2) | 1 ); /* Enable host config   */
#endif

	/*--------------------------------------------------------------------------+
	 * PCI master init: default is one 256MB region for PCI memory:
	 * 0x3_00000000 - 0x3_0FFFFFFF  ==> CONFIG_SYS_PCI_MEMBASE
	 *--------------------------------------------------------------------------*/
#if defined(CONFIG_SYS_PCI_MASTER_INIT)
	pci_master_init(hose);          /* Let board setup pci master */
#else
	out32r( PCIX0_POM0SA, 0 ); /* disable */
	out32r( PCIX0_POM1SA, 0 ); /* disable */
	out32r( PCIX0_POM2SA, 0 ); /* disable */
#if defined(CONFIG_440SPE) || \
    defined(CONFIG_460EX) || defined(CONFIG_460GT)
	out32r( PCIX0_POM0LAL, 0x10000000 );
	out32r( PCIX0_POM0LAH, 0x0000000c );
#else
	out32r( PCIX0_POM0LAL, 0x00000000 );
	out32r( PCIX0_POM0LAH, 0x00000003 );
#endif
	out32r( PCIX0_POM0PCIAL, CONFIG_SYS_PCI_MEMBASE );
	out32r( PCIX0_POM0PCIAH, 0x00000000 );
	out32r( PCIX0_POM0SA, 0xf0000001 ); /* 256MB, enabled */
	out32r( PCIX0_STS, in32r( PCIX0_STS ) & ~0x0000fff8 );
#endif

	/*--------------------------------------------------------------------------+
	 * PCI host configuration -- we don't make any assumptions here ... the
	 * _board_must_indicate_ what to do -- there's just too many runtime
	 * scenarios in environments like cPCI, PPMC, etc. to make a determination
	 * based on hard-coded values or state of arbiter enable.
	 *--------------------------------------------------------------------------*/
	if (is_pci_host(hose)) {
#ifdef CONFIG_PCI_SCAN_SHOW
		printf("PCI:   Bus Dev VenId DevId Class Int\n");
#endif
#if !defined(CONFIG_440EP) && !defined(CONFIG_440GR) && \
    !defined(CONFIG_440EPX) && !defined(CONFIG_440GRX)
		out16r( PCIX0_CMD, in16r( PCIX0_CMD ) | PCI_COMMAND_MASTER);
#endif
		hose->last_busno = pci_hose_scan(hose);
	}
	return hose->last_busno;
}
Esempio n. 6
0
int board_early_init_f (void)
{
	/*-------------------------------------------------------------------------
	 * Initialize EBC CONFIG
	 *-------------------------------------------------------------------------*/
	mtebc(EBC0_CFG, EBC_CFG_LE_UNLOCK |
	      EBC_CFG_PTD_DISABLE | EBC_CFG_RTC_64PERCLK |
	      EBC_CFG_ATC_PREVIOUS | EBC_CFG_DTC_PREVIOUS |
	      EBC_CFG_CTC_PREVIOUS | EBC_CFG_EMC_NONDEFAULT |
	      EBC_CFG_PME_DISABLE | EBC_CFG_PR_32);

	/*--------------------------------------------------------------------
	 * Setup the interrupt controller polarities, triggers, etc.
	 *-------------------------------------------------------------------*/
	/*
	 * Because of the interrupt handling rework to handle 440GX interrupts
	 * with the common code, we needed to change names of the UIC registers.
	 * Here the new relationship:
	 *
	 * U-Boot name	440GX name
	 * -----------------------
	 * UIC0		UICB0
	 * UIC1		UIC0
	 * UIC2		UIC1
	 * UIC3		UIC2
	 */
	mtdcr (UIC1SR, 0xffffffff);	/* clear all */
	mtdcr (UIC1ER, 0x00000000);	/* disable all */
	mtdcr (UIC1CR, 0x00000009);	/* SMI & UIC1 crit are critical */
	mtdcr (UIC1PR, 0xfffffe03);	/* per manual */
	mtdcr (UIC1TR, 0x01c00000);	/* per manual */
	mtdcr (UIC1VR, 0x00000001);	/* int31 highest, base=0x000 */
	mtdcr (UIC1SR, 0xffffffff);	/* clear all */

	mtdcr (UIC2SR, 0xffffffff);	/* clear all */
	mtdcr (UIC2ER, 0x00000000);	/* disable all */
	mtdcr (UIC2CR, 0x00000000);	/* all non-critical */
	mtdcr (UIC2PR, 0xffffe0ff);	/* per ref-board manual */
	mtdcr (UIC2TR, 0x00ffc000);	/* per ref-board manual */
	mtdcr (UIC2VR, 0x00000001);	/* int31 highest, base=0x000 */
	mtdcr (UIC2SR, 0xffffffff);	/* clear all */

	mtdcr (UIC3SR, 0xffffffff);	/* clear all */
	mtdcr (UIC3ER, 0x00000000);	/* disable all */
	mtdcr (UIC3CR, 0x00000000);	/* all non-critical */
	mtdcr (UIC3PR, 0xffffffff);	/* per ref-board manual */
	mtdcr (UIC3TR, 0x00ff8c0f);	/* per ref-board manual */
	mtdcr (UIC3VR, 0x00000001);	/* int31 highest, base=0x000 */
	mtdcr (UIC3SR, 0xffffffff);	/* clear all */

	mtdcr (UIC0SR, 0xfc000000); /* clear all */
	mtdcr (UIC0ER, 0x00000000); /* disable all */
	mtdcr (UIC0CR, 0x00000000); /* all non-critical */
	mtdcr (UIC0PR, 0xfc000000); /* */
	mtdcr (UIC0TR, 0x00000000); /* */
	mtdcr (UIC0VR, 0x00000001); /* */

	/* Setup shutdown/SSD empty interrupt as inputs */
	out32(GPIO0_TCR, in32(GPIO0_TCR) & ~(CONFIG_SYS_GPIO_SHUTDOWN | CONFIG_SYS_GPIO_SSD_EMPTY));
	out32(GPIO0_ODR, in32(GPIO0_ODR) & ~(CONFIG_SYS_GPIO_SHUTDOWN | CONFIG_SYS_GPIO_SSD_EMPTY));

	/* Setup GPIO/IRQ multiplexing */
	mtsdr(SDR0_PFC0, 0x01a33e00);

	return 0;
}
Esempio n. 7
0
uint32
arch_isa_read_io_32(int mapped_io_addr)
{
	return in32(mapped_io_addr);
}
Esempio n. 8
0
static void dump_gpio_reg( uintptr_t baseAdd)
{
	TRACE_INFO("GPIO_REVISION 0x%04x \r\n", in32( baseAdd + GPIO_REVISION ));
	TRACE_INFO("GPIO_SYSCONFIG 0x%04x \r\n", in32( baseAdd + GPIO_SYSCONFIG ));
	TRACE_INFO("GPIO_EOI 0x%04x \r\n", in32( baseAdd + GPIO_EOI ));
	TRACE_INFO("GPIO_IRQSTATUS_RAW_0 0x%04x \r\n", in32( baseAdd + GPIO_IRQSTATUS_RAW_0 ));
	TRACE_INFO("GPIO_IRQSTATUS_RAW_1 0x%04x \r\n", in32( baseAdd + GPIO_IRQSTATUS_RAW_1 ));
	TRACE_INFO("GPIO_IRQSTATUS_0 0x%04x \r\n", in32( baseAdd + GPIO_IRQSTATUS_0 ));
	TRACE_INFO("GPIO_IRQSTATUS_1 0x%04x \r\n", in32( baseAdd + GPIO_IRQSTATUS_1 ));
	TRACE_INFO("GPIO_IRQSTATUS_SET_0 0x%04x \r\n", in32( baseAdd + GPIO_IRQSTATUS_SET_0 ));
	TRACE_INFO("GPIO_IRQSTATUS_SET_1 0x%04x \r\n", in32( baseAdd + GPIO_IRQSTATUS_SET_1 ));
	TRACE_INFO("GPIO_IRQSTATUS_CLR_0 0x%04x \r\n", in32( baseAdd + GPIO_IRQSTATUS_CLR_0 ));
	TRACE_INFO("GPIO_IRQSTATUS_CLR_1 0x%04x \r\n", in32( baseAdd + GPIO_IRQSTATUS_CLR_1 ));
	TRACE_INFO("GPIO_SYSSTATUS 0x%04x \r\n", in32( baseAdd + GPIO_SYSSTATUS ));
	TRACE_INFO("GPIO_CTRL 0x%04x \r\n", in32( baseAdd + GPIO_CTRL ));
	TRACE_INFO("GPIO_OE 0x%04x \r\n", in32( baseAdd + GPIO_OE ));
	TRACE_INFO("GPIO_DATAIN 0x%04x \r\n", in32( baseAdd + GPIO_DATAIN ));
	TRACE_INFO("GPIO_DATAOUT 0x%04x \r\n", in32( baseAdd + GPIO_DATAOUT ));
	TRACE_INFO("GPIO_LEVELDETECT0 0x%04x \r\n", in32( baseAdd + GPIO_LEVELDETECT0 ));
	TRACE_INFO("GPIO_LEVELDETECT1 0x%04x \r\n", in32( baseAdd + GPIO_LEVELDETECT1 ));
	TRACE_INFO("GPIO_RISINGDETECT 0x%04x \r\n", in32( baseAdd + GPIO_RISINGDETECT ));
	TRACE_INFO("GPIO_FALLINGDETECT 0x%04x \r\n", in32( baseAdd + GPIO_FALLINGDETECT ));
	TRACE_INFO("GPIO_DEBOUNCENABLE 0x%04x \r\n", in32( baseAdd + GPIO_DEBOUNCENABLE ));
	TRACE_INFO("GPIO_DEBOUNCINGTIME 0x%04x \r\n", in32( baseAdd + GPIO_DEBOUNCINGTIME ));
	TRACE_INFO("GPIO_CLEARDATAOUT 0x%04x \r\n", in32( baseAdd + GPIO_CLEARDATAOUT ));
	TRACE_INFO("GPIO_SETDATAOUT 0x%04x \r\n", in32( baseAdd + GPIO_SETDATAOUT ));
}
Esempio n. 9
0
//#define CM_PER_GPIO1_CLKCTRL		(0xAC)	// This register manages the GPIO1 clocks. Section 8.1.2.1.41
//#define CM_PER_GPIO2_CLKCTRL		(0xB0)	// This register manages the GPIO2 clocks. Section 8.1.2.1.42
//#define CM_PER_GPIO3_CLKCTRL		(0xB4)	// This register manages the GPIO3 clocks. Section 8.1.2.1.43
//#define CM_PER_GPIO4_CLKCTRL		(0xB8)	// This register manages the GPIO4 clocks. Section 8.1.2.1.44
void GPIO0ModuleClkConfig(void)
{
	static char invo_count = 0;
	uintptr_t prcm_base,cm_wkup_regs;
	uint32_t	val;

	if( invo_count)	//第二次调用直接退出
		return;
	invo_count ++;

	prcm_base=mmap_device_io(CM_PRCM_SIZE,PRCM_BASE);
	cm_wkup_regs=prcm_base+0x400;
	/* Writing to MODULEMODE field of CM_WKUP_GPIO0_CLKCTRL register. */
    out32(cm_wkup_regs+CM_WKUP_GPIO0_CLKCTRL,CM_WKUP_GPIO0_CLKCTRL_MODULEMODE_ENABLE);

    /* Waiting for MODULEMODE field to reflect the written value. */
    while(CM_WKUP_GPIO0_CLKCTRL_MODULEMODE_ENABLE !=
          (in32(cm_wkup_regs + CM_WKUP_GPIO0_CLKCTRL) &
           CM_WKUP_GPIO0_CLKCTRL_MODULEMODE));

    /*
    ** Writing to OPTFCLKEN_GPIO0_GDBCLK field of CM_WKUP_GPIO0_CLKCTRL
    ** register.
    */
    val=in32(cm_wkup_regs + CM_WKUP_GPIO0_CLKCTRL);
    val|=CM_WKUP_GPIO0_CLKCTRL_OPTFCLKEN_GPIO0_GDBCLK;
    out32(cm_wkup_regs + CM_WKUP_GPIO0_CLKCTRL,val);

    /* Waiting for OPTFCLKEN_GPIO0_GDBCLK field to reflect the written value. */
    while(CM_WKUP_GPIO0_CLKCTRL_OPTFCLKEN_GPIO0_GDBCLK !=
          (in32(cm_wkup_regs + CM_WKUP_GPIO0_CLKCTRL) &
           CM_WKUP_GPIO0_CLKCTRL_OPTFCLKEN_GPIO0_GDBCLK));

    /* Verifying if the other bits are set to required settings. */

    /*
    ** Waiting for IDLEST field in CM_WKUP_CONTROL_CLKCTRL register to attain
    ** desired value.
    */
    while((CM_WKUP_CONTROL_CLKCTRL_IDLEST_FUNC <<
           CM_WKUP_CONTROL_CLKCTRL_IDLEST_SHIFT) !=
          (in32(cm_wkup_regs + CM_WKUP_CONTROL_CLKCTRL) &
           CM_WKUP_CONTROL_CLKCTRL_IDLEST));

    /*
    ** Waiting for CLKACTIVITY_L3_AON_GCLK field in CM_L3_AON_CLKSTCTRL
    ** register to attain desired value.
    */
    while(CM_WKUP_CM_L3_AON_CLKSTCTRL_CLKACTIVITY_L3_AON_GCLK !=
          (in32(cm_wkup_regs + CM_WKUP_CM_L3_AON_CLKSTCTRL) &
           CM_WKUP_CM_L3_AON_CLKSTCTRL_CLKACTIVITY_L3_AON_GCLK));

    /*
    ** Waiting for IDLEST field in CM_WKUP_L4WKUP_CLKCTRL register to attain
    ** desired value.
    */
    while((CM_WKUP_L4WKUP_CLKCTRL_IDLEST_FUNC <<
           CM_WKUP_L4WKUP_CLKCTRL_IDLEST_SHIFT) !=
          (in32(cm_wkup_regs + CM_WKUP_L4WKUP_CLKCTRL) &
           CM_WKUP_L4WKUP_CLKCTRL_IDLEST));

    /*
    ** Waiting for CLKACTIVITY_L4_WKUP_GCLK field in CM_WKUP_CLKSTCTRL register
    ** to attain desired value.
    */
    while(CM_WKUP_CLKSTCTRL_CLKACTIVITY_L4_WKUP_GCLK !=
          (in32(cm_wkup_regs + CM_WKUP_CLKSTCTRL) &
           CM_WKUP_CLKSTCTRL_CLKACTIVITY_L4_WKUP_GCLK));

    /*
    ** Waiting for CLKACTIVITY_L4_WKUP_AON_GCLK field in CM_L4_WKUP_AON_CLKSTCTRL
    ** register to attain desired value.
    */
    while(CM_WKUP_CM_L4_WKUP_AON_CLKSTCTRL_CLKACTIVITY_L4_WKUP_AON_GCLK !=
          (in32(cm_wkup_regs + CM_WKUP_CM_L4_WKUP_AON_CLKSTCTRL) &
           CM_WKUP_CM_L4_WKUP_AON_CLKSTCTRL_CLKACTIVITY_L4_WKUP_AON_GCLK));


    /* Writing to IDLEST field in CM_WKUP_GPIO0_CLKCTRL register. */
    while((CM_WKUP_GPIO0_CLKCTRL_IDLEST_FUNC <<
           CM_WKUP_GPIO0_CLKCTRL_IDLEST_SHIFT) !=
          (in32(cm_wkup_regs + CM_WKUP_GPIO0_CLKCTRL) &
           CM_WKUP_GPIO0_CLKCTRL_IDLEST));

    /*
    ** Waiting for CLKACTIVITY_GPIO0_GDBCLK field in CM_WKUP_GPIO0_CLKCTRL
    ** register to attain desired value.
    */
    while(CM_WKUP_CLKSTCTRL_CLKACTIVITY_GPIO0_GDBCLK !=
          (in32(cm_wkup_regs + CM_WKUP_CLKSTCTRL) &
           CM_WKUP_CLKSTCTRL_CLKACTIVITY_GPIO0_GDBCLK));
    munmap_device_io(prcm_base, CM_PRCM_SIZE);

}
Esempio n. 10
0
// Function Specification
//
// Name:  proc_pstate_kvm_setup
//
// Description: Get everything set up for KVM mode
//
// End Function Specification
void proc_pstate_kvm_setup()
{
    int                                 l_core;
    int                                 l_rc = 0;
    uint32_t                            l_configured_cores;
    pcbs_pcbspm_mode_reg_t              l_ppmr;
    pcbs_pmgp1_reg_t                    l_pmgp1;
    pcbs_power_management_bounds_reg_t  l_pmbr;
    errlHndl_t                          l_errlHndl;

    do
    {
        //only run this in KVM mode
        if(!G_sysConfigData.system_type.kvm)
        {
            break;
        }

        l_configured_cores = ~in32(PMC_CORE_DECONFIGURATION_REG);

        // Do per-core configuration
        for(l_core = 0; l_core < PGP_NCORES; l_core++, l_configured_cores <<= 1)
        {
            if(!(l_configured_cores & 0x80000000)) continue;

            //do read-modify-write to allow pmax clip to also clip voltage (not just frequency)
            l_rc = getscom_ffdc(CORE_CHIPLET_ADDRESS(PCBS_PCBSPM_MODE_REG, l_core),
                       &(l_ppmr.value), NULL); //commit errors internally
            if(l_rc)
            {
                TRAC_ERR("proc_pstate_kvm_setup: getscom(PCBS_PCBSPM_MODE_REG) failed. rc=%d, hw_core=%d",
                         l_rc, l_core);
                break;
            }
            l_ppmr.fields.enable_clipping_of_global_pstate_req = 1;
            l_rc = putscom_ffdc(CORE_CHIPLET_ADDRESS(PCBS_PCBSPM_MODE_REG, l_core),
                 l_ppmr.value, NULL); //commit errors internally
            if(l_rc)
            {
                TRAC_ERR("proc_pstate_kvm_setup: putscom(PCBS_PCBSPM_MODE_REG) failed. rc=%d, hw_core=%d",
                         l_rc, l_core);
                break;
            }

            //per Vaidy Srinivasan, clear bit 11 in the Power Management GP1 register
            l_pmgp1.value = 0;
            l_pmgp1.fields.pm_spr_override_en = 1;
            l_rc = putscom_ffdc(CORE_CHIPLET_ADDRESS(PCBS_PMGP1_REG_AND, l_core),
                           ~l_pmgp1.value, NULL); //commit errors internally
            if(l_rc)
            {
                TRAC_ERR("proc_pstate_kvm_setup: putscom(PCBS_PMGB1_REG_OR) failed. rc=0x%08x, hw_core=%d",
                         l_rc, l_core);
                break;
            }

            //set pmax/pmin clip initial settings
            l_pmbr.value = 0;
            l_pmbr.fields.pmin_clip = gpst_pmin(&G_global_pstate_table)+1; //Per David Du, we must use pmin+1 to avoid gpsa hang
            l_pmbr.fields.pmax_clip = gpst_pmax(&G_global_pstate_table);
            l_rc = putscom_ffdc(CORE_CHIPLET_ADDRESS(PCBS_POWER_MANAGEMENT_BOUNDS_REG, l_core),
                           l_pmbr.value, NULL); //commit errors internally
            if(l_rc)
            {
                TRAC_ERR("proc_pstate_kvm_setup: putscom(PCBS_POWER_MANAGEMENT_BOUNDS_REG) failed. rc=0x%08x, hw_core=%d",
                         l_rc, l_core);
                break;
            }

        }// end of per-core config

        if(l_rc)
        {
            break;
        }

        // Set the voltage clipping register to match the pmax/pmin clip values set above.
        pmc_rail_bounds_register_t prbr;
        prbr.value = in32(PMC_RAIL_BOUNDS_REGISTER);
        prbr.fields.pmin_rail = gpst_pmin(&G_global_pstate_table);
        prbr.fields.pmax_rail = gpst_pmax(&G_global_pstate_table);
        TRAC_IMP("pmin clip pstate = %d, pmax clip pstate = %d", prbr.fields.pmin_rail, prbr.fields.pmax_rail);
        out32(PMC_RAIL_BOUNDS_REGISTER, prbr.value);

        // Initialize the sapphire table in SRAM (sets valid bit)
        populate_pstate_to_sapphire_tbl();

        // copy sram image into mainstore HOMER
        populate_sapphire_tbl_to_mem();
        TRAC_IMP("proc_pstate_kvm_setup: RUNNING IN KVM MODE");
    }while(0);

    if(l_rc)
    {
        // Create Error Log and request reset
        /* @
         * @errortype
         * @moduleid    PROC_PSTATE_KVM_SETUP_MOD
         * @reasoncode  PROC_SCOM_ERROR
         * @userdata1   l_configured_cores
         * @userdata2   Return Code of call that failed
         * @userdata4   OCC_NO_EXTENDED_RC
         * @devdesc     OCC failed to scom a core register
         */
        l_errlHndl = createErrl(
                PROC_PSTATE_KVM_SETUP_MOD,          //modId
                PROC_SCOM_ERROR,                    //reasoncode
                OCC_NO_EXTENDED_RC,                 //Extended reason code
                ERRL_SEV_PREDICTIVE,                //Severity
                NULL,                               //Trace Buf
                DEFAULT_TRACE_SIZE,                 //Trace Size
                l_configured_cores,                 //userdata1
                l_rc                                //userdata2
                );

        addCalloutToErrl(l_errlHndl,
                ERRL_CALLOUT_TYPE_HUID,
                G_sysConfigData.proc_huid,
                ERRL_CALLOUT_PRIORITY_HIGH);
        addCalloutToErrl(l_errlHndl,
                ERRL_CALLOUT_TYPE_COMPONENT_ID,
                ERRL_COMPONENT_ID_FIRMWARE,
                ERRL_CALLOUT_PRIORITY_MED);

        REQUEST_RESET(l_errlHndl);
    }
}
Esempio n. 11
0
int board_early_init_f(void)
{
	register uint reg;

	/*--------------------------------------------------------------------
	 * Setup the external bus controller/chip selects
	 *-------------------------------------------------------------------*/
	mtdcr(ebccfga, xbcfg);
	reg = mfdcr(ebccfgd);
	mtdcr(ebccfgd, reg | 0x04000000);	/* Set ATC */

	mtebc(pb0ap, 0x03017300);	/* FLASH/SRAM */
	mtebc(pb0cr, 0xfc0da000);	/* BAS=0xfc0 64MB r/w 16-bit */

	mtebc(pb1ap, 0x00000000);
	mtebc(pb1cr, 0x00000000);

	mtebc(pb2ap, 0x04814500);
	/*CPLD*/ mtebc(pb2cr, 0x80018000);	/*BAS=0x800 1MB r/w 8-bit */

	mtebc(pb3ap, 0x00000000);
	mtebc(pb3cr, 0x00000000);

	mtebc(pb4ap, 0x00000000);
	mtebc(pb4cr, 0x00000000);

	mtebc(pb5ap, 0x00000000);
	mtebc(pb5cr, 0x00000000);

	/*--------------------------------------------------------------------
	 * Setup the GPIO pins
	 *-------------------------------------------------------------------*/
	/*CPLD cs */
	/*setup Address lines for flash size 64Meg. */
	out32(GPIO0_OSRL, in32(GPIO0_OSRL) | 0x50010000);
	out32(GPIO0_TSRL, in32(GPIO0_TSRL) | 0x50010000);
	out32(GPIO0_ISR1L, in32(GPIO0_ISR1L) | 0x50000000);

	/*setup emac */
	out32(GPIO0_TCR, in32(GPIO0_TCR) | 0xC080);
	out32(GPIO0_TSRL, in32(GPIO0_TSRL) | 0x40);
	out32(GPIO0_ISR1L, in32(GPIO0_ISR1L) | 0x55);
	out32(GPIO0_OSRH, in32(GPIO0_OSRH) | 0x50004000);
	out32(GPIO0_ISR1H, in32(GPIO0_ISR1H) | 0x00440000);

	/*UART1 */
	out32(GPIO1_TCR, in32(GPIO1_TCR) | 0x02000000);
	out32(GPIO1_OSRL, in32(GPIO1_OSRL) | 0x00080000);
	out32(GPIO1_ISR2L, in32(GPIO1_ISR2L) | 0x00010000);

	/* external interrupts IRQ0...3 */
	out32(GPIO1_TCR, in32(GPIO1_TCR) & ~0x00f00000);
	out32(GPIO1_TSRL, in32(GPIO1_TSRL) & ~0x0000ff00);
	out32(GPIO1_ISR1L, in32(GPIO1_ISR1L) | 0x00005500);

	/*setup USB 2.0 */
	out32(GPIO1_TCR, in32(GPIO1_TCR) | 0xc0000000);
	out32(GPIO1_OSRL, in32(GPIO1_OSRL) | 0x50000000);
	out32(GPIO0_TCR, in32(GPIO0_TCR) | 0xf);
	out32(GPIO0_OSRH, in32(GPIO0_OSRH) | 0xaa);
	out32(GPIO0_ISR2H, in32(GPIO0_ISR2H) | 0x00000500);

	/*--------------------------------------------------------------------
	 * Setup the interrupt controller polarities, triggers, etc.
	 *-------------------------------------------------------------------*/
	mtdcr(uic0sr, 0xffffffff);	/* clear all */
	mtdcr(uic0er, 0x00000000);	/* disable all */
	mtdcr(uic0cr, 0x00000009);	/* ATI & UIC1 crit are critical */
	mtdcr(uic0pr, 0xfffffe13);	/* per ref-board manual */
	mtdcr(uic0tr, 0x01c00008);	/* per ref-board manual */
	mtdcr(uic0vr, 0x00000001);	/* int31 highest, base=0x000 */
	mtdcr(uic0sr, 0xffffffff);	/* clear all */

	mtdcr(uic1sr, 0xffffffff);	/* clear all */
	mtdcr(uic1er, 0x00000000);	/* disable all */
	mtdcr(uic1cr, 0x00000000);	/* all non-critical */
	mtdcr(uic1pr, 0xffffe0ff);	/* per ref-board manual */
	mtdcr(uic1tr, 0x00ffc000);	/* per ref-board manual */
	mtdcr(uic1vr, 0x00000001);	/* int31 highest, base=0x000 */
	mtdcr(uic1sr, 0xffffffff);	/* clear all */

	/*--------------------------------------------------------------------
	 * Setup other serial configuration
	 *-------------------------------------------------------------------*/
	mfsdr(sdr_pci0, reg);
	mtsdr(sdr_pci0, 0x80000000 | reg);	/* PCI arbiter enabled */
	mtsdr(sdr_pfc0, 0x00003e00);	/* Pin function */
	mtsdr(sdr_pfc1, 0x00048000);	/* Pin function: UART0 has 4 pins */

	/*clear tmrclk divisor */
	*(unsigned char *)(CFG_BCSR_BASE | 0x04) = 0x00;

	/*enable ethernet */
	*(unsigned char *)(CFG_BCSR_BASE | 0x08) = 0xf0;

	/*enable usb 1.1 fs device and remove usb 2.0 reset */
	*(unsigned char *)(CFG_BCSR_BASE | 0x09) = 0x00;

	/*get rid of flash write protect */
	*(unsigned char *)(CFG_BCSR_BASE | 0x07) = 0x00;

	return 0;
}
Esempio n. 12
0
static const struct sigevent *spi_intr(void *area, int id)
{
	int channel_id = 0;
	uint32_t reg_value = 0;
	uintptr_t	base;
	int 		i, expected;
	omap3530_spi_t	*dev = area;
	base = dev->vbase;
	
	reg_value = in32(base + OMAP3530_MCSPI_IRQ_STATUS_OFFSET);

	/* The code below detects on which channel the interrupt
	 * has occured.
	 */
	if(reg_value & 0x0F)
		channel_id = OMAP3530_SPI_MASTER_CHANNEL_ONE;
	else {
		if(reg_value & 0x70)
			channel_id = OMAP3530_SPI_MASTER_CHANNEL_TWO;
		else
		{
			if(reg_value & 0x700)
				channel_id = OMAP3530_SPI_MASTER_CHANNEL_THREE;
			else 
				channel_id = OMAP3530_SPI_MASTER_CHANNEL_FOUR;
		}
	}
	if(channel_id>=NUM_OF_SPI_DEVS){
		out32(base + OMAP3530_MCSPI_IRQ_STATUS_OFFSET, reg_value);
		return NULL;
	}

	// Clear the interupt
	out32(base + OMAP3530_MCSPI_IRQ_STATUS_OFFSET, reg_value);

	// The remaining bytes are read from the omap3530_xfer function
	if (reg_value & INTR_TYPE_EOWKE)
		return (&dev->spievent);

#ifndef CPU_OMAP4430
	// Is Rx Full?
	if(reg_value & (INTR_TYPE_RX0_FULL << (channel_id * OMAP3530_INTERRUPT_BITS_PER_SPI_CHANNEL))) {
			expected = min(OMAP3530_SPI_FIFOLEN, dev->tlen - dev->rlen);
			// Read received block
			for(i = 0 ; i < expected; i++) {
					dev->pbuf[dev->rlen++] = in32(base + OMAP3530_MCSPI_CH1_RX_BUFFER_OFFSET + (OMAP3530_SPI_DEVICE_OFFSET * channel_id));
			}
	}

	// Is Tx empty?
	if(reg_value & (INTR_TYPE_TX0_EMPTY << (channel_id * OMAP3530_INTERRUPT_BITS_PER_SPI_CHANNEL))) { 
		expected = min(OMAP3530_SPI_FIFOLEN, dev->xlen - dev->tlen);
		if(expected) {
			// Start Tx again
			for(i = 0; i < expected; ++i) {
				out32(base + OMAP3530_MCSPI_CH1_TX_BUFFER_OFFSET + (OMAP3530_SPI_DEVICE_OFFSET * channel_id), dev->pbuf[dev->tlen++]);
			}			
		}
	}
#else
	// Is Rx Full?
	if(reg_value & (INTR_TYPE_RX0_FULL << (channel_id * OMAP3530_INTERRUPT_BITS_PER_SPI_CHANNEL))) {
			expected = min(dev->fifo_len, dev->tlen - dev->rlen);
			// Read received block
			for(i = 0 ; i < expected; i++) {
				dev->pbuf[dev->rlen++] = in32(base + OMAP3530_MCSPI_CH1_RX_BUFFER_OFFSET + (OMAP3530_SPI_DEVICE_OFFSET * channel_id));
			}
	}

	// Is Tx empty?
	if(reg_value & (INTR_TYPE_TX0_EMPTY << (channel_id * OMAP3530_INTERRUPT_BITS_PER_SPI_CHANNEL))) { 
		expected = min(dev->fifo_len, dev->xlen - dev->tlen);
		if(expected) {
			// Start Tx again
			for(i = 0; i < expected; ++i) {
				out32(base + OMAP3530_MCSPI_CH1_TX_BUFFER_OFFSET + (OMAP3530_SPI_DEVICE_OFFSET * channel_id), dev->pbuf[dev->tlen++]);
			}			
		}
	}
#endif
	return NULL;
}
Esempio n. 13
0
  /* RAM size is stored in CPC0_RGBAN1
   */
u32 pcippc2_sdram_size (void)
{
	return in32 (REG (CPC0, RGBAN1));
}
Esempio n. 14
0
int omap_dump( SIM_HBA *hba )
{
	SIM_MMC_EXT		*ext;
	omap_ext_t		*oext;
	uintptr_t		base;

	ext		= (SIM_MMC_EXT *)hba->ext;
	oext	= (omap_ext_t *)ext->handle;
	base	= oext->mmc_base;

#ifdef OMAP_DEBUG
	mmc_slogf( hba, _SLOGC_SIM_MMC, _SLOG_ERROR, 3, "%s: HL_REV %x, HL_HWINFO %x, HL_SYSCONFIG %x, SYSSTATUS %x, REV %x, CAPA %x, CUR_CAPA %x, SYSTEST %x, FE %x",
	__FUNCTION__, 
	in32( base + OMAP_MMCHS_HL_REV ),
	in32( base + OMAP_MMCHS_HL_HWINFO ),
	in32( base + OMAP_MMCHS_HL_SYSCONFIG ),
	in32( base + OMAP_MMCHS_SYSSTATUS ),
	in32( base + OMAP_MMCHS_REV ),
	in32( base + OMAP_MMCHS_CAPA ),
	in32( base + OMAP_MMCHS_CUR_CAPA ),
	in32( base + OMAP_MMCHS_SYSTEST ),
	in32( base + OMAP_MMCHS_FE ) );
	
	mmc_slogf( hba, _SLOGC_SIM_MMC, _SLOG_ERROR, 3, "%s: CSRE %x, CON %x, PWCNT %x, BLK %x, ARG %x, CMD %x, RSP10 %x, RSP32 %x, RSP54 %x,  RSP76 %x",
	__FUNCTION__,
	in32( base + OMAP_MMCHS_CSRE ),
	in32( base + OMAP_MMCHS_CON ),
	in32( base + OMAP_MMCHS_PWCNT ),
	in32( base + OMAP_MMCHS_BLK ),
	in32( base + OMAP_MMCHS_ARG ),
	in32( base + OMAP_MMCHS_CMD ),
	in32( base + OMAP_MMCHS_RSP10 ),
	in32( base + OMAP_MMCHS_RSP32 ),
	in32( base + OMAP_MMCHS_RSP54 ),
	in32( base + OMAP_MMCHS_RSP76 ) );

	mmc_slogf( hba, _SLOGC_SIM_MMC, _SLOG_ERROR, 3, "%s: PSTATE %x, HCTL %x, SYSCTL %x, STAT %x, IE %x, ISE %x, AC12 %x, ADMAES %x ADMASAL %x",
	__FUNCTION__,
	in32( base + OMAP_MMCHS_PSTATE ),
	in32( base + OMAP_MMCHS_HCTL ),
	in32( base + OMAP_MMCHS_SYSCTL ),
	in32( base + OMAP_MMCHS_STAT ), 
	in32( base + OMAP_MMCHS_IE ),
	in32( base + OMAP_MMCHS_ISE ),
	in32( base + OMAP_MMCHS_AC12 ),
	in32( base + OMAP_MMCHS_ADMAES ),
	in32( base + OMAP_MMCHS_ADMASAL ) );
#endif
	return( MMC_SUCCESS );
}
Esempio n. 15
0
uint32 in_reg(uint32 index)
{
	out32(index, vcons.index_port);
	return in32(vcons.value_port);
}
Esempio n. 16
0
static err_t gpio_init(Drive_Gpio *t)
{
	Drive_Gpio 		*cthis = ( Drive_Gpio *)t ;
	uint32_t		tmp_reg = 0;
	gpio_cfg 		*config = cthis->config;
	int 			i = 0;

	 assert( config->intr_line < 2);

	cthis->gpio_vbase = mmap_device_io( AM335X_GPIO_SIZE, GpioBase[ config->pin_group]);
#ifdef DEBUG_GPIO
	TRACE_INFO("Drive Piling :%s-%s-%d \r\n", __FILE__, __func__, __LINE__);
	TRACE_INFO("pin config 0x%04x \r\n", rd_pin_conf( config->pin_ctrl_off));
	return EXIT_SUCCESS;
#else
	if (cthis->gpio_vbase == MAP_DEVICE_FAILED)
	{

		return ERROR_T( gpio_init_mapio_fail);
	}
	gpioModuleConfig[ config->pin_group]();
	GPIOModuleEnable( cthis->gpio_vbase);

	//配置引脚方向为输入
	tmp_reg = in32( cthis->gpio_vbase + GPIO_OE );
	tmp_reg |= 1 << config->pin_number;
	out32( cthis->gpio_vbase + GPIO_OE, tmp_reg );


	//使能消抖
	tmp_reg=in32( cthis->gpio_vbase + GPIO_DEBOUNCENABLE);
	tmp_reg &=~( 1 << config->pin_number);
	tmp_reg |= ( 1 << config->pin_number);
	out32( cthis->gpio_vbase + GPIO_DEBOUNCENABLE, tmp_reg);

	//消抖时间
	out32( cthis->gpio_vbase + GPIO_DEBOUNCINGTIME, ( config->debou_time ));

	//配置中断监测类型
	for( i = 0; i < 4; i ++)
	{
		if( ( ( 1 << i) & config->intr_type) )
		{
			//使能该类型
			tmp_reg = in32( cthis->gpio_vbase + GPIO_DETECT(i));
			tmp_reg |= 1 << config->pin_number;
			out32(cthis->gpio_vbase + GPIO_DETECT(i), tmp_reg);
		}
		else
		{
			//禁止其他类型
			tmp_reg = in32( cthis->gpio_vbase + GPIO_DETECT(i));
			tmp_reg &= ~(1 << config->pin_number);
			out32(cthis->gpio_vbase + GPIO_DETECT(i), tmp_reg);
		}
	}

	//使能引脚中断
//	tmp_reg = in32( cthis->gpio_vbase + GPIO_IRQSTATUS_SET( config->intr_line));
//	tmp_reg |= 1 << config->pin_number;
//	out32(cthis->gpio_vbase + GPIO_IRQSTATUS_SET( config->intr_line), tmp_reg);
#ifdef DEBUG_GPIO
	dump_gpio_reg( cthis->gpio_vbase);
#endif
	SIGEV_INTR_INIT( &cthis->isr_event );
	cthis->irq_id = InterruptAttach_r ( GpioIntNum[ config->intr_line][ config->pin_group], gpioExtInteIsr, cthis, 1, _NTO_INTR_FLAGS_END );
	return EXIT_SUCCESS;

#endif
}
Esempio n. 17
0
int misc_init_r (void)
{
	volatile unsigned char *duart0_mcr = (unsigned char *)((ulong)DUART0_BA + 4);
	volatile unsigned char *duart1_mcr = (unsigned char *)((ulong)DUART1_BA + 4);
	volatile unsigned char *duart2_mcr = (unsigned char *)((ulong)DUART2_BA + 4);
	volatile unsigned char *duart3_mcr = (unsigned char *)((ulong)DUART3_BA + 4);
	unsigned char *dst;
	ulong len = sizeof(fpgadata);
	int status;
	int index;
	int i;

	dst = malloc(CFG_FPGA_MAX_SIZE);
	if (gunzip (dst, CFG_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) {
		printf ("GUNZIP ERROR - must RESET board to recover\n");
		do_reset (NULL, 0, 0, NULL);
	}

	status = fpga_boot(dst, len);
	if (status != 0) {
		printf("\nFPGA: Booting failed ");
		switch (status) {
		case ERROR_FPGA_PRG_INIT_LOW:
			printf("(Timeout: INIT not low after asserting PROGRAM*)\n ");
			break;
		case ERROR_FPGA_PRG_INIT_HIGH:
			printf("(Timeout: INIT not high after deasserting PROGRAM*)\n ");
			break;
		case ERROR_FPGA_PRG_DONE:
			printf("(Timeout: DONE not high after programming FPGA)\n ");
			break;
		}

		/* display infos on fpgaimage */
		index = 15;
		for (i=0; i<4; i++) {
			len = dst[index];
			printf("FPGA: %s\n", &(dst[index+1]));
			index += len+3;
		}
		putc ('\n');
		/* delayed reboot */
		for (i=20; i>0; i--) {
			printf("Rebooting in %2d seconds \r",i);
			for (index=0;index<1000;index++)
				udelay(1000);
		}
		putc ('\n');
		do_reset(NULL, 0, 0, NULL);
	}

	puts("FPGA:  ");

	/* display infos on fpgaimage */
	index = 15;
	for (i=0; i<4; i++) {
		len = dst[index];
		printf("%s ", &(dst[index+1]));
		index += len+3;
	}
	putc ('\n');

	free(dst);

	/*
	 * Reset FPGA via FPGA_DATA pin
	 */
	SET_FPGA(FPGA_PRG | FPGA_CLK);
	udelay(1000); /* wait 1ms */
	SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);
	udelay(1000); /* wait 1ms */

	/*
	 * Reset external DUARTs
	 */
	out32(GPIO0_OR, in32(GPIO0_OR) | CFG_DUART_RST); /* set reset to high */
	udelay(10); /* wait 10us */
	out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_DUART_RST); /* set reset to low */
	udelay(1000); /* wait 1ms */

	/*
	 * Enable interrupts in exar duart mcr[3]
	 */
	*duart0_mcr = 0x08;
	*duart1_mcr = 0x08;
	*duart2_mcr = 0x08;
	*duart3_mcr = 0x08;

	return (0);
}
Esempio n. 18
0
static const struct sigevent *spi_intr(void *area, int id)
{
    int channel_id = 0;
    uint32_t reg_value = 0;
    uintptr_t	base;
    int 		i, expected;
    omap3_spi_t	*dev = area;
    base = dev->vbase;

    reg_value = in32(base + OMAP3_MCSPI_IRQ_STATUS_OFFSET);

    /* The code below detects on which channel the interrupt
     * has occured.
     */
    if(reg_value & 0x0F)
        channel_id = OMAP3_SPI_MASTER_CHANNEL_ONE;
    else {
        if(reg_value & 0x70)
            channel_id = OMAP3_SPI_MASTER_CHANNEL_TWO;
        else {
            if(reg_value & 0x700)
                channel_id = OMAP3_SPI_MASTER_CHANNEL_THREE;
            else
                channel_id = OMAP3_SPI_MASTER_CHANNEL_FOUR;
        }
    }

    /* Clear the interupt */
    out32(base + OMAP3_MCSPI_IRQ_STATUS_OFFSET, reg_value);

    if (channel_id >= NUM_OF_SPI_DEVS) {
        return NULL;
    }

    /* The remaining bytes are read from the omap3_xfer function */
    if (reg_value & INTR_TYPE_EOWKE)
        return (&dev->spievent);

    /* Is Rx Full? also implies that EOW event is not raised and more data needs to be transfered */
    if (reg_value & INTR_TYPE_RX0_FULL << (channel_id * OMAP3_INTERRUPT_BITS_PER_SPI_CHANNEL)) {

        /* Bytes available in the Rx FIFO */
        expected = OMAP3_SPI_FIFOLEN * dev->dlen;
        for(i = 0; i < expected; i += dev->dlen, dev->rlen += dev->dlen) {
            switch (dev->dlen) {
            case 1:
                dev->pbuf[dev->rlen] = in32(base + OMAP3_MCSPI_CH1_RX_BUFFER_OFFSET + (OMAP3_SPI_DEVICE_OFFSET * channel_id));
                break;
            case 2:
                *(uint16_t *)(&dev->pbuf[dev->rlen]) = in32(base + OMAP3_MCSPI_CH1_RX_BUFFER_OFFSET + (OMAP3_SPI_DEVICE_OFFSET * channel_id));
                break;
            default:
                *(uint32_t *)(&dev->pbuf[dev->rlen]) = in32(base + OMAP3_MCSPI_CH1_RX_BUFFER_OFFSET + (OMAP3_SPI_DEVICE_OFFSET * channel_id));
                break;
            }
        }

        /* number of bytes to be sent */
        expected = min(OMAP3_SPI_FIFOLEN * dev->dlen, dev->xlen - dev->tlen);
        if (expected) {
            for (i = 0; i < expected; i += dev->dlen) {
                switch(dev->dlen) {
                case 1:
                    out32(base + OMAP3_MCSPI_CH1_TX_BUFFER_OFFSET + OMAP3_SPI_DEVICE_OFFSET * channel_id, dev->pbuf[dev->tlen + i]);
                    break;
                case 2:
                    out32(base + OMAP3_MCSPI_CH1_TX_BUFFER_OFFSET + OMAP3_SPI_DEVICE_OFFSET * channel_id, *(uint16_t *)(&dev->pbuf[dev->tlen + i]));
                    break;
                default:
                    out32(base + OMAP3_MCSPI_CH1_TX_BUFFER_OFFSET + OMAP3_SPI_DEVICE_OFFSET * channel_id, *(uint32_t *)(&dev->pbuf[dev->tlen + i]));
                    break;
                }
            }

            dev->tlen += expected;
        }
    }

    return NULL;
}
Esempio n. 19
0
// Function Specification
//
// Name: task_check_for_checkstop
//
// Description: Check for checkstop
//
// End Function Specification
void task_check_for_checkstop(task_t *i_self)
{
    pore_status_t l_gpe0_status;
    ocb_oisr0_t l_oisr0_status;
    static bool L_checkstop_traced = FALSE;
    uint8_t l_reason_code = 0;

    do
    {
        // This check is disabled once a checkstop or frozen GPE is detected
        if(L_checkstop_traced)
        {
            break;
        }

        // Looked for a frozen GPE, a sign that the chip has stopped working or
        // check-stopped.  This check also looks for an interrupt status flag that
        // indicates if the system has check-stopped.
        l_gpe0_status.value = in64(PORE_GPE0_STATUS);
        l_oisr0_status.value = in32(OCB_OISR0);

        if (l_gpe0_status.fields.freeze_action
            ||
            l_oisr0_status.fields.check_stop)
        {
            errlHndl_t l_err = NULL;

            if (l_gpe0_status.fields.freeze_action)
            {
                TRAC_IMP("Frozen GPE0 detected by RTL");
                l_reason_code = OCC_GPE_HALTED;
            }

            if (l_oisr0_status.fields.check_stop)
            {
                TRAC_IMP("System checkstop detected by RTL");
                l_reason_code = OCC_SYSTEM_HALTED;
            }

            L_checkstop_traced = TRUE;

            /*
             * @errortype
             * @moduleid    MAIN_SYSTEM_HALTED_MID
             * @reasoncode  OCC_GPE_HALTED
             * @userdata1   High order word of PORE_GPE0_STATUS
             * @userdata2   OCB_OISR0
             * @devdesc     OCC detected frozen GPE0
             */
            /*
             * @errortype
             * @moduleid    MAIN_SYSTEM_HALTED_MID
             * @reasoncode  OCC_SYSTEM_HALTED
             * @userdata1   High order word of PORE_GPE0_STATUS
             * @userdata2   OCB_OISR0
             * @devdesc     OCC detected system checkstop
             */
             l_err = createErrl(MAIN_SYSTEM_HALTED_MID,
                                l_reason_code,
                                OCC_NO_EXTENDED_RC,
                                ERRL_SEV_INFORMATIONAL,
                                NULL,
                                DEFAULT_TRACE_SIZE,
                                l_gpe0_status.words.high_order,
                                l_oisr0_status.value);

             // The commit code will check for the frozen GPE0 and system
             // checkstop conditions and take appropriate actions.
             commitErrl(&l_err);
        }
    }
    while(0);
}
Esempio n. 20
0
/*
 * Initialise one of the serial ports
 */
void
init_sa1100(unsigned channel, const char *init, const char *defaults)
{
	paddr_t		base;
	unsigned	baud;
	unsigned	brd;
	unsigned	clk;
	int			alt;

	/*
	 * Default clock rate is 3.6864MHz
	 */
	clk = 3686400;
	alt = 0;

	parse_line(channel, defaults, &baud, &clk, &alt);
	parse_line(channel, init, &baud, &clk, &alt);
	base = dbg_device[channel].base;

	brd = (clk / (16 * baud)) - 1;

	if (base == SA1100_UART1_BASE) {
		if (alt) {
			unsigned	tmp;

			/*
			 * Re-assign UART1 to driver GPIO pins 14/15
			 */
			out32(SA1100_PPC_BASE + SA1100_PPAR, SA1100_PPAR_UPR);

			/*
			 * Configure GPIO pin 14 as an output, pin 15 as an input
			 */
			tmp = in32(SA1100_GPIO_BASE + SA1100_GPDR);
			tmp |= SA1100_GPIO_14;
			tmp &= ~SA1100_GPIO_15;
			out32(SA1100_GPIO_BASE + SA1100_GPDR, tmp);

			/*
			 * Configure GPIO pins 14/15 to use their alternate functions
			 */
			tmp = in32(SA1100_GPIO_BASE + SA1100_GAFR);
			tmp |= SA1100_GPIO_14 | SA1100_GPIO_15;
			out32(SA1100_GPIO_BASE + SA1100_GAFR, tmp);
		}
		else {
			/*
			 * Enable UART1 output onto serial port 1 pins
			 */
			out32(SA1100_SDLC_BASE + SA1100_SDCR0, SA1100_SDCR0_SUS);
		}
	}

	/*
	 * Disable UART while programming baud rate divisor
	 */
	while (in32(base + SA1100_UTSR1) & SA1100_UTSR1_TBY)
		;
	out32(base + SA1100_UTCR3, 0);
	out32(base + SA1100_UTBRD_HI, (brd >> 8) & 0xf);
	out32(base + SA1100_UTBRD_LO, brd & 0xff);

	/*
	 * Clear status bits
	 * Set 8bits, no parity, 1 stop bit
	 */
	out32(base + SA1100_UTSR0, 0xff);
	out32(base + SA1100_UTCR0, SA1100_UTCR0_DSS);

	/*
	 * Re-enable receive and transmit
	 */
	out32(base + SA1100_UTCR3, SA1100_UTCR3_RXE | SA1100_UTCR3_TXE);
}
Esempio n. 21
0
static int fpga_boot (const unsigned char *fpgadata, int size)
{
	int i, index, len;
	int count;
	unsigned char b;

#ifdef CFG_FPGA_SPARTAN2
	int j;
#else
	int bit;
#endif

	/* display infos on fpgaimage */
	index = 15;
	for (i = 0; i < 4; i++) {
		len = fpgadata[index];
		DBG ("FPGA: %s\n", &(fpgadata[index + 1]));
		index += len + 3;
	}

#ifdef CFG_FPGA_SPARTAN2
	/* search for preamble 0xFFFFFFFF */
	while (1) {
		if ((fpgadata[index] == 0xff) && (fpgadata[index + 1] == 0xff)
		    && (fpgadata[index + 2] == 0xff)
		    && (fpgadata[index + 3] == 0xff))
			break;	/* preamble found */
		else
			index++;
	}
#else
	/* search for preamble 0xFF2X */
	for (index = 0; index < size - 1; index++) {
		if ((fpgadata[index] == 0xff)
		    && ((fpgadata[index + 1] & 0xf0) == 0x30))
			break;
	}
	index += 2;
#endif

	DBG ("FPGA: configdata starts at position 0x%x\n", index);
	DBG ("FPGA: length of fpga-data %d\n", size - index);

	/*
	 * Setup port pins for fpga programming
	 */
#ifndef CONFIG_M5249
	out32 (GPIO0_ODR, 0x00000000);	/* no open drain pins */
	out32 (GPIO0_TCR, in32 (GPIO0_TCR) | FPGA_PRG | FPGA_CLK | FPGA_DATA);	/* setup for output */
#endif
	SET_FPGA (FPGA_PRG_HIGH | FPGA_CLK_HIGH | FPGA_DATA_HIGH);	/* set pins to high */

	DBG ("%s, ", (FPGA_DONE_STATE == 0) ? "NOT DONE" : "DONE");
	DBG ("%s\n", (FPGA_INIT_STATE == 0) ? "NOT INIT" : "INIT");

	/*
	 * Init fpga by asserting and deasserting PROGRAM*
	 */
	SET_FPGA (FPGA_PRG_LOW | FPGA_CLK_HIGH | FPGA_DATA_HIGH);	/* set prog active */

	/* Wait for FPGA init line low */
	count = 0;
	while (FPGA_INIT_STATE) {
		udelay (1000);	/* wait 1ms */
		/* Check for timeout - 100us max, so use 3ms */
		if (count++ > 3) {
			DBG ("FPGA: Booting failed!\n");
			return ERROR_FPGA_PRG_INIT_LOW;
		}
	}

	DBG ("%s, ", (FPGA_DONE_STATE == 0) ? "NOT DONE" : "DONE");
	DBG ("%s\n", (FPGA_INIT_STATE == 0) ? "NOT INIT" : "INIT");

	/* deassert PROGRAM* */
	SET_FPGA (FPGA_PRG_HIGH | FPGA_CLK_HIGH | FPGA_DATA_HIGH);	/* set prog inactive */

	/* Wait for FPGA end of init period .  */
	count = 0;
	while (!(FPGA_INIT_STATE)) {
		udelay (1000);	/* wait 1ms */
		/* Check for timeout */
		if (count++ > 3) {
			DBG ("FPGA: Booting failed!\n");
			return ERROR_FPGA_PRG_INIT_HIGH;
		}
	}

	DBG ("%s, ", (FPGA_DONE_STATE == 0) ? "NOT DONE" : "DONE");
	DBG ("%s\n", (FPGA_INIT_STATE == 0) ? "NOT INIT" : "INIT");

	DBG ("write configuration data into fpga\n");
	/* write configuration-data into fpga... */

#ifdef CFG_FPGA_SPARTAN2
	/*
	 * Load uncompressed image into fpga
	 */
	for (i = index; i < size; i++) {
		b = fpgadata[i];
		for (j = 0; j < 8; j++) {
			if ((b & 0x80) == 0x80) {
				FPGA_WRITE_1;
			} else {
				FPGA_WRITE_0;
			}
			b <<= 1;
		}
	}
#else
	/* send 0xff 0x20 */
	FPGA_WRITE_1;
	FPGA_WRITE_1;
	FPGA_WRITE_1;
	FPGA_WRITE_1;
	FPGA_WRITE_1;
	FPGA_WRITE_1;
	FPGA_WRITE_1;
	FPGA_WRITE_1;
	FPGA_WRITE_0;
	FPGA_WRITE_0;
	FPGA_WRITE_1;
	FPGA_WRITE_0;
	FPGA_WRITE_0;
	FPGA_WRITE_0;
	FPGA_WRITE_0;
	FPGA_WRITE_0;

	/*
	 ** Bit_DeCompression
	 **   Code 1           .. maxOnes     : n                 '1's followed by '0'
	 **        maxOnes + 1 .. maxOnes + 1 : n - 1             '1's no '0'
	 **        maxOnes + 2 .. 254         : n - (maxOnes + 2) '0's followed by '1'
	 **        255                        :                   '1'
	 */

	for (i = index; i < size; i++) {
		b = fpgadata[i];
		if ((b >= 1) && (b <= MAX_ONES)) {
			for (bit = 0; bit < b; bit++) {
				FPGA_WRITE_1;
			}
			FPGA_WRITE_0;
		} else if (b == (MAX_ONES + 1)) {
			for (bit = 1; bit < b; bit++) {
				FPGA_WRITE_1;
			}
		} else if ((b >= (MAX_ONES + 2)) && (b <= 254)) {
			for (bit = 0; bit < (b - (MAX_ONES + 2)); bit++) {
				FPGA_WRITE_0;
			}
			FPGA_WRITE_1;
		} else if (b == 255) {
			FPGA_WRITE_1;
		}
	}
#endif

	DBG ("%s, ", (FPGA_DONE_STATE == 0) ? "NOT DONE" : "DONE");
	DBG ("%s\n", (FPGA_INIT_STATE == 0) ? "NOT INIT" : "INIT");

	/*
	 * Check if fpga's DONE signal - correctly booted ?
	 */

	/* Wait for FPGA end of programming period .  */
	count = 0;
	while (!(FPGA_DONE_STATE)) {
		udelay (1000);	/* wait 1ms */
		/* Check for timeout */
		if (count++ > 3) {
			DBG ("FPGA: Booting failed!\n");
			return ERROR_FPGA_PRG_DONE;
		}
	}

	DBG ("FPGA: Booting successful!\n");
	return 0;
}
Esempio n. 22
0
static int omap3_interrupt(SIM_HBA *hba, int irq, int resp_type, uint32_t *resp)
{
	SIM_MMC_EXT		*ext;
	omap3_ext_t		*omap3;
	uint32_t		sts;
	int				intr = 0;
	uintptr_t		base;

	ext   = (SIM_MMC_EXT *)hba->ext;
	omap3 = (omap3_ext_t *)ext->handle;
	base  = omap3->mmc_base;

	sts = in32(base + OMAP3_MMCHS_STAT);
	sts &= in32(base + OMAP3_MMCHS_IE) | INTR_ERRI;
	out32(base + OMAP3_MMCHS_STAT, sts);

	if (sts & INTR_ERRI) {	// Any errors ?
		slogf(_SLOGC_SIM_MMC, _SLOG_ERROR, "OMAP3 interrupt error = %x", sts);
		intr |= MMC_INTR_ERROR | MMC_INTR_COMMAND;
		if (sts & INTR_DTO) {
			intr |= MMC_ERR_DATA_TO;
			out32(base + OMAP3_MMCHS_SYSCTL, in32(base + OMAP3_MMCHS_SYSCTL) | SYSCTL_SRD);
			while (in32(base + OMAP3_MMCHS_SYSCTL) & SYSCTL_SRD);
		}
		if (sts & INTR_DCRC)
			intr |= MMC_ERR_DATA_CRC;
		if (sts & INTR_DEB)
			intr |= MMC_ERR_DATA_END;

		if (sts & INTR_CTO) {
			intr |= MMC_ERR_CMD_TO;
			out32(base + OMAP3_MMCHS_SYSCTL, in32(base + OMAP3_MMCHS_SYSCTL) | SYSCTL_SRC);
			while (in32(base + OMAP3_MMCHS_SYSCTL) & SYSCTL_SRC);
		}
		if (sts & INTR_CCRC)
			intr |= MMC_ERR_CMD_CRC;
		if (sts & INTR_CEB)
			intr |= MMC_ERR_CMD_END;
		if (sts & INTR_CIE)
			intr |= MMC_ERR_CMD_IDX;
	} else {
		if (sts & INTR_CC) {
			intr |= MMC_INTR_COMMAND;
			if (resp) {
				if (resp_type & MMC_RSP_136) {
					resp[3] = in32(base + OMAP3_MMCHS_RSP76);
					resp[2] = in32(base + OMAP3_MMCHS_RSP54);
					resp[1] = in32(base + OMAP3_MMCHS_RSP32);
					resp[0] = in32(base + OMAP3_MMCHS_RSP10);
				} else if (resp_type & MMC_RSP_PRESENT)
					resp[0] = in32(base + OMAP3_MMCHS_RSP10);
			}

			// Busy check?
			if (resp_type & MMC_RSP_BUSY) {
				int		i;

				for (i = 1024 * 256; i > 0; i--) {
					if (in32(base + OMAP3_MMCHS_PSTATE) & PSTATE_DLA) {
						nanospin_ns(1024);
						continue;
					}
					break;
				}
				if (i <= 0) {
					intr |= MMC_ERR_CMD_TO | MMC_INTR_ERROR;
					slogf(_SLOGC_SIM_MMC, _SLOG_ERROR, "OMAP3 busy check time out");
				}
			}
		}

		if (sts & (INTR_TC | INTR_BWR | INTR_BRR)) {
			if (sts & INTR_TC)
				intr |= MMC_INTR_DATA;
			if (sts & INTR_BRR)
				intr |= MMC_INTR_RBRDY;
			if (sts & INTR_BWR)
				intr |= MMC_INTR_WBRDY;

		}
	}

	if (intr)
		out32(base + OMAP3_MMCHS_IE, 0);

	return intr;
}
Esempio n. 23
0
int emac4xx_miiphy_write (char *devname, unsigned char addr,
		unsigned char reg, unsigned short value)
{
	unsigned long sta_reg;	/* STA scratch area */
	unsigned long i;
	unsigned long emac_reg;

	emac_reg = miiphy_getemac_offset ();
	/* see if it is ready for 1000 nsec */
	i = 0;

	while ((in32 (EMAC_STACR + emac_reg) & EMAC_STACR_OC) == EMAC_STACR_OC_MASK) {
		if (i > 5)
			return -1;
		udelay (7);
		i++;
	}
	sta_reg = 0;
	sta_reg = reg;		/* reg address */
	/* set clock (50Mhz) and read flags */
#if defined(CONFIG_440GX) || defined(CONFIG_440SPE) || \
    defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
#if defined(CONFIG_IBM_EMAC4_V4)      /* EMAC4 V4 changed bit setting */
		sta_reg = (sta_reg & ~EMAC_STACR_OP_MASK) | EMAC_STACR_WRITE;
#else
		sta_reg |= EMAC_STACR_WRITE;
#endif
#else
	sta_reg = (sta_reg | EMAC_STACR_WRITE) & ~EMAC_STACR_CLK_100MHZ;
#endif

#if defined(CONFIG_PHY_CLK_FREQ) && !defined(CONFIG_440GX) && \
    !defined(CONFIG_440SP) && !defined(CONFIG_440SPE) && \
    !defined(CONFIG_440EPX) && !defined(CONFIG_440GRX)
	sta_reg = sta_reg | CONFIG_PHY_CLK_FREQ;	/* Set clock frequency (PLB freq. dependend) */
#endif
	sta_reg = sta_reg | ((unsigned long) addr << 5);/* Phy address */
	sta_reg = sta_reg | EMAC_STACR_OC_MASK;		/* new IBM emac v4 */
	memcpy (&sta_reg, &value, 2);	/* put in data */

	out32 (EMAC_STACR + emac_reg, sta_reg);

	/* wait for completion */
	i = 0;
	sta_reg = in32 (EMAC_STACR + emac_reg);
#ifdef ET_DEBUG
		printf ("a31: read : EMAC_STACR=0x%0x\n", sta_reg);	/* test-only */
#endif
	while ((sta_reg & EMAC_STACR_OC) == EMAC_STACR_OC_MASK) {
		udelay (7);
		if (i > 5)
			return -1;
		i++;
		sta_reg = in32 (EMAC_STACR + emac_reg);
#ifdef ET_DEBUG
		printf ("a32: read : EMAC_STACR=0x%0x\n", sta_reg);	/* test-only */
#endif
	}

	if ((sta_reg & EMAC_STACR_PHYE) != 0)
		return -1;
	return 0;

}				/* phy_write */
Esempio n. 24
0
static unsigned
timer_start_ixp1200()
{
	return in32(ixp1200_timer_base + IXP1200_TIMER_1_VALUE);
}
Esempio n. 25
0
static unsigned
timer_start_ixp425()
{
	return in32(ixp425_timer_base + IXP425_TIMER0_VAL);
}
Esempio n. 26
0
void
init_qtime_ixp1200()
{
	struct qtime_entry	*qtime = alloc_qtime();
	unsigned			pll;
	static const char	pll_mult[] = {
		/*
		 * Multiplier for IXP1200_CLOCK_FREQ for PLL_CFG values
		 * FIXME: these are taken from the Programmer's Reference Manual,
		 *        but I'm not sure they are actually 100% correct...
		 */
		8,
		10,
		12,
		14,
		16,
		18,
		20,
		22,
		24,
		26,
		28,
		30,
		36,
		40,
		42,
		44,
		45,
		48,
		52,
		54,
		56,
		60,
		63
	};

	/*
	 * Map the timer registers
	 */
	ixp1200_timer_base = startup_io_map(IXP1200_TIMER_SIZE, IXP1200_TIMER_BASE);

	/*
	 * Calulate CPU core PLL frequency
	 */
	pll = in32(IXP1200_PLL_CFG_BASE) & IXP1200_PLL_CFG_CCF;
	if (pll > 22) {
		crash("PLL_CFG is %d. Max supported value is 22\n", pll);
	}
	pll = IXP1200_CLOCK_FREQ * pll_mult[pll];

	/*
	 * Set the timer free running, divide by 16, with maximum countdown
	 */
	pll = pll / 16;	
	out32(ixp1200_timer_base + IXP1200_TIMER_1_LOAD, 0x00ffffff);
	out32(ixp1200_timer_base + IXP1200_TIMER_1_CONTROL, IXP1200_TIMER_CONTROL_EN | IXP1200_TIMER_CONTROL_STP_16 | IXP1200_TIMER_CONTROL_FREE);

	timer_start = timer_start_ixp1200;
	timer_diff = timer_diff_ixp1200;

	qtime->intr = 36;

	qtime->timer_rate  = IXP1200_CLOCK_RATE;
	qtime->timer_scale = IXP1200_CLOCK_SCALE;
	qtime->cycles_per_sec = (uint64_t)pll;
	invert_timer_freq(qtime, pll);

	add_callout_array(timer_callouts, sizeof(timer_callouts));
}
Esempio n. 27
0
void *omap3_xfer(void *hdl, uint32_t device, uint8_t *buf, int *len)
{
	omap3_spi_t	*dev = hdl;
	uintptr_t		base = dev->vbase;
	uint32_t	 	id;
	int 			i;
	int 			timeout, expected;
	uint32_t 		reg_value = 0;

	id = device & SPI_DEV_ID_MASK;
	if (id >=dev->num_cs) {
		*len = -1;
		return buf;
	}

	dev->xlen = *len;
	// Cannot set more than 64KB of data at one time
	if(dev->xlen>(64 * 1024))
	{
		*len = -1;
		return buf;
	}
	dev->rlen = 0;
	dev->tlen = min(OMAP3_SPI_FIFOLEN, dev->xlen);
	dev->pbuf = buf;
	dev->dlen = ((devlist[id].cfg.mode & SPI_MODE_CHAR_LEN_MASK) + 7) >> 3;
	
    // Estimate transfer time in us... The calculated dtime is only used for
    // the timeout, so it doesn't have to be that accurate.  At higher clock
    // rates, a calcuated dtime of 0 would mess-up the timeout calculation, so
    // round up to 1 us
	dev->dtime = dev->dlen * 1000 * 1000 / devlist[id].cfg.clock_rate;
    if (dev->dtime == 0)
		dev->dtime = 1;

	omap3_setup(dev, device);

	/* force CS */
	set_port((base + OMAP3_MCSPI_CH1_CONFIG_OFFSET + 0x14*id),OMAP3_MCSPI_FORCE_MODE_ONE, OMAP3_MCSPI_FORCE_MODE_ONE);

	/*set FIFO */
	set_port((base + OMAP3_MCSPI_CH1_CONFIG_OFFSET + 0x14*id),  OMAP3_MCSPI_FFER | OMAP3_MCSPI_FFEW ,  OMAP3_MCSPI_FFER | OMAP3_MCSPI_FFEW );  
	out32(base + OMAP3_MCSPI_XFERLEVEL_OFFSET , (dev->xlen<<16) | 0xF<<8 | 0xF);   /* set transfer levels :MCBSP_FIFO_THRESHOLD= 16-1*/

	/* Configue the SPI control register to enable the corresponding channel of the SPI */
 	set_port(base + OMAP3_MCSPI_CH1_CTRL_OFFSET+0x14*id, OMAP3_MCSPI_CHANNEL_ENABLE, OMAP3_MCSPI_CHANNEL_ENABLE);

	// Clear any pending interrupts
	out32(base + OMAP3_MCSPI_IRQ_STATUS_OFFSET, 0xF );

	/* start the data transmit.....this happens by writing data to
	* the corresponding transmit register. This module has been  
	* designed for Transmit/Recieve Mode. This part will change  
	* according to the design. 
	*/
	for(i=0; i<dev->tlen; i++){ 
		out32(base + OMAP3_MCSPI_CH1_TX_BUFFER_OFFSET + 0x14*id, dev->pbuf[i]);
	}	

	/* Enable Interrupts */
	out32(base + OMAP3_MCSPI_IRQ_ENABLE_OFFSET, INTR_TYPE_EOWKE + (INTR_TYPE_RX0_FULL << (id * OMAP3_INTERRUPT_BITS_PER_SPI_CHANNEL)) );

	/*
	* Wait for exchange to finish
	*/
	if (omap3_wait(dev, dev->xlen * 10)) {
		fprintf(stderr, "OMAP3 SPI: XFER Timeout!!!\n");
		dev->rlen = -1;
	}

	// Read the last spi words
	if(dev->rlen < dev->xlen && dev->rlen != -1) {
		reg_value = in32(base + OMAP3_MCSPI_CH1_STATUS_OFFSET + (OMAP3_SPI_DEVICE_OFFSET * id));
		timeout = 1000;
		while( timeout-- && ((reg_value & OMAP3_MCSPI_CH_RX_REG_FULL) == 0) ) {
			nanospin_ns(100);
			reg_value = in32(base + OMAP3_MCSPI_CH1_STATUS_OFFSET + (OMAP3_SPI_DEVICE_OFFSET * id));
		}
		
		if(timeout <= 0) {
			dev->rlen = -1;
		}
		else {
			// last words to read from buffer
			expected = dev->tlen - dev->rlen;
			for(i = 0; i < expected; i++) {
				dev->pbuf[dev->rlen++] = in32(base + OMAP3_MCSPI_CH1_RX_BUFFER_OFFSET + (OMAP3_SPI_DEVICE_OFFSET * id));
			}
		}
	}

	//disable interrupts
    out32(base + OMAP3_MCSPI_IRQ_ENABLE_OFFSET, 0);	

	/*un-force CS */
	set_port((base + OMAP3_MCSPI_CH1_CONFIG_OFFSET + 0x14*id),OMAP3_MCSPI_FORCE_MODE_ONE, 0);

	set_port(base + OMAP3_MCSPI_CH1_CTRL_OFFSET + 0x14*id, OMAP3_MCSPI_CHANNEL_ENABLE, 0);
	set_port(base + OMAP3_MCSPI_CH1_CONFIG_OFFSET + 0x14*id,  OMAP3_MCSPI_FFER|OMAP3_MCSPI_FFEW, 0);
	out32(base + OMAP3_MCSPI_XFERLEVEL_OFFSET , 0);  
	
    *len = dev->rlen;

    return buf;
}
Esempio n. 28
0
/*---------------------------------------------------------------------------*/
void     pci_read (usys reg, usys *val)
{
    out32 (0xcf8, reg)  ;
    *val = in32 (0xcfc) ;
} /* End of function pci_read() */
Esempio n. 29
0
static unsigned
timer_start_pxa270()
{
	return in32(pxa270_timer_base + PXA250_OSCR);
}
Esempio n. 30
0
int omap3530_wait(omap3530_spi_t *dev, int len)
{
	struct _pulse	 pulse;
	int rx_idx = dev->sdma_rx_chid;
	
	while (1) {
		if (len) {
			uint64_t	to = dev->dtime * 1000 * 50; /* 50 times for time out */
			to *= len ;	
			TimerTimeout(CLOCK_REALTIME, _NTO_TIMEOUT_RECEIVE, NULL, &to, NULL);
		}
		if (MsgReceivePulse(dev->chid, &pulse, sizeof(pulse), NULL) == -1){
			fprintf(stderr, "omap3530_wait: errono %s(%d), status %x\n", strerror(errno), errno, in32(dev->vbase+ OMAP3530_MCSPI_IRQ_STATUS_OFFSET));
			return -1;
		}

		switch (pulse.code) {
			case OMAP3530_SPI_EVENT:
					return 0;
			case OMAP3530_SDMA_EVENT:
				{
					/* Unmask the Interrupt */
					InterruptUnmask(dev->irq_sdma+rx_idx, dev->iid_sdma);
					if ((dev->dma4->channel[rx_idx].csr & DMA4_CSR_FRAME)){
						/* clear interrupt status line 0 for transmit channel */
						dev->dma4->channel[rx_idx].csr |= DMA4_CSR_FRAME;
						return 0;
					}else {
						  continue;
					}
				}
		}
	}

	return 0;
}