void __init arch_init_irq(void) { /* hardware initialization */ nile4_irq_setup(); m1543_irq_setup(); /* controller setup */ init_i8259_irqs(); vrc5476_irq_init(VRC5476_IRQ_BASE); mips_cpu_irq_init(CPU_IRQ_BASE); /* setup cascade interrupts */ setup_irq(VRC5476_IRQ_BASE + VRC5476_I8259_CASCADE, &irq_cascade); setup_irq(CPU_IRQ_BASE + CPU_VRC5476_CASCADE, &irq_cascade); /* setup error interrupts for debugging */ setup_irq(VRC5476_IRQ_BASE + VRC5476_IRQ_CPCE, &irq_error); setup_irq(VRC5476_IRQ_BASE + VRC5476_IRQ_CNTD, &irq_error); setup_irq(VRC5476_IRQ_BASE + VRC5476_IRQ_MCE, &irq_error); setup_irq(VRC5476_IRQ_BASE + VRC5476_IRQ_LBRT, &irq_error); setup_irq(VRC5476_IRQ_BASE + VRC5476_IRQ_PCIS, &irq_error); setup_irq(VRC5476_IRQ_BASE + VRC5476_IRQ_PCI, &irq_error); /* setup the grandpa intr vector */ set_except_vector(0, ddb5476_handle_int); }
void __init arch_init_irq(void) { mips_hpt_frequency = QEMU_C0_COUNTER_CLOCK; /* 100MHz */ init_i8259_irqs(); set_c0_status(0x8400); }
void i8259_init(void) { init_i8259_irqs(); outb(0x00, 0x4d0); outb(0x02, 0x4d1); /* USB IRQ9 is level */ }
/* * On systems with i8259-style interrupt controllers we assume for * driver compatibility reasons interrupts 0 - 15 to be the i8295 * interrupts even if the hardware uses a different interrupt numbering. */ void __init arch_init_irq(void) { init_i8259_irqs(); /* Integrated i8259 */ switch (sni_brd_type) { case SNI_BRD_10: case SNI_BRD_10NEW: case SNI_BRD_TOWER_OASIC: case SNI_BRD_MINITOWER: sni_a20r_irq_init(); break; case SNI_BRD_PCI_TOWER: sni_pcit_irq_init(); break; case SNI_BRD_PCI_TOWER_CPLUS: sni_pcit_cplus_irq_init(); break; case SNI_BRD_RM200: sni_rm200_irq_init(); break; case SNI_BRD_PCI_MTOWER: case SNI_BRD_PCI_DESKTOP: case SNI_BRD_PCI_MTOWER_CPLUS: sni_pcimt_irq_init(); break; } }
void rs780e_init_irq(void) { /* Route the HT interrupt to Core0 INT1 */ INT_router_regs_HT1_int0 = 0x20 | (1 << phy_core_id[0]); INT_router_regs_HT1_int1 = 0x20 | (1 << phy_core_id[0]); INT_router_regs_HT1_int2 = 0x20 | (1 << phy_core_id[0]); INT_router_regs_HT1_int3 = 0x20 | (1 << phy_core_id[0]); INT_router_regs_HT1_int4 = 0x20 | (1 << phy_core_id[0]); INT_router_regs_HT1_int5 = 0x20 | (1 << phy_core_id[0]); INT_router_regs_HT1_int6 = 0x20 | (1 << phy_core_id[0]); INT_router_regs_HT1_int7 = 0x20 | (1 << phy_core_id[0]); /* Enable the all HT interrupt */ HT_irq_enable_reg0 = 0x0000ffff; HT_irq_enable_reg1 = 0x00000000; HT_irq_enable_reg2 = 0x00000000; HT_irq_enable_reg3 = 0x00000000; HT_irq_enable_reg4 = 0x00000000; HT_irq_enable_reg5 = 0x00000000; HT_irq_enable_reg6 = 0x00000000; HT_irq_enable_reg7 = 0x00000000; /* Enable the IO interrupt controller */ IO_control_regs_Intenset = IO_control_regs_Inten | (0xffff << 16); prom_printf("the new IO inten is %x\n", IO_control_regs_Inten); /* Sets the first-level interrupt dispatcher. */ mips_cpu_irq_init(); #ifdef CONFIG_I8259 init_i8259_irqs(); #endif set_c0_status(STATUSF_IP6); mach_ip3 = dispatch_ht_irq; }
void __init arch_init_irq(void) { mips_cpu_irq_init(); gt641xx_irq_init(); init_i8259_irqs(); setup_irq(GT641XX_CASCADE_IRQ, &cascade); setup_irq(I8259_CASCADE_IRQ, &cascade); }
void __init arch_init_irq(void) { /* by default, we disable all interrupts and route all vrc5477 * interrupts to pin 0 (irq 2) */ ddb_out32(DDB_INTCTRL0, 0); ddb_out32(DDB_INTCTRL1, 0); ddb_out32(DDB_INTCTRL2, 0); ddb_out32(DDB_INTCTRL3, 0); clear_c0_status(0xff00); set_c0_status(0x0400); /* setup PCI interrupt attributes */ set_pci_int_attr(PCI0, INTA, ACTIVE_LOW, LEVEL_SENSE); set_pci_int_attr(PCI0, INTB, ACTIVE_LOW, LEVEL_SENSE); if (mips_machtype == MACH_NEC_ROCKHOPPERII) set_pci_int_attr(PCI0, INTC, ACTIVE_HIGH, LEVEL_SENSE); else set_pci_int_attr(PCI0, INTC, ACTIVE_LOW, LEVEL_SENSE); set_pci_int_attr(PCI0, INTD, ACTIVE_LOW, LEVEL_SENSE); set_pci_int_attr(PCI0, INTE, ACTIVE_LOW, LEVEL_SENSE); set_pci_int_attr(PCI1, INTA, ACTIVE_LOW, LEVEL_SENSE); set_pci_int_attr(PCI1, INTB, ACTIVE_LOW, LEVEL_SENSE); set_pci_int_attr(PCI1, INTC, ACTIVE_LOW, LEVEL_SENSE); set_pci_int_attr(PCI1, INTD, ACTIVE_LOW, LEVEL_SENSE); set_pci_int_attr(PCI1, INTE, ACTIVE_LOW, LEVEL_SENSE); /* * for debugging purpose, we enable several error interrupts * and route them to pin 1. (IP3) */ /* cpu parity check - 0 */ ll_vrc5477_irq_route(0, 1); ll_vrc5477_irq_enable(0); /* cpu no-target decode - 1 */ ll_vrc5477_irq_route(1, 1); ll_vrc5477_irq_enable(1); /* local bus read time-out - 7 */ ll_vrc5477_irq_route(7, 1); ll_vrc5477_irq_enable(7); /* PCI SERR# - 14 */ ll_vrc5477_irq_route(14, 1); ll_vrc5477_irq_enable(14); /* PCI internal error - 15 */ ll_vrc5477_irq_route(15, 1); ll_vrc5477_irq_enable(15); /* IOPCI SERR# - 30 */ ll_vrc5477_irq_route(30, 1); ll_vrc5477_irq_enable(30); /* IOPCI internal error - 31 */ ll_vrc5477_irq_route(31, 1); ll_vrc5477_irq_enable(31); /* init all controllers */ init_i8259_irqs(); mips_cpu_irq_init(); vrc5477_irq_init(VRC5477_IRQ_BASE); /* setup cascade interrupts */ setup_irq(VRC5477_IRQ_BASE + VRC5477_I8259_CASCADE, &irq_cascade); setup_irq(CPU_IRQ_BASE + CPU_VRC5477_CASCADE, &irq_cascade); }
void __init init_IRQ(void) { set_except_vector(0, cobalt_handle_int); init_i8259_irqs(); /* 0 ... 15 */ mips_cpu_irq_init(16); /* 16 ... 23 */ /* * Mask all cpu interrupts * (except IE4, we already masked those at VIA level) */ change_c0_status(ST0_IM, IE_IRQ4); }
/* * On systems with i8259-style interrupt controllers we assume for * driver compatibility reasons interrupts 0 - 15 to be the i8295 * interrupts even if the hardware uses a different interrupt numbering. */ void __init arch_init_irq(void) { int i; init_i8259_irqs(); /* Integrated i8259 */ init_pciasic(); /* Actually we've got more interrupts to handle ... */ for (i = PCIMT_IRQ_INT2; i <= PCIMT_IRQ_ETHERNET; i++) set_irq_chip(i, &pciasic_irq_type); change_c0_status(ST0_IM, IE_IRQ1|IE_IRQ2|IE_IRQ3|IE_IRQ4); }
void __init init_IRQ(void) { set_except_vector(0, mipsIRQ); init_generic_irq(); init_i8259_irqs(); #ifdef CONFIG_REMOTE_DEBUG if (remote_debug) { set_debug_traps(); breakpoint(); } #endif }
void __init arch_init_irq(void) { extern void tx4927_irq_init(void); tx4927_irq_init(); toshiba_rbtx4927_irq_ioc_init(); #ifdef CONFIG_TOSHIBA_FPCIB0 if (tx4927_using_backplane) init_i8259_irqs(); #endif /* Onboard 10M Ether: High Active */ set_irq_type(RBTX4927_RTL_8019_IRQ, IRQF_TRIGGER_HIGH); wbflush(); }
void __init mach_init_irq(void) { clear_c0_status(ST0_IM | ST0_BEV); irq_router_init(); mips_cpu_irq_init(); init_i8259_irqs(); irq_set_chip_and_handler(LOONGSON_UART_IRQ, &loongson_irq_chip, handle_level_irq); /* setup HT1 irq */ setup_irq(LOONGSON_HT1_IRQ, &cascade_irqaction); set_c0_status(STATUSF_IP2 | STATUSF_IP6); }
void __init arch_init_irq(void) { init_i8259_irqs(); if (!cpu_has_veic) mips_cpu_irq_init(); switch(mips_revision_sconid) { case MIPS_REVISION_SCON_SOCIT: case MIPS_REVISION_SCON_ROCIT: if (cpu_has_veic) init_msc_irqs (MIPS_MSC01_IC_REG_BASE, MSC01E_INT_BASE, msc_eicirqmap, msc_nr_eicirqs); else init_msc_irqs (MIPS_MSC01_IC_REG_BASE, MSC01C_INT_BASE, msc_irqmap, msc_nr_irqs); break; case MIPS_REVISION_SCON_SOCITSC: case MIPS_REVISION_SCON_SOCITSCP: if (cpu_has_veic) init_msc_irqs (MIPS_SOCITSC_IC_REG_BASE, MSC01E_INT_BASE, msc_eicirqmap, msc_nr_eicirqs); else init_msc_irqs (MIPS_SOCITSC_IC_REG_BASE, MSC01C_INT_BASE, msc_irqmap, msc_nr_irqs); } if (cpu_has_veic) { set_vi_handler (MSC01E_INT_I8259A, malta_hw0_irqdispatch); set_vi_handler (MSC01E_INT_COREHI, corehi_irqdispatch); setup_irq (MSC01E_INT_BASE+MSC01E_INT_I8259A, &i8259irq); setup_irq (MSC01E_INT_BASE+MSC01E_INT_COREHI, &corehi_irqaction); } else if (cpu_has_vint) { set_vi_handler (MIPSCPU_INT_I8259A, malta_hw0_irqdispatch); set_vi_handler (MIPSCPU_INT_COREHI, corehi_irqdispatch); #ifdef CONFIG_MIPS_MT_SMTC setup_irq_smtc (MIPS_CPU_IRQ_BASE+MIPSCPU_INT_I8259A, &i8259irq, (0x100 << MIPSCPU_INT_I8259A)); setup_irq_smtc (MIPS_CPU_IRQ_BASE+MIPSCPU_INT_COREHI, &corehi_irqaction, (0x100 << MIPSCPU_INT_COREHI)); #else /* Not SMTC */ setup_irq (MIPS_CPU_IRQ_BASE+MIPSCPU_INT_I8259A, &i8259irq); setup_irq (MIPS_CPU_IRQ_BASE+MIPSCPU_INT_COREHI, &corehi_irqaction); #endif /* CONFIG_MIPS_MT_SMTC */ } else { setup_irq (MIPS_CPU_IRQ_BASE+MIPSCPU_INT_I8259A, &i8259irq); setup_irq (MIPS_CPU_IRQ_BASE+MIPSCPU_INT_COREHI, &corehi_irqaction); } }
void __init ht_irq_init(void) { unsigned int t; u32 i; /* * Clear all of the interrupts while we change the able around a bit. * int-handler is not on bootstrap */ clear_c0_status(ST0_IM | ST0_BEV); local_irq_disable(); /* Route the LPC interrupt to Core0 INT0 */ INT_router_regs_lpc_int = 0x11; *(volatile unsigned int *)(0x900000003ff00000 + 0x1428) = (0x1<<10);//Enable lpc interrupts /* Route the HT interrupt to Core0 INT1 */ INT_router_regs_HT1_int0 = 0x21; INT_router_regs_HT1_int1 = 0x21; INT_router_regs_HT1_int2 = 0x21; INT_router_regs_HT1_int3 = 0x21; INT_router_regs_HT1_int4 = 0x21; INT_router_regs_HT1_int5 = 0x21; INT_router_regs_HT1_int6 = 0x21; INT_router_regs_HT1_int7 = 0x21; HT_irq_enable_reg0 = 0xffffffff; HT_irq_enable_reg1 = 0x00000000; HT_irq_enable_reg2 = 0x00000000; HT_irq_enable_reg3 = 0x00000000; HT_irq_enable_reg4 = 0x00000000; HT_irq_enable_reg5 = 0x00000000; HT_irq_enable_reg6 = 0x00000000; HT_irq_enable_reg7 = 0x00000000; /* Enable the IO interrupt controller */ t = IO_control_regs_Intenset; IO_control_regs_Intenset = t | (0xffff << 16); IO_control_regs_Intenset = t | (0xffff << 16) | (0x1 << 10); t = IO_control_regs_Intenset; // for (i = I8259A_IRQ_BASE; i < I8259A_IRQ_BASE + 16; i++) // irq_set_chip_and_handler(i, &irq_type, handle_level_irq); // ke_spin_init(&ht_lock); init_i8259_irqs(); }
void __init mach_init_irq(void) { LOONGSON_INTEDGE = LOONGSON_ICU_SYSTEMERR | LOONGSON_ICU_MASTERERR | LOONGSON_ICU_RETRYERR | LOONGSON_ICU_MBOXES; mips_cpu_irq_init(); init_i8259_irqs(); bonito_irq_init(); setup_irq(MIPS_CPU_IRQ_BASE + 2, &cascade_irqaction); setup_irq(MIPS_CPU_IRQ_BASE + 5, &cascade_irqaction); }
/* * On systems with i8259-style interrupt controllers we assume for * driver compatibility reasons interrupts 0 - 15 to be the i8295 * interrupts even if the hardware uses a different interrupt numbering. */ void __init arch_init_irq(void) { int i; init_i8259_irqs(); /* Integrated i8259 */ init_pciasic(); /* Actually we've got more interrupts to handle ... */ for (i = PCIMT_IRQ_INT2; i <= PCIMT_IRQ_ETHERNET; i++) { irq_desc[i].status = IRQ_DISABLED; irq_desc[i].action = 0; irq_desc[i].depth = 1; irq_desc[i].handler = &pciasic_irq_type; } change_c0_status(ST0_IM, IE_IRQ1|IE_IRQ2|IE_IRQ3|IE_IRQ4); }
void __init mach_init_irq(void) { /* init all controller * 0-15 ------> i8259 interrupt * 16-23 ------> mips cpu interrupt * 32-63 ------> bonito irq */ /* Sets the first-level interrupt dispatcher. */ mips_cpu_irq_init(); init_i8259_irqs(); bonito_irq_init(); /* setup north bridge irq (bonito) */ setup_irq(LOONGSON_NORTH_BRIDGE_IRQ, &ip6_irqaction); /* setup source bridge irq (i8259) */ setup_irq(LOONGSON_SOUTH_BRIDGE_IRQ, &cascade_irqaction); }
void __init arch_init_irq(void) { init_i8259_irqs(); if (!cpu_has_veic) mips_cpu_irq_init (MIPSCPU_INT_BASE); switch(mips_revision_corid) { case MIPS_REVISION_CORID_CORE_MSC: case MIPS_REVISION_CORID_CORE_FPGA2: case MIPS_REVISION_CORID_CORE_FPGA3: case MIPS_REVISION_CORID_CORE_24K: case MIPS_REVISION_CORID_CORE_EMUL_MSC: if (cpu_has_veic) init_msc_irqs (MSC01E_INT_BASE, msc_eicirqmap, msc_nr_eicirqs); else init_msc_irqs (MSC01C_INT_BASE, msc_irqmap, msc_nr_irqs); } if (cpu_has_veic) { set_vi_handler (MSC01E_INT_I8259A, malta_hw0_irqdispatch); set_vi_handler (MSC01E_INT_COREHI, corehi_irqdispatch); setup_irq (MSC01E_INT_BASE+MSC01E_INT_I8259A, &i8259irq); setup_irq (MSC01E_INT_BASE+MSC01E_INT_COREHI, &corehi_irqaction); } else if (cpu_has_vint) { set_vi_handler (MIPSCPU_INT_I8259A, malta_hw0_irqdispatch); set_vi_handler (MIPSCPU_INT_COREHI, corehi_irqdispatch); #ifdef CONFIG_MIPS_MT_SMTC setup_irq_smtc (MIPSCPU_INT_BASE+MIPSCPU_INT_I8259A, &i8259irq, (0x100 << MIPSCPU_INT_I8259A)); setup_irq_smtc (MIPSCPU_INT_BASE+MIPSCPU_INT_COREHI, &corehi_irqaction, (0x100 << MIPSCPU_INT_COREHI)); #else /* Not SMTC */ setup_irq (MIPSCPU_INT_BASE+MIPSCPU_INT_I8259A, &i8259irq); setup_irq (MIPSCPU_INT_BASE+MIPSCPU_INT_COREHI, &corehi_irqaction); #endif /* CONFIG_MIPS_MT_SMTC */ } else { setup_irq (MIPSCPU_INT_BASE+MIPSCPU_INT_I8259A, &i8259irq); setup_irq (MIPSCPU_INT_BASE+MIPSCPU_INT_COREHI, &corehi_irqaction); } }
void __init arch_init_irq(void) { init_i8259_irqs(); if (!cpu_has_veic) mips_cpu_irq_init(); if (mips_cm_present()) { write_gcr_gic_base(GIC_BASE_ADDR | CM_GCR_GIC_BASE_GICEN_MSK); gic_present = 1; } else { if (mips_revision_sconid == MIPS_REVISION_SCON_ROCIT) { _msc01_biu_base = (unsigned long) ioremap_nocache(MSC01_BIU_REG_BASE, MSC01_BIU_ADDRSPACE_SZ); gic_present = (REG(_msc01_biu_base, MSC01_SC_CFG) & MSC01_SC_CFG_GICPRES_MSK) >> MSC01_SC_CFG_GICPRES_SHF; } }
/* * On systems with i8259-style interrupt controllers we assume for * driver compatibility reasons interrupts 0 - 15 to be the i8259 * interrupts even if the hardware uses a different interrupt numbering. */ void __init arch_init_irq(void) { /* * this is a hack to get back the still needed wired mapping * killed by init_mm() */ /* Map 0xe0000000 -> 0x0:800005C0, 0xe0010000 -> 0x1:30000580 */ add_wired_entry(0x02000017, 0x03c00017, 0xe0000000, PM_64K); /* Map 0xe2000000 -> 0x0:900005C0, 0xe3010000 -> 0x0:910005C0 */ add_wired_entry(0x02400017, 0x02440017, 0xe2000000, PM_16M); /* Map 0xe4000000 -> 0x0:600005C0, 0xe4100000 -> 400005C0 */ add_wired_entry(0x01800017, 0x01000017, 0xe4000000, PM_4M); init_i8259_irqs(); /* Integrated i8259 */ mips_cpu_irq_init(); init_r4030_ints(); change_c0_status(ST0_IM, IE_IRQ2 | IE_IRQ1); }
/* * On systems with i8259-style interrupt controllers we assume for * driver compatibility reasons interrupts 0 - 15 to be the i8259 * interrupts even if the hardware uses a different interrupt numbering. */ void __init init_IRQ (void) { int i; set_except_vector(0, jazz_handle_int); init_generic_irq(); init_i8259_irqs(); /* Integrated i8259 */ #if 0 init_jazz_irq(); /* Actually we've got more interrupts to handle ... */ for (i = PCIMT_IRQ_INT2; i <= PCIMT_IRQ_ETHERNET; i++) { irq_desc[i].status = IRQ_DISABLED; irq_desc[i].action = 0; irq_desc[i].depth = 1; irq_desc[i].handler = &pciasic_irq_type; } #endif }
void __init arch_init_irq(void) { init_i8259_irqs(); if (!cpu_has_veic) mips_cpu_irq_init(); if (gcmp_present) { GCMPGCB(GICBA) = GIC_BASE_ADDR | GCMP_GCB_GICBA_EN_MSK; gic_present = 1; } else { if (mips_revision_sconid == MIPS_REVISION_SCON_ROCIT) { _msc01_biu_base = (unsigned long) ioremap_nocache(MSC01_BIU_REG_BASE, MSC01_BIU_ADDRSPACE_SZ); gic_present = (REG(_msc01_biu_base, MSC01_SC_CFG) & MSC01_SC_CFG_GICPRES_MSK) >> MSC01_SC_CFG_GICPRES_SHF; } }
void __init mach_init_irq(void) { /* init all controller * 0-15 ------> i8259 interrupt * 16-23 ------> mips cpu interrupt * 32-63 ------> bonito irq */ /* most bonito irq should be level triggered */ LOONGSON_INTEDGE = LOONGSON_ICU_SYSTEMERR | LOONGSON_ICU_MASTERERR | LOONGSON_ICU_RETRYERR | LOONGSON_ICU_MBOXES; /* Sets the first-level interrupt dispatcher. */ mips_cpu_irq_init(); init_i8259_irqs(); bonito_irq_init(); /* bonito irq at IP2 */ setup_irq(MIPS_CPU_IRQ_BASE + 2, &cascade_irqaction); /* 8259 irq at IP5 */ setup_irq(MIPS_CPU_IRQ_BASE + 5, &cascade_irqaction); }
void __init init_irq_2f(void) { unsigned int mask; /* init all controller * 0-15 ------> i8259 interrupt * 16-23 ------> mips cpu interrupt * 32-63 ------> bonito irq */ /* setup cs5536 as high level trigger */ LOONGSON_INTPOL = LOONGSON_INT_BIT_INT0 | LOONGSON_INT_BIT_INT1; LOONGSON_INTEDGE &= ~(LOONGSON_INT_BIT_INT0 | LOONGSON_INT_BIT_INT1); /* Sets the first-level interrupt dispatcher. */ mips_cpu_irq_init(); init_i8259_irqs(); bonito_irq_init(); /* setup north bridge irq (bonito) */ setup_irq(LOONGSON_NORTH_BRIDGE_IRQ, &ip6_irqaction); /* setup source bridge irq (i8259) */ setup_irq(LOONGSON_SOUTH_BRIDGE_IRQ, &cascade_irqaction); }
void __init arch_init_irq(void) { set_except_vector(0, mipsIRQ); init_i8259_irqs(); if (!cpu_has_veic) mips_cpu_irq_init (MIPSCPU_INT_BASE); switch(mips_revision_corid) { case MIPS_REVISION_CORID_CORE_MSC: case MIPS_REVISION_CORID_CORE_FPGA2: case MIPS_REVISION_CORID_CORE_FPGA3: case MIPS_REVISION_CORID_CORE_EMUL_MSC: if (cpu_has_veic) init_msc_irqs (MSC01E_INT_BASE, msc_eicirqmap, msc_nr_eicirqs); else init_msc_irqs (MSC01C_INT_BASE, msc_irqmap, msc_nr_irqs); } if (cpu_has_veic) { set_vi_handler (MSC01E_INT_I8259A, malta_hw0_irqdispatch); set_vi_handler (MSC01E_INT_COREHI, corehi_irqdispatch); setup_irq (MSC01E_INT_BASE+MSC01E_INT_I8259A, &i8259irq); setup_irq (MSC01E_INT_BASE+MSC01E_INT_COREHI, &corehi_irqaction); } else if (cpu_has_vint) { set_vi_handler (MIPSCPU_INT_I8259A, malta_hw0_irqdispatch); set_vi_handler (MIPSCPU_INT_COREHI, corehi_irqdispatch); setup_irq (MIPSCPU_INT_BASE+MIPSCPU_INT_I8259A, &i8259irq); setup_irq (MIPSCPU_INT_BASE+MIPSCPU_INT_COREHI, &corehi_irqaction); } else { set_except_vector(0, mipsIRQ); setup_irq (MIPSCPU_INT_BASE+MIPSCPU_INT_I8259A, &i8259irq); setup_irq (MIPSCPU_INT_BASE+MIPSCPU_INT_COREHI, &corehi_irqaction); } }
void __init arch_init_irq(void) { /* setup cascade interrupts */ setup_irq(NILE4_IRQ_BASE + NILE4_INT_INTE, &irq_cascade); setup_irq(CPU_IRQ_BASE + CPU_NILE4_CASCADE, &irq_cascade); set_except_vector(0, ddbIRQ); nile4_irq_setup(NILE4_IRQ_BASE); m1543_irq_setup(); init_i8259_irqs(); printk("CPU_IRQ_BASE: %d\n",CPU_IRQ_BASE); mips_cpu_irq_init(CPU_IRQ_BASE); printk("enabling 8259 cascade\n"); ddb5074_led_hex(0); /* Enable the interrupt cascade */ nile4_enable_irq(NILE4_IRQ_BASE+IRQ_I8259_CASCADE); }
void __init arch_init_irq(void) { int gic_present, gcmp_present; init_i8259_irqs(); if (!cpu_has_veic) mips_cpu_irq_init(); gcmp_present = gcmp_probe(GCMP_BASE_ADDR, GCMP_ADDRSPACE_SZ); if (gcmp_present) { GCMPGCB(GICBA) = GIC_BASE_ADDR | GCMP_GCB_GICBA_EN_MSK; gic_present = 1; } else { _msc01_biu_base = (unsigned long) ioremap_nocache(MSC01_BIU_REG_BASE, MSC01_BIU_ADDRSPACE_SZ); gic_present = (REG(_msc01_biu_base, MSC01_SC_CFG) & MSC01_SC_CFG_GICPRES_MSK) >> MSC01_SC_CFG_GICPRES_SHF; } if (gic_present) printk(KERN_DEBUG "GIC present\n"); switch (mips_revision_sconid) { case MIPS_REVISION_SCON_SOCIT: case MIPS_REVISION_SCON_ROCIT: if (cpu_has_veic) init_msc_irqs(MIPS_MSC01_IC_REG_BASE, MSC01E_INT_BASE, msc_eicirqmap, msc_nr_eicirqs); else init_msc_irqs(MIPS_MSC01_IC_REG_BASE, MSC01C_INT_BASE, msc_irqmap, msc_nr_irqs); break; case MIPS_REVISION_SCON_SOCITSC: case MIPS_REVISION_SCON_SOCITSCP: if (cpu_has_veic) init_msc_irqs(MIPS_SOCITSC_IC_REG_BASE, MSC01E_INT_BASE, msc_eicirqmap, msc_nr_eicirqs); else init_msc_irqs(MIPS_SOCITSC_IC_REG_BASE, MSC01C_INT_BASE, msc_irqmap, msc_nr_irqs); } if (cpu_has_veic) { set_vi_handler(MSC01E_INT_I8259A, malta_hw0_irqdispatch); set_vi_handler(MSC01E_INT_COREHI, corehi_irqdispatch); setup_irq(MSC01E_INT_BASE+MSC01E_INT_I8259A, &i8259irq); setup_irq(MSC01E_INT_BASE+MSC01E_INT_COREHI, &corehi_irqaction); } else if (cpu_has_vint) { set_vi_handler(MIPSCPU_INT_I8259A, malta_hw0_irqdispatch); set_vi_handler(MIPSCPU_INT_COREHI, corehi_irqdispatch); #ifdef CONFIG_MIPS_MT_SMTC setup_irq_smtc(MIPS_CPU_IRQ_BASE+MIPSCPU_INT_I8259A, &i8259irq, (0x100 << MIPSCPU_INT_I8259A)); setup_irq_smtc(MIPS_CPU_IRQ_BASE+MIPSCPU_INT_COREHI, &corehi_irqaction, (0x100 << MIPSCPU_INT_COREHI)); /* * Temporary hack to ensure that the subsidiary device * interrupts coing in via the i8259A, but associated * with low IRQ numbers, will restore the Status.IM * value associated with the i8259A. */ { int i; for (i = 0; i < 16; i++) irq_hwmask[i] = (0x100 << MIPSCPU_INT_I8259A); } #else /* Not SMTC */ setup_irq(MIPS_CPU_IRQ_BASE+MIPSCPU_INT_I8259A, &i8259irq); setup_irq(MIPS_CPU_IRQ_BASE+MIPSCPU_INT_COREHI, &corehi_irqaction); #endif /* CONFIG_MIPS_MT_SMTC */ } else { setup_irq(MIPS_CPU_IRQ_BASE+MIPSCPU_INT_I8259A, &i8259irq); setup_irq(MIPS_CPU_IRQ_BASE+MIPSCPU_INT_COREHI, &corehi_irqaction); } #if defined(CONFIG_MIPS_MT_SMP) if (gic_present) { /* FIXME */ int i; struct { unsigned int resched; unsigned int call; } ipiirq[] = { { .resched = GIC_IPI_EXT_INTR_RESCHED_VPE0, .call = GIC_IPI_EXT_INTR_CALLFNC_VPE0}, { .resched = GIC_IPI_EXT_INTR_RESCHED_VPE1, .call = GIC_IPI_EXT_INTR_CALLFNC_VPE1 }, { .resched = GIC_IPI_EXT_INTR_RESCHED_VPE2,