static irqreturn_t vfio_intx_handler(int irq, void *dev_id)
{
struct vfio_pci_device *vdev = dev_id;
unsigned long flags;
int ret = IRQ_NONE;
spin_lock_irqsave(&vdev->irqlock, flags);
if (!vdev->pci_2_3) {
disable_irq_nosync(vdev->pdev->irq);
vdev->ctx[0].masked = true;
ret = IRQ_HANDLED;
} else if (!vdev->ctx[0].masked && /* may be shared */
pci_check_and_mask_intx(vdev->pdev)) {
vdev->ctx[0].masked = true;
ret = IRQ_HANDLED;
}
spin_unlock_irqrestore(&vdev->irqlock, flags);
if (ret == IRQ_HANDLED)
vfio_send_intx_eventfd(vdev, NULL);
return ret;
}
/**
* This is interrupt handler which will check if the interrupt is for the right device.
* If yes, disable it here and will be enable later.
*/
static irqreturn_t
igbuio_pci_irqhandler(int irq, struct uio_info *info)
{
struct rte_uio_pci_dev *udev = info->priv;
/* Legacy mode need to mask in hardware */
if (udev->mode == RTE_INTR_MODE_LEGACY &&
!pci_check_and_mask_intx(udev->pdev))
return IRQ_NONE;
/* Message signal mode, no share IRQ and automasked */
return IRQ_HANDLED;
}
/**
* This is interrupt handler which will check if the interrupt is for the right device.
* If yes, disable it here and will be enable later.
*/
static irqreturn_t
igbuio_pci_irqhandler(int irq, void *dev_id)
{
struct rte_uio_pci_dev *udev = (struct rte_uio_pci_dev *)dev_id;
struct uio_info *info = &udev->info;
/* Legacy mode need to mask in hardware */
if (udev->mode == RTE_INTR_MODE_LEGACY &&
!pci_check_and_mask_intx(udev->pdev))
return IRQ_NONE;
uio_event_notify(info);
/* Message signal mode, no share IRQ and automasked */
return IRQ_HANDLED;
}
irqreturn_t irq_handler(int irq, void *dev_id)
{
u16 value;
uint8_t *csr;
#ifndef MSI_TEST
if( !pci_check_and_mask_intx(pdev) )
{ return IRQ_NONE; }
#endif
counter++;
csr = (uint8_t*)&value;
pci_read_config_word(pdev, PCI_COMMAND, &value);
csr[1] = 1;
pci_write_config_word(pdev, PCI_COMMAND, value);
return IRQ_HANDLED;
}