static void fdt_create(VersalVirt *s)
{
MachineClass *mc = MACHINE_GET_CLASS(s);
int i;
s->fdt = create_device_tree(&s->fdt_size);
if (!s->fdt) {
error_report("create_device_tree() failed");
exit(1);
}
/* Allocate all phandles. */
s->phandle.gic = qemu_fdt_alloc_phandle(s->fdt);
for (i = 0; i < ARRAY_SIZE(s->phandle.ethernet_phy); i++) {
s->phandle.ethernet_phy[i] = qemu_fdt_alloc_phandle(s->fdt);
}
s->phandle.clk_25Mhz = qemu_fdt_alloc_phandle(s->fdt);
s->phandle.clk_125Mhz = qemu_fdt_alloc_phandle(s->fdt);
/* Create /chosen node for load_dtb. */
qemu_fdt_add_subnode(s->fdt, "/chosen");
/* Header */
qemu_fdt_setprop_cell(s->fdt, "/", "interrupt-parent", s->phandle.gic);
qemu_fdt_setprop_cell(s->fdt, "/", "#size-cells", 0x2);
qemu_fdt_setprop_cell(s->fdt, "/", "#address-cells", 0x2);
qemu_fdt_setprop_string(s->fdt, "/", "model", mc->desc);
qemu_fdt_setprop_string(s->fdt, "/", "compatible", "xlnx-versal-virt");
}
static void create_dt_mpc8xxx_gpio(void *fdt, const char *soc, const char *mpic)
{
hwaddr mmio0 = MPC8XXX_GPIO_OFFSET;
int irq0 = MPC8XXX_GPIO_IRQ;
gchar *node = g_strdup_printf("%s/gpio@%"PRIx64, soc, mmio0);
gchar *poweroff = g_strdup_printf("%s/power-off", soc);
int gpio_ph;
qemu_fdt_add_subnode(fdt, node);
qemu_fdt_setprop_string(fdt, node, "compatible", "fsl,qoriq-gpio");
qemu_fdt_setprop_cells(fdt, node, "reg", mmio0, 0x1000);
qemu_fdt_setprop_cells(fdt, node, "interrupts", irq0, 0x2);
qemu_fdt_setprop_phandle(fdt, node, "interrupt-parent", mpic);
qemu_fdt_setprop_cells(fdt, node, "#gpio-cells", 2);
qemu_fdt_setprop(fdt, node, "gpio-controller", NULL, 0);
gpio_ph = qemu_fdt_alloc_phandle(fdt);
qemu_fdt_setprop_cell(fdt, node, "phandle", gpio_ph);
qemu_fdt_setprop_cell(fdt, node, "linux,phandle", gpio_ph);
/* Power Off Pin */
qemu_fdt_add_subnode(fdt, poweroff);
qemu_fdt_setprop_string(fdt, poweroff, "compatible", "gpio-poweroff");
qemu_fdt_setprop_cells(fdt, poweroff, "gpios", gpio_ph, 0, 0);
g_free(node);
g_free(poweroff);
}
static void fdt_add_gem_nodes(VersalVirt *s)
{
uint64_t addrs[] = { MM_GEM1, MM_GEM0 };
unsigned int irqs[] = { VERSAL_GEM1_IRQ_0, VERSAL_GEM0_IRQ_0 };
const char clocknames[] = "pclk\0hclk\0tx_clk\0rx_clk";
const char compat_gem[] = "cdns,zynqmp-gem\0cdns,gem";
int i;
for (i = 0; i < ARRAY_SIZE(addrs); i++) {
char *name = g_strdup_printf("/ethernet@%" PRIx64, addrs[i]);
qemu_fdt_add_subnode(s->fdt, name);
fdt_add_fixed_link_nodes(s, name, s->phandle.ethernet_phy[i]);
qemu_fdt_setprop_string(s->fdt, name, "phy-mode", "rgmii-id");
qemu_fdt_setprop_cell(s->fdt, name, "phy-handle",
s->phandle.ethernet_phy[i]);
qemu_fdt_setprop_cells(s->fdt, name, "clocks",
s->phandle.clk_25Mhz, s->phandle.clk_25Mhz,
s->phandle.clk_25Mhz, s->phandle.clk_25Mhz);
qemu_fdt_setprop(s->fdt, name, "clock-names",
clocknames, sizeof(clocknames));
qemu_fdt_setprop_cells(s->fdt, name, "interrupts",
GIC_FDT_IRQ_TYPE_SPI, irqs[i],
GIC_FDT_IRQ_FLAGS_LEVEL_HI,
GIC_FDT_IRQ_TYPE_SPI, irqs[i],
GIC_FDT_IRQ_FLAGS_LEVEL_HI);
qemu_fdt_setprop_sized_cells(s->fdt, name, "reg",
2, addrs[i], 2, 0x1000);
qemu_fdt_setprop(s->fdt, name, "compatible",
compat_gem, sizeof(compat_gem));
qemu_fdt_setprop_cell(s->fdt, name, "#address-cells", 1);
qemu_fdt_setprop_cell(s->fdt, name, "#size-cells", 0);
g_free(name);
}
}
static void fdt_add_clk_node(VersalVirt *s, const char *name,
unsigned int freq_hz, uint32_t phandle)
{
qemu_fdt_add_subnode(s->fdt, name);
qemu_fdt_setprop_cell(s->fdt, name, "phandle", phandle);
qemu_fdt_setprop_cell(s->fdt, name, "clock-frequency", freq_hz);
qemu_fdt_setprop_cell(s->fdt, name, "#clock-cells", 0x0);
qemu_fdt_setprop_string(s->fdt, name, "compatible", "fixed-clock");
qemu_fdt_setprop(s->fdt, name, "u-boot,dm-pre-reloc", NULL, 0);
}
int spapr_rtas_device_tree_setup(void *fdt, hwaddr rtas_addr,
hwaddr rtas_size)
{
int ret;
int i;
ret = fdt_add_mem_rsv(fdt, rtas_addr, rtas_size);
if (ret < 0) {
fprintf(stderr, "Couldn't add RTAS reserve entry: %s\n",
fdt_strerror(ret));
return ret;
}
ret = qemu_fdt_setprop_cell(fdt, "/rtas", "linux,rtas-base",
rtas_addr);
if (ret < 0) {
fprintf(stderr, "Couldn't add linux,rtas-base property: %s\n",
fdt_strerror(ret));
return ret;
}
ret = qemu_fdt_setprop_cell(fdt, "/rtas", "linux,rtas-entry",
rtas_addr);
if (ret < 0) {
fprintf(stderr, "Couldn't add linux,rtas-entry property: %s\n",
fdt_strerror(ret));
return ret;
}
ret = qemu_fdt_setprop_cell(fdt, "/rtas", "rtas-size",
rtas_size);
if (ret < 0) {
fprintf(stderr, "Couldn't add rtas-size property: %s\n",
fdt_strerror(ret));
return ret;
}
for (i = 0; i < TOKEN_MAX; i++) {
struct rtas_call *call = &rtas_table[i];
if (!call->name) {
continue;
}
ret = qemu_fdt_setprop_cell(fdt, "/rtas", call->name,
i + TOKEN_BASE);
if (ret < 0) {
fprintf(stderr, "Couldn't add rtas token for %s: %s\n",
call->name, fdt_strerror(ret));
return ret;
}
}
return 0;
}
static void fdt_add_fixed_link_nodes(VersalVirt *s, char *gemname,
uint32_t phandle)
{
char *name = g_strdup_printf("%s/fixed-link", gemname);
qemu_fdt_add_subnode(s->fdt, name);
qemu_fdt_setprop_cell(s->fdt, name, "phandle", phandle);
qemu_fdt_setprop(s->fdt, name, "full-duplex", NULL, 0);
qemu_fdt_setprop_cell(s->fdt, name, "speed", 1000);
g_free(name);
}
static int xilinx_load_device_tree(hwaddr addr,
uint32_t ramsize,
hwaddr initrd_base,
hwaddr initrd_size,
const char *kernel_cmdline)
{
char *path;
int fdt_size;
void *fdt = NULL;
int r;
const char *dtb_filename;
dtb_filename = qemu_opt_get(qemu_get_machine_opts(), "dtb");
if (dtb_filename) {
fdt = load_device_tree(dtb_filename, &fdt_size);
if (!fdt) {
error_report("Error while loading device tree file '%s'",
dtb_filename);
}
} else {
/* Try the local "ppc.dtb" override. */
fdt = load_device_tree("ppc.dtb", &fdt_size);
if (!fdt) {
path = qemu_find_file(QEMU_FILE_TYPE_BIOS, BINARY_DEVICE_TREE_FILE);
if (path) {
fdt = load_device_tree(path, &fdt_size);
g_free(path);
}
}
}
if (!fdt) {
return 0;
}
r = qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-start",
initrd_base);
if (r < 0) {
error_report("couldn't set /chosen/linux,initrd-start");
}
r = qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-end",
(initrd_base + initrd_size));
if (r < 0) {
error_report("couldn't set /chosen/linux,initrd-end");
}
r = qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", kernel_cmdline);
if (r < 0)
fprintf(stderr, "couldn't set /chosen/bootargs\n");
cpu_physical_memory_write(addr, fdt, fdt_size);
return fdt_size;
}
int qemu_fdt_setprop_phandle(void *fdt, const char *node_path,
const char *property,
const char *target_node_path)
{
uint32_t phandle = qemu_fdt_get_phandle(fdt, target_node_path);
return qemu_fdt_setprop_cell(fdt, node_path, property, phandle);
}
static void fdt_add_uart_nodes(VersalVirt *s)
{
uint64_t addrs[] = { MM_UART1, MM_UART0 };
unsigned int irqs[] = { VERSAL_UART1_IRQ_0, VERSAL_UART0_IRQ_0 };
const char compat[] = "arm,pl011\0arm,sbsa-uart";
const char clocknames[] = "uartclk\0apb_pclk";
int i;
for (i = 0; i < ARRAY_SIZE(addrs); i++) {
char *name = g_strdup_printf("/uart@%" PRIx64, addrs[i]);
qemu_fdt_add_subnode(s->fdt, name);
qemu_fdt_setprop_cell(s->fdt, name, "current-speed", 115200);
qemu_fdt_setprop_cells(s->fdt, name, "clocks",
s->phandle.clk_125Mhz, s->phandle.clk_125Mhz);
qemu_fdt_setprop(s->fdt, name, "clock-names",
clocknames, sizeof(clocknames));
qemu_fdt_setprop_cells(s->fdt, name, "interrupts",
GIC_FDT_IRQ_TYPE_SPI, irqs[i],
GIC_FDT_IRQ_FLAGS_LEVEL_HI);
qemu_fdt_setprop_sized_cells(s->fdt, name, "reg",
2, addrs[i], 2, 0x1000);
qemu_fdt_setprop(s->fdt, name, "compatible",
compat, sizeof(compat));
qemu_fdt_setprop(s->fdt, name, "u-boot,dm-pre-reloc", NULL, 0);
if (addrs[i] == MM_UART0) {
/* Select UART0. */
qemu_fdt_setprop_string(s->fdt, "/chosen", "stdout-path", name);
}
g_free(name);
}
}
static void fdt_add_gic_nodes(VersalVirt *s)
{
char *nodename;
nodename = g_strdup_printf("/gic@%x", MM_GIC_APU_DIST_MAIN);
qemu_fdt_add_subnode(s->fdt, nodename);
qemu_fdt_setprop_cell(s->fdt, nodename, "phandle", s->phandle.gic);
qemu_fdt_setprop_cells(s->fdt, nodename, "interrupts",
GIC_FDT_IRQ_TYPE_PPI, VERSAL_GIC_MAINT_IRQ,
GIC_FDT_IRQ_FLAGS_LEVEL_HI);
qemu_fdt_setprop(s->fdt, nodename, "interrupt-controller", NULL, 0);
qemu_fdt_setprop_sized_cells(s->fdt, nodename, "reg",
2, MM_GIC_APU_DIST_MAIN,
2, MM_GIC_APU_DIST_MAIN_SIZE,
2, MM_GIC_APU_REDIST_0,
2, MM_GIC_APU_REDIST_0_SIZE);
qemu_fdt_setprop_cell(s->fdt, nodename, "#interrupt-cells", 3);
qemu_fdt_setprop_string(s->fdt, nodename, "compatible", "arm,gic-v3");
g_free(nodename);
}
static void dt_serial_create(void *fdt, unsigned long long offset,
const char *soc, const char *mpic,
const char *alias, int idx, bool defcon)
{
char ser[128];
snprintf(ser, sizeof(ser), "%s/serial@%llx", soc, offset);
qemu_fdt_add_subnode(fdt, ser);
qemu_fdt_setprop_string(fdt, ser, "device_type", "serial");
qemu_fdt_setprop_string(fdt, ser, "compatible", "ns16550");
qemu_fdt_setprop_cells(fdt, ser, "reg", offset, 0x100);
qemu_fdt_setprop_cell(fdt, ser, "cell-index", idx);
qemu_fdt_setprop_cell(fdt, ser, "clock-frequency", 0);
qemu_fdt_setprop_cells(fdt, ser, "interrupts", 42, 2);
qemu_fdt_setprop_phandle(fdt, ser, "interrupt-parent", mpic);
qemu_fdt_setprop_string(fdt, "/aliases", alias, ser);
if (defcon) {
qemu_fdt_setprop_string(fdt, "/chosen", "linux,stdout-path", ser);
}
}
static void fdt_add_cpu_nodes(VersalVirt *s, uint32_t psci_conduit)
{
int i;
qemu_fdt_add_subnode(s->fdt, "/cpus");
qemu_fdt_setprop_cell(s->fdt, "/cpus", "#size-cells", 0x0);
qemu_fdt_setprop_cell(s->fdt, "/cpus", "#address-cells", 1);
for (i = XLNX_VERSAL_NR_ACPUS - 1; i >= 0; i--) {
char *name = g_strdup_printf("/cpus/cpu@%d", i);
ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(i));
qemu_fdt_add_subnode(s->fdt, name);
qemu_fdt_setprop_cell(s->fdt, name, "reg", armcpu->mp_affinity);
if (psci_conduit != QEMU_PSCI_CONDUIT_DISABLED) {
qemu_fdt_setprop_string(s->fdt, name, "enable-method", "psci");
}
qemu_fdt_setprop_string(s->fdt, name, "device_type", "cpu");
qemu_fdt_setprop_string(s->fdt, name, "compatible",
armcpu->dtb_compatible);
g_free(name);
}
}
static int microblaze_load_dtb(hwaddr addr,
uint32_t ramsize,
uint32_t initrd_start,
uint32_t initrd_end,
const char *kernel_cmdline,
const char *dtb_filename)
{
int fdt_size;
void *fdt = NULL;
int r;
if (dtb_filename) {
fdt = load_device_tree(dtb_filename, &fdt_size);
}
if (!fdt) {
return 0;
}
if (kernel_cmdline) {
r = qemu_fdt_setprop_string(fdt, "/chosen", "bootargs",
kernel_cmdline);
if (r < 0) {
fprintf(stderr, "couldn't set /chosen/bootargs\n");
}
}
if (initrd_start) {
qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-start",
initrd_start);
qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-end",
initrd_end);
}
cpu_physical_memory_write(addr, fdt, fdt_size);
return fdt_size;
}
static int ppce500_load_device_tree(QEMUMachineInitArgs *args,
PPCE500Params *params,
hwaddr addr,
hwaddr initrd_base,
hwaddr initrd_size,
bool dry_run)
{
CPUPPCState *env = first_cpu->env_ptr;
int ret = -1;
uint64_t mem_reg_property[] = { 0, cpu_to_be64(args->ram_size) };
int fdt_size;
void *fdt;
uint8_t hypercall[16];
uint32_t clock_freq = 400000000;
uint32_t tb_freq = 400000000;
int i;
char compatible_sb[] = "fsl,mpc8544-immr\0simple-bus";
char soc[128];
char mpic[128];
uint32_t mpic_ph;
uint32_t msi_ph;
char gutil[128];
char pci[128];
char msi[128];
uint32_t *pci_map = NULL;
int len;
uint32_t pci_ranges[14] =
{
0x2000000, 0x0, 0xc0000000,
0x0, 0xc0000000,
0x0, 0x20000000,
0x1000000, 0x0, 0x0,
0x0, 0xe1000000,
0x0, 0x10000,
};
QemuOpts *machine_opts = qemu_get_machine_opts();
const char *dtb_file = qemu_opt_get(machine_opts, "dtb");
const char *toplevel_compat = qemu_opt_get(machine_opts, "dt_compatible");
if (dtb_file) {
char *filename;
filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, dtb_file);
if (!filename) {
goto out;
}
fdt = load_device_tree(filename, &fdt_size);
if (!fdt) {
goto out;
}
goto done;
}
fdt = create_device_tree(&fdt_size);
if (fdt == NULL) {
goto out;
}
/* Manipulate device tree in memory. */
qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 2);
qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 2);
qemu_fdt_add_subnode(fdt, "/memory");
qemu_fdt_setprop_string(fdt, "/memory", "device_type", "memory");
qemu_fdt_setprop(fdt, "/memory", "reg", mem_reg_property,
sizeof(mem_reg_property));
qemu_fdt_add_subnode(fdt, "/chosen");
if (initrd_size) {
ret = qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-start",
initrd_base);
if (ret < 0) {
fprintf(stderr, "couldn't set /chosen/linux,initrd-start\n");
}
ret = qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-end",
(initrd_base + initrd_size));
if (ret < 0) {
fprintf(stderr, "couldn't set /chosen/linux,initrd-end\n");
}
}
ret = qemu_fdt_setprop_string(fdt, "/chosen", "bootargs",
args->kernel_cmdline);
if (ret < 0)
fprintf(stderr, "couldn't set /chosen/bootargs\n");
if (kvm_enabled()) {
/* Read out host's frequencies */
clock_freq = kvmppc_get_clockfreq();
tb_freq = kvmppc_get_tbfreq();
/* indicate KVM hypercall interface */
qemu_fdt_add_subnode(fdt, "/hypervisor");
qemu_fdt_setprop_string(fdt, "/hypervisor", "compatible",
"linux,kvm");
kvmppc_get_hypercall(env, hypercall, sizeof(hypercall));
qemu_fdt_setprop(fdt, "/hypervisor", "hcall-instructions",
hypercall, sizeof(hypercall));
/* if KVM supports the idle hcall, set property indicating this */
if (kvmppc_get_hasidle(env)) {
qemu_fdt_setprop(fdt, "/hypervisor", "has-idle", NULL, 0);
}
}
/* Create CPU nodes */
qemu_fdt_add_subnode(fdt, "/cpus");
qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 1);
qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0);
/* We need to generate the cpu nodes in reverse order, so Linux can pick
the first node as boot node and be happy */
for (i = smp_cpus - 1; i >= 0; i--) {
CPUState *cpu;
PowerPCCPU *pcpu;
char cpu_name[128];
uint64_t cpu_release_addr = MPC8544_SPIN_BASE + (i * 0x20);
cpu = qemu_get_cpu(i);
if (cpu == NULL) {
continue;
}
env = cpu->env_ptr;
pcpu = POWERPC_CPU(cpu);
snprintf(cpu_name, sizeof(cpu_name), "/cpus/PowerPC,8544@%x",
ppc_get_vcpu_dt_id(pcpu));
qemu_fdt_add_subnode(fdt, cpu_name);
qemu_fdt_setprop_cell(fdt, cpu_name, "clock-frequency", clock_freq);
qemu_fdt_setprop_cell(fdt, cpu_name, "timebase-frequency", tb_freq);
qemu_fdt_setprop_string(fdt, cpu_name, "device_type", "cpu");
qemu_fdt_setprop_cell(fdt, cpu_name, "reg",
ppc_get_vcpu_dt_id(pcpu));
qemu_fdt_setprop_cell(fdt, cpu_name, "d-cache-line-size",
env->dcache_line_size);
qemu_fdt_setprop_cell(fdt, cpu_name, "i-cache-line-size",
env->icache_line_size);
qemu_fdt_setprop_cell(fdt, cpu_name, "d-cache-size", 0x8000);
qemu_fdt_setprop_cell(fdt, cpu_name, "i-cache-size", 0x8000);
qemu_fdt_setprop_cell(fdt, cpu_name, "bus-frequency", 0);
if (cpu->cpu_index) {
qemu_fdt_setprop_string(fdt, cpu_name, "status", "disabled");
qemu_fdt_setprop_string(fdt, cpu_name, "enable-method",
"spin-table");
qemu_fdt_setprop_u64(fdt, cpu_name, "cpu-release-addr",
cpu_release_addr);
} else {
qemu_fdt_setprop_string(fdt, cpu_name, "status", "okay");
}
}
qemu_fdt_add_subnode(fdt, "/aliases");
/* XXX These should go into their respective devices' code */
snprintf(soc, sizeof(soc), "/soc@%llx", MPC8544_CCSRBAR_BASE);
qemu_fdt_add_subnode(fdt, soc);
qemu_fdt_setprop_string(fdt, soc, "device_type", "soc");
qemu_fdt_setprop(fdt, soc, "compatible", compatible_sb,
sizeof(compatible_sb));
qemu_fdt_setprop_cell(fdt, soc, "#address-cells", 1);
qemu_fdt_setprop_cell(fdt, soc, "#size-cells", 1);
qemu_fdt_setprop_cells(fdt, soc, "ranges", 0x0,
MPC8544_CCSRBAR_BASE >> 32, MPC8544_CCSRBAR_BASE,
MPC8544_CCSRBAR_SIZE);
/* XXX should contain a reasonable value */
qemu_fdt_setprop_cell(fdt, soc, "bus-frequency", 0);
snprintf(mpic, sizeof(mpic), "%s/pic@%llx", soc, MPC8544_MPIC_REGS_OFFSET);
qemu_fdt_add_subnode(fdt, mpic);
qemu_fdt_setprop_string(fdt, mpic, "device_type", "open-pic");
qemu_fdt_setprop_string(fdt, mpic, "compatible", "fsl,mpic");
qemu_fdt_setprop_cells(fdt, mpic, "reg", MPC8544_MPIC_REGS_OFFSET,
0x40000);
qemu_fdt_setprop_cell(fdt, mpic, "#address-cells", 0);
qemu_fdt_setprop_cell(fdt, mpic, "#interrupt-cells", 2);
mpic_ph = qemu_fdt_alloc_phandle(fdt);
qemu_fdt_setprop_cell(fdt, mpic, "phandle", mpic_ph);
qemu_fdt_setprop_cell(fdt, mpic, "linux,phandle", mpic_ph);
qemu_fdt_setprop(fdt, mpic, "interrupt-controller", NULL, 0);
/*
* We have to generate ser1 first, because Linux takes the first
* device it finds in the dt as serial output device. And we generate
* devices in reverse order to the dt.
*/
dt_serial_create(fdt, MPC8544_SERIAL1_REGS_OFFSET,
soc, mpic, "serial1", 1, false);
dt_serial_create(fdt, MPC8544_SERIAL0_REGS_OFFSET,
soc, mpic, "serial0", 0, true);
snprintf(gutil, sizeof(gutil), "%s/global-utilities@%llx", soc,
MPC8544_UTIL_OFFSET);
qemu_fdt_add_subnode(fdt, gutil);
qemu_fdt_setprop_string(fdt, gutil, "compatible", "fsl,mpc8544-guts");
qemu_fdt_setprop_cells(fdt, gutil, "reg", MPC8544_UTIL_OFFSET, 0x1000);
qemu_fdt_setprop(fdt, gutil, "fsl,has-rstcr", NULL, 0);
snprintf(msi, sizeof(msi), "/%s/msi@%llx", soc, MPC8544_MSI_REGS_OFFSET);
qemu_fdt_add_subnode(fdt, msi);
qemu_fdt_setprop_string(fdt, msi, "compatible", "fsl,mpic-msi");
qemu_fdt_setprop_cells(fdt, msi, "reg", MPC8544_MSI_REGS_OFFSET, 0x200);
msi_ph = qemu_fdt_alloc_phandle(fdt);
qemu_fdt_setprop_cells(fdt, msi, "msi-available-ranges", 0x0, 0x100);
qemu_fdt_setprop_phandle(fdt, msi, "interrupt-parent", mpic);
qemu_fdt_setprop_cells(fdt, msi, "interrupts",
0xe0, 0x0,
0xe1, 0x0,
0xe2, 0x0,
0xe3, 0x0,
0xe4, 0x0,
0xe5, 0x0,
0xe6, 0x0,
0xe7, 0x0);
qemu_fdt_setprop_cell(fdt, msi, "phandle", msi_ph);
qemu_fdt_setprop_cell(fdt, msi, "linux,phandle", msi_ph);
snprintf(pci, sizeof(pci), "/pci@%llx", MPC8544_PCI_REGS_BASE);
qemu_fdt_add_subnode(fdt, pci);
qemu_fdt_setprop_cell(fdt, pci, "cell-index", 0);
qemu_fdt_setprop_string(fdt, pci, "compatible", "fsl,mpc8540-pci");
qemu_fdt_setprop_string(fdt, pci, "device_type", "pci");
qemu_fdt_setprop_cells(fdt, pci, "interrupt-map-mask", 0xf800, 0x0,
0x0, 0x7);
pci_map = pci_map_create(fdt, qemu_fdt_get_phandle(fdt, mpic),
params->pci_first_slot, params->pci_nr_slots,
&len);
qemu_fdt_setprop(fdt, pci, "interrupt-map", pci_map, len);
qemu_fdt_setprop_phandle(fdt, pci, "interrupt-parent", mpic);
qemu_fdt_setprop_cells(fdt, pci, "interrupts", 24, 2);
qemu_fdt_setprop_cells(fdt, pci, "bus-range", 0, 255);
for (i = 0; i < 14; i++) {
pci_ranges[i] = cpu_to_be32(pci_ranges[i]);
}
qemu_fdt_setprop_cell(fdt, pci, "fsl,msi", msi_ph);
qemu_fdt_setprop(fdt, pci, "ranges", pci_ranges, sizeof(pci_ranges));
qemu_fdt_setprop_cells(fdt, pci, "reg", MPC8544_PCI_REGS_BASE >> 32,
MPC8544_PCI_REGS_BASE, 0, 0x1000);
qemu_fdt_setprop_cell(fdt, pci, "clock-frequency", 66666666);
qemu_fdt_setprop_cell(fdt, pci, "#interrupt-cells", 1);
qemu_fdt_setprop_cell(fdt, pci, "#size-cells", 2);
qemu_fdt_setprop_cell(fdt, pci, "#address-cells", 3);
qemu_fdt_setprop_string(fdt, "/aliases", "pci0", pci);
params->fixup_devtree(params, fdt);
if (toplevel_compat) {
qemu_fdt_setprop(fdt, "/", "compatible", toplevel_compat,
strlen(toplevel_compat) + 1);
}
done:
if (!dry_run) {
qemu_fdt_dumpdtb(fdt, fdt_size);
cpu_physical_memory_write(addr, fdt, fdt_size);
}
ret = fdt_size;
out:
g_free(pci_map);
return ret;
}
static int bamboo_load_device_tree(hwaddr addr,
uint32_t ramsize,
hwaddr initrd_base,
hwaddr initrd_size,
const char *kernel_cmdline)
{
int ret = -1;
uint32_t mem_reg_property[] = { 0, 0, cpu_to_be32(ramsize) };
char *filename;
int fdt_size;
void *fdt;
uint32_t tb_freq = 400000000;
uint32_t clock_freq = 400000000;
filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, BINARY_DEVICE_TREE_FILE);
if (!filename) {
goto out;
}
fdt = load_device_tree(filename, &fdt_size);
g_free(filename);
if (fdt == NULL) {
goto out;
}
/* Manipulate device tree in memory. */
ret = qemu_fdt_setprop(fdt, "/memory", "reg", mem_reg_property,
sizeof(mem_reg_property));
if (ret < 0)
fprintf(stderr, "couldn't set /memory/reg\n");
ret = qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-start",
initrd_base);
if (ret < 0)
fprintf(stderr, "couldn't set /chosen/linux,initrd-start\n");
ret = qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-end",
(initrd_base + initrd_size));
if (ret < 0)
fprintf(stderr, "couldn't set /chosen/linux,initrd-end\n");
ret = qemu_fdt_setprop_string(fdt, "/chosen", "bootargs",
kernel_cmdline);
if (ret < 0)
fprintf(stderr, "couldn't set /chosen/bootargs\n");
/* Copy data from the host device tree into the guest. Since the guest can
* directly access the timebase without host involvement, we must expose
* the correct frequencies. */
if (kvm_enabled()) {
tb_freq = kvmppc_get_tbfreq();
clock_freq = kvmppc_get_clockfreq();
}
qemu_fdt_setprop_cell(fdt, "/cpus/cpu@0", "clock-frequency",
clock_freq);
qemu_fdt_setprop_cell(fdt, "/cpus/cpu@0", "timebase-frequency",
tb_freq);
rom_add_blob_fixed(BINARY_DEVICE_TREE_FILE, fdt, fdt_size, addr);
g_free(fdt);
return 0;
out:
return ret;
}
static void
microblaze_generic_fdt_init(MachineState *machine)
{
CPUState *cpu;
ram_addr_t ram_kernel_base = 0, ram_kernel_size = 0;
void *fdt = NULL;
const char *dtb_arg, *hw_dtb_arg;
QemuOpts *machine_opts;
int fdt_size;
/* for memory node */
char node_path[DT_PATH_LENGTH];
FDTMachineInfo *fdti;
MemoryRegion *main_mem;
/* For DMA node */
char dma_path[DT_PATH_LENGTH] = { 0 };
uint32_t memory_phandle;
/* For Ethernet nodes */
char **eth_paths;
char *phy_path;
char *mdio_path;
uint32_t n_eth;
uint32_t prop_val;
machine_opts = qemu_opts_find(qemu_find_opts("machine"), 0);
if (!machine_opts) {
goto no_dtb_arg;
}
dtb_arg = qemu_opt_get(machine_opts, "dtb");
hw_dtb_arg = qemu_opt_get(machine_opts, "hw-dtb");
if (!dtb_arg && !hw_dtb_arg) {
goto no_dtb_arg;
}
/* If the user only provided a -dtb, use it as the hw description. */
if (!hw_dtb_arg) {
hw_dtb_arg = dtb_arg;
}
fdt = load_device_tree(hw_dtb_arg, &fdt_size);
if (!fdt) {
hw_error("Error: Unable to load Device Tree %s\n", hw_dtb_arg);
return;
}
if (IS_PETALINUX_MACHINE) {
/* Mark the simple-bus as incompatible as it breaks the Microblaze
* PetaLinux boot
*/
add_to_compat_table(NULL, "compatible:simple-bus", NULL);
}
/* find memory node or add new one if needed */
while (qemu_fdt_get_node_by_name(fdt, node_path, "memory")) {
qemu_fdt_add_subnode(fdt, "/memory@0");
qemu_fdt_setprop_cells(fdt, "/memory@0", "reg", 0, machine->ram_size);
}
if (!qemu_fdt_getprop(fdt, "/memory", "compatible", NULL, 0, NULL)) {
qemu_fdt_setprop_string(fdt, "/memory", "compatible",
"qemu:memory-region");
qemu_fdt_setprop_cells(fdt, "/memory", "qemu,ram", 1);
}
if (IS_PETALINUX_MACHINE) {
/* If using a *-plnx machine, the AXI DMA memory links are not included
* in the DTB by default. To avoid seg faults, add the links in here if
* they have not already been added by the user
*/
qemu_fdt_get_node_by_name(fdt, dma_path, "dma");
if (strcmp(dma_path, "") != 0) {
memory_phandle = qemu_fdt_check_phandle(fdt, node_path);
if (!memory_phandle) {
memory_phandle = qemu_fdt_alloc_phandle(fdt);
qemu_fdt_setprop_cells(fdt, "/memory", "linux,phandle",
memory_phandle);
qemu_fdt_setprop_cells(fdt, "/memory", "phandle",
memory_phandle);
}
if (!qemu_fdt_getprop(fdt, dma_path, "sg", NULL, 0, NULL)) {
qemu_fdt_setprop_phandle(fdt, dma_path, "sg", node_path);
}
if (!qemu_fdt_getprop(fdt, dma_path, "s2mm", NULL, 0, NULL)) {
qemu_fdt_setprop_phandle(fdt, dma_path, "s2mm", node_path);
}
if (!qemu_fdt_getprop(fdt, dma_path, "mm2s", NULL, 0, NULL)) {
qemu_fdt_setprop_phandle(fdt, dma_path, "mm2s", node_path);
}
}
/* Copy phyaddr value from phy node reg property */
n_eth = qemu_fdt_get_n_nodes_by_name(fdt, ð_paths, "ethernet");
while (n_eth--) {
mdio_path = qemu_fdt_get_child_by_name(fdt, eth_paths[n_eth],
"mdio");
if (mdio_path) {
phy_path = qemu_fdt_get_child_by_name(fdt, mdio_path,
"phy");
if (phy_path) {
prop_val = qemu_fdt_getprop_cell(fdt, phy_path, "reg", NULL, 0,
NULL, &error_abort);
qemu_fdt_setprop_cell(fdt, eth_paths[n_eth], "xlnx,phyaddr",
prop_val);
g_free(phy_path);
} else {
qemu_log_mask(LOG_GUEST_ERROR, "phy not found in %s",
mdio_path);
}
g_free(mdio_path);
}
g_free(eth_paths[n_eth]);
}
g_free(eth_paths);
}
/* Instantiate peripherals from the FDT. */
fdti = fdt_generic_create_machine(fdt, NULL);
main_mem = MEMORY_REGION(object_resolve_path(node_path, NULL));
ram_kernel_base = object_property_get_int(OBJECT(main_mem), "addr", NULL);
ram_kernel_size = object_property_get_int(OBJECT(main_mem), "size", NULL);
if (!memory_region_is_mapped(main_mem)) {
/* If the memory region is not mapped, map it here.
* It has to be mapped somewhere, so guess that the base address
* is where the kernel starts
*/
memory_region_add_subregion(get_system_memory(), ram_kernel_base,
main_mem);
if (ram_kernel_base && IS_PETALINUX_MACHINE) {
/* If the memory added is at an offset from zero QEMU will error
* when an ISR/exception is triggered. Add a small amount of hack
* RAM to handle this.
*/
MemoryRegion *hack_ram = g_new(MemoryRegion, 1);
memory_region_init_ram(hack_ram, NULL, "hack_ram", 0x1000,
&error_abort);
vmstate_register_ram_global(hack_ram);
memory_region_add_subregion(get_system_memory(), 0, hack_ram);
}
}
fdt_init_destroy_fdti(fdti);
fdt_g = fdt;
microblaze_load_kernel(MICROBLAZE_CPU(first_cpu), ram_kernel_base,
ram_kernel_size, machine->initrd_filename, NULL,
microblaze_generic_fdt_reset, 0, fdt, fdt_size);
/* Register FDT to prop mapper for secondary cores. */
cpu = CPU_NEXT(first_cpu);
while (cpu) {
qemu_register_reset(secondary_cpu_reset, cpu);
cpu = CPU_NEXT(cpu);
}
return;
no_dtb_arg:
if (!QTEST_RUNNING) {
hw_error("DTB must be specified for %s machine model\n", MACHINE_NAME);
}
return;
}
