static void twl4030_phy_power(struct twl4030_usb *twl, int on) { u8 pwr; pwr = twl4030_usb_read(twl, PHY_PWR_CTRL); if (on) { regulator_enable(twl->usb3v1); regulator_enable(twl->usb1v8); /* * Disabling usb3v1 regulator (= writing 0 to VUSB3V1_DEV_GRP * in twl4030) resets the VUSB_DEDICATED2 register. This reset * enables VUSB3V1_SLEEP bit that remaps usb3v1 ACTIVE state to * SLEEP. We work around this by clearing the bit after usv3v1 * is re-activated. This ensures that VUSB3V1 is really active. */ twl_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, 0, VUSB_DEDICATED2); regulator_enable(twl->usb1v5); pwr &= ~PHY_PWR_PHYPWD; WARN_ON(twl4030_usb_write_verify(twl, PHY_PWR_CTRL, pwr) < 0); twl4030_usb_write(twl, PHY_CLK_CTRL, twl4030_usb_read(twl, PHY_CLK_CTRL) | (PHY_CLK_CTRL_CLOCKGATING_EN | PHY_CLK_CTRL_CLK32K_EN)); } else { pwr |= PHY_PWR_PHYPWD; WARN_ON(twl4030_usb_write_verify(twl, PHY_PWR_CTRL, pwr) < 0); regulator_disable(twl->usb1v5); regulator_disable(twl->usb1v8); regulator_disable(twl->usb3v1); } }
static void twl4030_i2c_access(struct twl4030_usb *twl, int on) { unsigned long timeout; int val = twl4030_usb_read(twl, PHY_CLK_CTRL); if (val >= 0) { if (on) { /* enable DPLL to access PHY registers over I2C */ val |= REQ_PHY_DPLL_CLK; WARN_ON(twl4030_usb_write_verify(twl, PHY_CLK_CTRL, (u8)val) < 0); timeout = jiffies + HZ; while (!(twl4030_usb_read(twl, PHY_CLK_CTRL_STS) & PHY_DPLL_CLK) && time_before(jiffies, timeout)) udelay(10); if (!(twl4030_usb_read(twl, PHY_CLK_CTRL_STS) & PHY_DPLL_CLK)) dev_err(twl->dev, "Timeout setting T2 HSUSB " "PHY DPLL clock\n"); } else { /* let ULPI control the DPLL clock */ val &= ~REQ_PHY_DPLL_CLK; WARN_ON(twl4030_usb_write_verify(twl, PHY_CLK_CTRL, (u8)val) < 0); } } }
static void twl4030_phy_power(struct twl4030_usb *twl, int on) { u8 pwr; pwr = twl4030_usb_read(PHY_PWR_CTRL); if (on) { pwr &= ~PHY_PWR_PHYPWD; if (twl4030_usb_write_verify(PHY_PWR_CTRL, pwr) < 0) { printk(KERN_ERR "twl4030_usb: i2c write failed," " line %d\n", __LINE__); return; } twl4030_usb_write(PHY_CLK_CTRL, twl4030_usb_read(PHY_CLK_CTRL) | (PHY_CLK_CTRL_CLOCKGATING_EN | PHY_CLK_CTRL_CLK32K_EN)); } else { pwr |= PHY_PWR_PHYPWD; if (twl4030_usb_write_verify(PHY_PWR_CTRL, pwr) < 0) { printk(KERN_ERR "twl4030_usb: i2c write failed," " line %d\n", __LINE__); } } return; }
static void twl4030_phy_power(struct twl4030_usb *twl, int on) { u8 pwr; pwr = twl4030_usb_read(twl, PHY_PWR_CTRL); if (on) { regulator_enable(twl->usb3v1); regulator_enable(twl->usb1v8); twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, 0, VUSB_DEDICATED2); regulator_enable(twl->usb1v5); pwr &= ~PHY_PWR_PHYPWD; WARN_ON(twl4030_usb_write_verify(twl, PHY_PWR_CTRL, pwr) < 0); twl4030_usb_write(twl, PHY_CLK_CTRL, twl4030_usb_read(twl, PHY_CLK_CTRL) | (PHY_CLK_CTRL_CLOCKGATING_EN | PHY_CLK_CTRL_CLK32K_EN)); } else { pwr |= PHY_PWR_PHYPWD; WARN_ON(twl4030_usb_write_verify(twl, PHY_PWR_CTRL, pwr) < 0); regulator_disable(twl->usb1v5); regulator_disable(twl->usb1v8); regulator_disable(twl->usb3v1); } }
static void twl4030_phy_power(struct twl4030_usb *twl, int on) { u8 pwr; pwr = twl4030_usb_read(twl, PHY_PWR_CTRL); printk(KERN_ERR "twl4030_phy_power + : PHY_PWR_CTRL=%x ====^^==== (twl4030-usb.c)\n", pwr); pwr = twl4030_usb_read(twl, PHY_CLK_CTRL); printk(KERN_ERR "twl4030_phy_power + : PHY_CLK_CTRL=%x ====^^==== (twl4030-usb.c)\n", pwr); pwr = twl4030_usb_read(twl, PHY_CLK_CTRL_STS); printk(KERN_ERR "twl4030_phy_power + : PHY_CLK_CTRL_STS=%x ====^^==== (twl4030-usb.c)\n", pwr); if (on) { #if 0 /* LGE_CHANGE [HEAVEN: [email protected]] on 2009-10-14, for <25.12 USB interrupt fix> */ regulator_enable(twl->usb3v1); regulator_enable(twl->usb1v8); #endif /* * Disabling usb3v1 regulator (= writing 0 to VUSB3V1_DEV_GRP * in twl4030) resets the VUSB_DEDICATED2 register. This reset * enables VUSB3V1_SLEEP bit that remaps usb3v1 ACTIVE state to * SLEEP. We work around this by clearing the bit after usv3v1 * is re-activated. This ensures that VUSB3V1 is really active. */ twl_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, 0, VUSB_DEDICATED2); #if 1 /* LGE_CHANGE [HEAVEN: [email protected]] on 2009-10-14, for <25.12 USB interrupt fix> */ regulator_enable(twl->usb1v8); #endif regulator_enable(twl->usb1v5); pwr &= ~PHY_PWR_PHYPWD; WARN_ON(twl4030_usb_write_verify(twl, PHY_PWR_CTRL, pwr) < 0); twl4030_usb_write(twl, PHY_CLK_CTRL, twl4030_usb_read(twl, PHY_CLK_CTRL) | (PHY_CLK_CTRL_CLOCKGATING_EN | PHY_CLK_CTRL_CLK32K_EN)); } else { msleep(250); // LGE_CHANGE [HUB] jjun.lee for USB unplug detect (TI Girish) pwr |= PHY_PWR_PHYPWD; WARN_ON(twl4030_usb_write_verify(twl, PHY_PWR_CTRL, pwr) < 0); regulator_disable(twl->usb1v5); regulator_disable(twl->usb1v8); #if 1 /* LGE_CHANGE [HEAVEN: [email protected]] on 2009-10-14, for <25.12 USB interrupt fix> */ /* Put VUSB3V1 regulator in sleep mode */ twl_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, 0x08, VUSB_DEDICATED2); #else regulator_disable(twl->usb3v1); #endif } pwr = twl4030_usb_read(twl, PHY_PWR_CTRL); printk(KERN_ERR "twl4030_phy_power - : PHY_PWR_CTRL=%x ====^^==== (twl4030-usb.c)\n", pwr); pwr = twl4030_usb_read(twl, PHY_CLK_CTRL); printk(KERN_ERR "twl4030_phy_power - : PHY_CLK_CTRL=%x ====^^==== (twl4030-usb.c)\n", pwr); pwr = twl4030_usb_read(twl, PHY_CLK_CTRL_STS); printk(KERN_ERR "twl4030_phy_power - : PHY_CLK_CTRL_STS=%x ====^^==== (twl4030-usb.c)\n", pwr); }
static void twl4030_phy_power(struct twl4030_usb *twl, int on) { u8 pwr; pwr = twl4030_usb_read(twl, PHY_PWR_CTRL); if (on) { pwr &= ~PHY_PWR_PHYPWD; WARN_ON(twl4030_usb_write_verify(twl, PHY_PWR_CTRL, pwr) < 0); twl4030_usb_write(twl, PHY_CLK_CTRL, twl4030_usb_read(twl, PHY_CLK_CTRL) | (PHY_CLK_CTRL_CLOCKGATING_EN | PHY_CLK_CTRL_CLK32K_EN)); } else { pwr |= PHY_PWR_PHYPWD; WARN_ON(twl4030_usb_write_verify(twl, PHY_PWR_CTRL, pwr) < 0); } }
static void __twl4030_phy_power(struct twl4030_usb *twl, int on) { u8 pwr = twl4030_usb_read(twl, PHY_PWR_CTRL); if (on) pwr &= ~PHY_PWR_PHYPWD; else pwr |= PHY_PWR_PHYPWD; WARN_ON(twl4030_usb_write_verify(twl, PHY_PWR_CTRL, pwr) < 0); }
static void twl4030_i2c_access(int on) { unsigned long timeout; int val = twl4030_usb_read(PHY_CLK_CTRL); if (val >= 0) { if (on) { /* enable DPLL to access PHY registers over I2C */ val |= REQ_PHY_DPLL_CLK; if (twl4030_usb_write_verify(PHY_CLK_CTRL, (u8)val) < 0) { printk(KERN_ERR "twl4030_usb: i2c write failed," " line %d\n", __LINE__); return; } timeout = jiffies + HZ; while (!(twl4030_usb_read(PHY_CLK_CTRL_STS) & PHY_DPLL_CLK) && time_before(jiffies, timeout)) udelay(10); if (!(twl4030_usb_read(PHY_CLK_CTRL_STS) & PHY_DPLL_CLK)) printk(KERN_ERR "Timeout setting T2 HSUSB " "PHY DPLL clock\n"); } else { /* let ULPI control the DPLL clock */ val &= ~REQ_PHY_DPLL_CLK; if (twl4030_usb_write_verify(PHY_CLK_CTRL, (u8)val) < 0) { printk(KERN_ERR "twl4030_usb: i2c write failed," " line %d\n", __LINE__); } } } return; }