struct pipe_context *
fd_context_init(struct fd_context *ctx, struct pipe_screen *pscreen,
const uint8_t *primtypes, void *priv)
{
struct fd_screen *screen = fd_screen(pscreen);
struct pipe_context *pctx;
int i;
ctx->screen = screen;
ctx->primtypes = primtypes;
ctx->primtype_mask = 0;
for (i = 0; i < PIPE_PRIM_MAX; i++)
if (primtypes[i])
ctx->primtype_mask |= (1 << i);
/* need some sane default in case state tracker doesn't
* set some state:
*/
ctx->sample_mask = 0xffff;
pctx = &ctx->base;
pctx->screen = pscreen;
pctx->priv = priv;
pctx->flush = fd_context_flush;
for (i = 0; i < ARRAY_SIZE(ctx->rings); i++) {
ctx->rings[i] = fd_ringbuffer_new(screen->pipe, 0x100000);
if (!ctx->rings[i])
goto fail;
}
fd_context_next_rb(pctx);
fd_reset_wfi(ctx);
util_dynarray_init(&ctx->draw_patches);
util_slab_create(&ctx->transfer_pool, sizeof(struct pipe_transfer),
16, UTIL_SLAB_SINGLETHREADED);
fd_draw_init(pctx);
fd_resource_context_init(pctx);
fd_query_context_init(pctx);
fd_texture_init(pctx);
fd_state_init(pctx);
ctx->blitter = util_blitter_create(pctx);
if (!ctx->blitter)
goto fail;
ctx->primconvert = util_primconvert_create(pctx, ctx->primtype_mask);
if (!ctx->primconvert)
goto fail;
return pctx;
fail:
pctx->destroy(pctx);
return NULL;
}
struct pipe_context *
vc4_context_create(struct pipe_screen *pscreen, void *priv, unsigned flags)
{
struct vc4_screen *screen = vc4_screen(pscreen);
struct vc4_context *vc4;
/* Prevent dumping of the shaders built during context setup. */
uint32_t saved_shaderdb_flag = vc4_debug & VC4_DEBUG_SHADERDB;
vc4_debug &= ~VC4_DEBUG_SHADERDB;
vc4 = rzalloc(NULL, struct vc4_context);
if (!vc4)
return NULL;
struct pipe_context *pctx = &vc4->base;
vc4->screen = screen;
pctx->screen = pscreen;
pctx->priv = priv;
pctx->destroy = vc4_context_destroy;
pctx->flush = vc4_pipe_flush;
pctx->invalidate_resource = vc4_invalidate_resource;
vc4_draw_init(pctx);
vc4_state_init(pctx);
vc4_program_init(pctx);
vc4_query_init(pctx);
vc4_resource_context_init(pctx);
vc4_job_init(vc4);
vc4->fd = screen->fd;
util_slab_create(&vc4->transfer_pool, sizeof(struct vc4_transfer),
16, UTIL_SLAB_SINGLETHREADED);
vc4->blitter = util_blitter_create(pctx);
if (!vc4->blitter)
goto fail;
vc4->primconvert = util_primconvert_create(pctx,
(1 << PIPE_PRIM_QUADS) - 1);
if (!vc4->primconvert)
goto fail;
vc4->uploader = u_upload_create(pctx, 16 * 1024,
PIPE_BIND_INDEX_BUFFER,
PIPE_USAGE_STREAM);
vc4_debug |= saved_shaderdb_flag;
vc4->sample_mask = (1 << VC4_MAX_SAMPLES) - 1;
return &vc4->base;
fail:
pctx->destroy(pctx);
return NULL;
}
struct pipe_context *
vc4_context_create(struct pipe_screen *pscreen, void *priv)
{
struct vc4_screen *screen = vc4_screen(pscreen);
struct vc4_context *vc4;
/* Prevent dumping of the shaders built during context setup. */
uint32_t saved_shaderdb_flag = vc4_debug & VC4_DEBUG_SHADERDB;
vc4_debug &= ~VC4_DEBUG_SHADERDB;
vc4 = rzalloc(NULL, struct vc4_context);
if (vc4 == NULL)
return NULL;
struct pipe_context *pctx = &vc4->base;
vc4->screen = screen;
pctx->screen = pscreen;
pctx->priv = priv;
pctx->destroy = vc4_context_destroy;
pctx->flush = vc4_pipe_flush;
vc4_draw_init(pctx);
vc4_state_init(pctx);
vc4_program_init(pctx);
vc4_query_init(pctx);
vc4_resource_context_init(pctx);
vc4_init_cl(vc4, &vc4->bcl);
vc4_init_cl(vc4, &vc4->rcl);
vc4_init_cl(vc4, &vc4->shader_rec);
vc4_init_cl(vc4, &vc4->bo_handles);
vc4->dirty = ~0;
vc4->fd = screen->fd;
util_slab_create(&vc4->transfer_pool, sizeof(struct vc4_transfer),
16, UTIL_SLAB_SINGLETHREADED);
vc4->blitter = util_blitter_create(pctx);
if (!vc4->blitter)
goto fail;
vc4->primconvert = util_primconvert_create(pctx,
(1 << PIPE_PRIM_QUADS) - 1);
if (!vc4->primconvert)
goto fail;
vc4_debug |= saved_shaderdb_flag;
return &vc4->base;
fail:
pctx->destroy(pctx);
return NULL;
}
bool r600_common_context_init(struct r600_common_context *rctx,
struct r600_common_screen *rscreen)
{
util_slab_create(&rctx->pool_transfers,
sizeof(struct r600_transfer), 64,
UTIL_SLAB_SINGLETHREADED);
rctx->screen = rscreen;
rctx->ws = rscreen->ws;
rctx->family = rscreen->family;
rctx->chip_class = rscreen->chip_class;
if (rscreen->family == CHIP_HAWAII)
rctx->max_db = 16;
else if (rscreen->chip_class >= EVERGREEN)
rctx->max_db = 8;
else
rctx->max_db = 4;
rctx->b.transfer_map = u_transfer_map_vtbl;
rctx->b.transfer_flush_region = u_default_transfer_flush_region;
rctx->b.transfer_unmap = u_transfer_unmap_vtbl;
rctx->b.transfer_inline_write = u_default_transfer_inline_write;
rctx->b.memory_barrier = r600_memory_barrier;
rctx->b.flush = r600_flush_from_st;
LIST_INITHEAD(&rctx->texture_buffers);
r600_init_context_texture_functions(rctx);
r600_streamout_init(rctx);
r600_query_init(rctx);
cayman_init_msaa(&rctx->b);
rctx->allocator_so_filled_size = u_suballocator_create(&rctx->b, 4096, 4,
0, PIPE_USAGE_DEFAULT, TRUE);
if (!rctx->allocator_so_filled_size)
return false;
rctx->uploader = u_upload_create(&rctx->b, 1024 * 1024, 256,
PIPE_BIND_INDEX_BUFFER |
PIPE_BIND_CONSTANT_BUFFER);
if (!rctx->uploader)
return false;
if (rscreen->info.r600_has_dma && !(rscreen->debug_flags & DBG_NO_ASYNC_DMA)) {
rctx->rings.dma.cs = rctx->ws->cs_create(rctx->ws, RING_DMA,
r600_flush_dma_ring,
rctx, NULL);
rctx->rings.dma.flush = r600_flush_dma_ring;
}
return true;
}
void etna_pipe_transfer_init(struct pipe_context *pc)
{
struct etna_pipe_context *priv = etna_pipe_context(pc);
pc->transfer_map = etna_pipe_transfer_map;
pc->transfer_flush_region = etna_pipe_transfer_flush_region;
pc->transfer_unmap = etna_pipe_transfer_unmap;
pc->transfer_inline_write = u_default_transfer_inline_write;
util_slab_create(&priv->transfer_pool, sizeof(struct etna_transfer),
16, UTIL_SLAB_SINGLETHREADED);
}
struct pipe_screen* r300_screen_create(struct radeon_winsys *rws)
{
struct r300_screen *r300screen = CALLOC_STRUCT(r300_screen);
if (!r300screen) {
FREE(r300screen);
return NULL;
}
rws->query_info(rws, &r300screen->info);
r300_init_debug(r300screen);
r300_parse_chipset(r300screen->info.pci_id, &r300screen->caps);
if (SCREEN_DBG_ON(r300screen, DBG_NO_ZMASK))
r300screen->caps.zmask_ram = 0;
if (SCREEN_DBG_ON(r300screen, DBG_NO_HIZ))
r300screen->caps.hiz_ram = 0;
if (r300screen->info.drm_minor < 8)
r300screen->caps.has_us_format = FALSE;
pipe_mutex_init(r300screen->num_contexts_mutex);
util_slab_create(&r300screen->pool_buffers,
sizeof(struct r300_resource), 64,
UTIL_SLAB_SINGLETHREADED);
r300screen->rws = rws;
r300screen->screen.winsys = (struct pipe_winsys*)rws;
r300screen->screen.destroy = r300_destroy_screen;
r300screen->screen.get_name = r300_get_name;
r300screen->screen.get_vendor = r300_get_vendor;
r300screen->screen.get_param = r300_get_param;
r300screen->screen.get_shader_param = r300_get_shader_param;
r300screen->screen.get_paramf = r300_get_paramf;
r300screen->screen.get_video_param = r300_get_video_param;
r300screen->screen.is_format_supported = r300_is_format_supported;
r300screen->screen.is_video_format_supported = vl_video_buffer_is_format_supported;
r300screen->screen.context_create = r300_create_context;
r300screen->screen.fence_reference = r300_fence_reference;
r300screen->screen.fence_signalled = r300_fence_signalled;
r300screen->screen.fence_finish = r300_fence_finish;
r300_init_screen_resource_functions(r300screen);
util_format_s3tc_init();
return &r300screen->screen;
}
struct pipe_context *
fd_context_create(struct pipe_screen *pscreen, void *priv)
{
struct fd_screen *screen = fd_screen(pscreen);
struct fd_context *ctx = CALLOC_STRUCT(fd_context);
struct pipe_context *pctx;
if (!ctx)
return NULL;
DBG("");
ctx->screen = screen;
ctx->ring = fd_ringbuffer_new(screen->pipe, 0x100000);
ctx->draw_start = fd_ringmarker_new(ctx->ring);
ctx->draw_end = fd_ringmarker_new(ctx->ring);
pctx = &ctx->base;
pctx->screen = pscreen;
pctx->priv = priv;
pctx->flush = fd_context_flush;
pctx->destroy = fd_context_destroy;
util_slab_create(&ctx->transfer_pool, sizeof(struct pipe_transfer),
16, UTIL_SLAB_SINGLETHREADED);
fd_vbo_init(pctx);
fd_blend_init(pctx);
fd_rasterizer_init(pctx);
fd_zsa_init(pctx);
fd_state_init(pctx);
fd_resource_context_init(pctx);
fd_clear_init(pctx);
fd_prog_init(pctx);
fd_texture_init(pctx);
ctx->blitter = util_blitter_create(pctx);
if (!ctx->blitter) {
fd_context_destroy(pctx);
return NULL;
}
/* construct vertex state used for solid ops (clear, and gmem<->mem) */
ctx->solid_vertexbuf = create_solid_vertexbuf(pctx);
fd_state_emit_setup(pctx);
return pctx;
}
struct pipe_context *
fd_context_init(struct fd_context *ctx,
struct pipe_screen *pscreen, void *priv)
{
struct fd_screen *screen = fd_screen(pscreen);
struct pipe_context *pctx;
ctx->screen = screen;
/* need some sane default in case state tracker doesn't
* set some state:
*/
ctx->sample_mask = 0xffff;
pctx = &ctx->base;
pctx->screen = pscreen;
pctx->priv = priv;
pctx->flush = fd_context_flush;
ctx->ring = fd_ringbuffer_new(screen->pipe, 0x100000);
if (!ctx->ring)
goto fail;
ctx->draw_start = fd_ringmarker_new(ctx->ring);
ctx->draw_end = fd_ringmarker_new(ctx->ring);
util_slab_create(&ctx->transfer_pool, sizeof(struct pipe_transfer),
16, UTIL_SLAB_SINGLETHREADED);
fd_draw_init(pctx);
fd_resource_context_init(pctx);
fd_texture_init(pctx);
fd_state_init(pctx);
ctx->blitter = util_blitter_create(pctx);
if (!ctx->blitter)
goto fail;
return pctx;
fail:
pctx->destroy(pctx);
return NULL;
}
/**
* Initialize the toy compiler.
*/
void
toy_compiler_init(struct toy_compiler *tc, const struct ilo_dev_info *dev)
{
memset(tc, 0, sizeof(*tc));
tc->dev = dev;
tc_init_inst_templ(tc);
util_slab_create(&tc->mempool, sizeof(struct toy_inst),
64, UTIL_SLAB_SINGLETHREADED);
list_inithead(&tc->instructions);
/* instructions are added to the tail */
tc_tail(tc);
tc->rect_linear_width = 1;
/* skip 0 so that util_hash_table_get() never returns NULL */
tc->next_vrf = 1;
}
struct pipe_context *
i915_create_context(struct pipe_screen *screen, void *priv)
{
struct i915_context *i915;
i915 = CALLOC_STRUCT(i915_context);
if (i915 == NULL)
return NULL;
i915->iws = i915_screen(screen)->iws;
i915->base.screen = screen;
i915->base.priv = priv;
i915->base.destroy = i915_destroy;
if (i915_screen(screen)->debug.use_blitter)
i915->base.clear = i915_clear_blitter;
else
i915->base.clear = i915_clear_render;
i915->base.draw_vbo = i915_draw_vbo;
/* init this before draw */
util_slab_create(&i915->transfer_pool, sizeof(struct pipe_transfer),
16, UTIL_SLAB_SINGLETHREADED);
util_slab_create(&i915->texture_transfer_pool, sizeof(struct i915_transfer),
16, UTIL_SLAB_SINGLETHREADED);
/* Batch stream debugging is a bit hacked up at the moment:
*/
i915->batch = i915->iws->batchbuffer_create(i915->iws);
/*
* Create drawing context and plug our rendering stage into it.
*/
i915->draw = draw_create(&i915->base);
assert(i915->draw);
if (!debug_get_option_i915_no_vbuf()) {
draw_set_rasterize_stage(i915->draw, i915_draw_vbuf_stage(i915));
} else {
draw_set_rasterize_stage(i915->draw, i915_draw_render_stage(i915));
}
i915_init_surface_functions(i915);
i915_init_state_functions(i915);
i915_init_flush_functions(i915);
i915_init_resource_functions(i915);
i915_init_query_functions(i915);
draw_install_aaline_stage(i915->draw, &i915->base);
draw_install_aapoint_stage(i915->draw, &i915->base);
draw_enable_point_sprites(i915->draw, TRUE);
/* augmented draw pipeline clobbers state functions */
i915_init_fixup_state_functions(i915);
/* Create blitter last - calls state creation functions. */
i915->blitter = util_blitter_create(&i915->base);
assert(i915->blitter);
i915->dirty = ~0;
i915->hardware_dirty = ~0;
i915->immediate_dirty = ~0;
i915->dynamic_dirty = ~0;
i915->static_dirty = ~0;
i915->flush_dirty = 0;
return &i915->base;
}
struct pipe_context* r300_create_context(struct pipe_screen* screen,
void *priv)
{
struct r300_context* r300 = CALLOC_STRUCT(r300_context);
struct r300_screen* r300screen = r300_screen(screen);
struct radeon_winsys *rws = r300screen->rws;
if (!r300)
return NULL;
r300->rws = rws;
r300->screen = r300screen;
r300->context.screen = screen;
r300->context.priv = priv;
r300->context.destroy = r300_destroy_context;
util_slab_create(&r300->pool_transfers,
sizeof(struct pipe_transfer), 64,
UTIL_SLAB_SINGLETHREADED);
r300->cs = rws->cs_create(rws, RING_GFX, r300_flush_callback, r300, NULL);
if (r300->cs == NULL)
goto fail;
if (!r300screen->caps.has_tcl) {
/* Create a Draw. This is used for SW TCL. */
r300->draw = draw_create(&r300->context);
if (r300->draw == NULL)
goto fail;
/* Enable our renderer. */
draw_set_rasterize_stage(r300->draw, r300_draw_stage(r300));
/* Disable converting points/lines to triangles. */
draw_wide_line_threshold(r300->draw, 10000000.f);
draw_wide_point_threshold(r300->draw, 10000000.f);
draw_wide_point_sprites(r300->draw, FALSE);
draw_enable_line_stipple(r300->draw, TRUE);
draw_enable_point_sprites(r300->draw, FALSE);
}
if (!r300_setup_atoms(r300))
goto fail;
r300_init_blit_functions(r300);
r300_init_flush_functions(r300);
r300_init_query_functions(r300);
r300_init_state_functions(r300);
r300_init_resource_functions(r300);
r300_init_render_functions(r300);
r300_init_states(&r300->context);
r300->context.create_video_codec = vl_create_decoder;
r300->context.create_video_buffer = vl_video_buffer_create;
r300->uploader = u_upload_create(&r300->context, 256 * 1024, 4,
PIPE_BIND_CUSTOM);
r300->blitter = util_blitter_create(&r300->context);
if (r300->blitter == NULL)
goto fail;
r300->blitter->draw_rectangle = r300_blitter_draw_rectangle;
/* The KIL opcode needs the first texture unit to be enabled
* on r3xx-r4xx. In order to calm down the CS checker, we bind this
* dummy texture there. */
if (!r300->screen->caps.is_r500) {
struct pipe_resource *tex;
struct pipe_resource rtempl = {{0}};
struct pipe_sampler_view vtempl = {{0}};
rtempl.target = PIPE_TEXTURE_2D;
rtempl.format = PIPE_FORMAT_I8_UNORM;
rtempl.usage = PIPE_USAGE_IMMUTABLE;
rtempl.width0 = 1;
rtempl.height0 = 1;
rtempl.depth0 = 1;
tex = screen->resource_create(screen, &rtempl);
u_sampler_view_default_template(&vtempl, tex, tex->format);
r300->texkill_sampler = (struct r300_sampler_view*)
r300->context.create_sampler_view(&r300->context, tex, &vtempl);
pipe_resource_reference(&tex, NULL);
}
if (r300screen->caps.has_tcl) {
struct pipe_resource vb;
memset(&vb, 0, sizeof(vb));
vb.target = PIPE_BUFFER;
vb.format = PIPE_FORMAT_R8_UNORM;
vb.usage = PIPE_USAGE_DEFAULT;
vb.width0 = sizeof(float) * 16;
vb.height0 = 1;
vb.depth0 = 1;
r300->dummy_vb.buffer = screen->resource_create(screen, &vb);
r300->context.set_vertex_buffers(&r300->context, 0, 1, &r300->dummy_vb);
}
{
struct pipe_depth_stencil_alpha_state dsa;
memset(&dsa, 0, sizeof(dsa));
dsa.depth.writemask = 1;
r300->dsa_decompress_zmask =
r300->context.create_depth_stencil_alpha_state(&r300->context,
&dsa);
}
r300->hyperz_time_of_last_flush = os_time_get();
/* Register allocator state */
rc_init_regalloc_state(&r300->fs_regalloc_state);
/* Print driver info. */
#ifdef DEBUG
{
#else
if (DBG_ON(r300, DBG_INFO)) {
#endif
fprintf(stderr,
"r300: DRM version: %d.%d.%d, Name: %s, ID: 0x%04x, GB: %d, Z: %d\n"
"r300: GART size: %"PRIu64" MB, VRAM size: %"PRIu64" MB\n"
"r300: AA compression RAM: %s, Z compression RAM: %s, HiZ RAM: %s\n",
r300->screen->info.drm_major,
r300->screen->info.drm_minor,
r300->screen->info.drm_patchlevel,
screen->get_name(screen),
r300->screen->info.pci_id,
r300->screen->info.r300_num_gb_pipes,
r300->screen->info.r300_num_z_pipes,
r300->screen->info.gart_size >> 20,
r300->screen->info.vram_size >> 20,
"YES", /* XXX really? */
r300->screen->caps.zmask_ram ? "YES" : "NO",
r300->screen->caps.hiz_ram ? "YES" : "NO");
}
return &r300->context;
fail:
r300_destroy_context(&r300->context);
return NULL;
}
bool r600_common_context_init(struct r600_common_context *rctx,
struct r600_common_screen *rscreen)
{
util_slab_create(&rctx->pool_transfers,
sizeof(struct r600_transfer), 64,
UTIL_SLAB_SINGLETHREADED);
rctx->screen = rscreen;
rctx->ws = rscreen->ws;
rctx->family = rscreen->family;
rctx->chip_class = rscreen->chip_class;
if (rscreen->chip_class >= CIK)
rctx->max_db = MAX2(8, rscreen->info.r600_num_backends);
else if (rscreen->chip_class >= EVERGREEN)
rctx->max_db = 8;
else
rctx->max_db = 4;
rctx->b.invalidate_resource = r600_invalidate_resource;
rctx->b.transfer_map = u_transfer_map_vtbl;
rctx->b.transfer_flush_region = u_transfer_flush_region_vtbl;
rctx->b.transfer_unmap = u_transfer_unmap_vtbl;
rctx->b.transfer_inline_write = u_default_transfer_inline_write;
rctx->b.memory_barrier = r600_memory_barrier;
rctx->b.flush = r600_flush_from_st;
rctx->b.set_debug_callback = r600_set_debug_callback;
if (rscreen->info.drm_major == 2 && rscreen->info.drm_minor >= 43) {
rctx->b.get_device_reset_status = r600_get_reset_status;
rctx->gpu_reset_counter =
rctx->ws->query_value(rctx->ws,
RADEON_GPU_RESET_COUNTER);
}
LIST_INITHEAD(&rctx->texture_buffers);
r600_init_context_texture_functions(rctx);
r600_streamout_init(rctx);
r600_query_init(rctx);
cayman_init_msaa(&rctx->b);
rctx->allocator_so_filled_size = u_suballocator_create(&rctx->b, 4096, 4,
0, PIPE_USAGE_DEFAULT, TRUE);
if (!rctx->allocator_so_filled_size)
return false;
rctx->uploader = u_upload_create(&rctx->b, 1024 * 1024,
PIPE_BIND_INDEX_BUFFER |
PIPE_BIND_CONSTANT_BUFFER, PIPE_USAGE_STREAM);
if (!rctx->uploader)
return false;
rctx->ctx = rctx->ws->ctx_create(rctx->ws);
if (!rctx->ctx)
return false;
if (rscreen->info.r600_has_dma && !(rscreen->debug_flags & DBG_NO_ASYNC_DMA)) {
rctx->dma.cs = rctx->ws->cs_create(rctx->ctx, RING_DMA,
r600_flush_dma_ring,
rctx, NULL);
rctx->dma.flush = r600_flush_dma_ring;
}
return true;
}
static struct pipe_context *
ilo_context_create(struct pipe_screen *screen, void *priv, unsigned flags)
{
struct ilo_screen *is = ilo_screen(screen);
struct ilo_context *ilo;
ilo = CALLOC_STRUCT(ilo_context);
if (!ilo)
return NULL;
ilo->winsys = is->dev.winsys;
ilo->dev = &is->dev;
/*
* initialize first, otherwise it may not be safe to call
* ilo_context_destroy() on errors
*/
util_slab_create(&ilo->transfer_mempool,
sizeof(struct ilo_transfer), 64, UTIL_SLAB_SINGLETHREADED);
ilo->shader_cache = ilo_shader_cache_create();
ilo->cp = ilo_cp_create(ilo->dev, ilo->winsys, ilo->shader_cache);
if (ilo->cp)
ilo->render = ilo_render_create(&ilo->cp->builder);
if (!ilo->cp || !ilo->shader_cache || !ilo->render) {
ilo_context_destroy(&ilo->base);
return NULL;
}
ilo_cp_set_submit_callback(ilo->cp,
ilo_context_cp_submitted, (void *) ilo);
ilo->base.screen = screen;
ilo->base.priv = priv;
ilo->base.destroy = ilo_context_destroy;
ilo->base.flush = ilo_flush;
ilo->base.render_condition = ilo_render_condition;
ilo_init_draw_functions(ilo);
ilo_init_query_functions(ilo);
ilo_init_state_functions(ilo);
ilo_init_blit_functions(ilo);
ilo_init_transfer_functions(ilo);
ilo_init_video_functions(ilo);
ilo_init_gpgpu_functions(ilo);
ilo_init_draw(ilo);
ilo_state_vector_init(ilo->dev, &ilo->state_vector);
/*
* These must be called last as u_upload/u_blitter are clients of the pipe
* context.
*/
ilo->uploader = u_upload_create(&ilo->base, 1024 * 1024,
PIPE_BIND_CONSTANT_BUFFER | PIPE_BIND_INDEX_BUFFER,
PIPE_USAGE_STREAM);
if (!ilo->uploader) {
ilo_context_destroy(&ilo->base);
return NULL;
}
ilo->blitter = ilo_blitter_create(ilo);
if (!ilo->blitter) {
ilo_context_destroy(&ilo->base);
return NULL;
}
return &ilo->base;
}
static struct pipe_context *
ilo_context_create(struct pipe_screen *screen, void *priv)
{
struct ilo_screen *is = ilo_screen(screen);
struct ilo_context *ilo;
ilo = CALLOC_STRUCT(ilo_context);
if (!ilo)
return NULL;
ilo->winsys = is->winsys;
ilo->dev = &is->dev;
/*
* initialize first, otherwise it may not be safe to call
* ilo_context_destroy() on errors
*/
util_slab_create(&ilo->transfer_mempool,
sizeof(struct ilo_transfer), 64, UTIL_SLAB_SINGLETHREADED);
/* 8192 DWords */
ilo->cp = ilo_cp_create(ilo->winsys, 8192, is->dev.has_llc);
ilo->shader_cache = ilo_shader_cache_create();
if (ilo->cp)
ilo->hw3d = ilo_3d_create(ilo->cp, ilo->dev);
if (!ilo->cp || !ilo->shader_cache || !ilo->hw3d) {
ilo_context_destroy(&ilo->base);
return NULL;
}
ilo_cp_set_flush_callback(ilo->cp,
ilo_context_cp_flushed, (void *) ilo);
ilo->base.screen = screen;
ilo->base.priv = priv;
ilo->base.destroy = ilo_context_destroy;
ilo->base.flush = ilo_flush;
ilo_init_3d_functions(ilo);
ilo_init_query_functions(ilo);
ilo_init_state_functions(ilo);
ilo_init_blit_functions(ilo);
ilo_init_transfer_functions(ilo);
ilo_init_video_functions(ilo);
ilo_init_gpgpu_functions(ilo);
ilo_init_states(ilo);
/*
* These must be called last as u_upload/u_blitter are clients of the pipe
* context.
*/
ilo->uploader = u_upload_create(&ilo->base, 1024 * 1024, 16,
PIPE_BIND_CONSTANT_BUFFER | PIPE_BIND_INDEX_BUFFER);
if (!ilo->uploader) {
ilo_context_destroy(&ilo->base);
return NULL;
}
ilo->blitter = ilo_blitter_create(ilo);
if (!ilo->blitter) {
ilo_context_destroy(&ilo->base);
return NULL;
}
return &ilo->base;
}
static struct pipe_context *r600_create_context(struct pipe_screen *screen, void *priv)
{
struct r600_context *rctx = CALLOC_STRUCT(r600_context);
struct r600_screen* rscreen = (struct r600_screen *)screen;
int shader, i;
if (rctx == NULL)
return NULL;
if (!r600_common_context_init(&rctx->b, &rscreen->b))
goto fail;
rctx->b.b.screen = screen;
rctx->b.b.priv = priv;
rctx->b.b.destroy = r600_destroy_context;
rctx->b.b.flush = r600_flush_from_st;
/* Easy accessing of screen/winsys. */
rctx->screen = rscreen;
si_init_blit_functions(rctx);
r600_init_query_functions(rctx);
r600_init_context_resource_functions(rctx);
si_init_compute_functions(rctx);
if (rscreen->b.info.has_uvd) {
rctx->b.b.create_video_codec = radeonsi_uvd_create_decoder;
rctx->b.b.create_video_buffer = radeonsi_video_buffer_create;
} else {
rctx->b.b.create_video_codec = vl_create_decoder;
rctx->b.b.create_video_buffer = vl_video_buffer_create;
}
rctx->b.rings.gfx.cs = rctx->b.ws->cs_create(rctx->b.ws, RING_GFX, NULL);
rctx->b.rings.gfx.flush = r600_flush_from_winsys;
si_init_all_descriptors(rctx);
/* Initialize cache_flush. */
rctx->cache_flush = si_atom_cache_flush;
rctx->atoms.cache_flush = &rctx->cache_flush;
rctx->atoms.streamout_begin = &rctx->b.streamout.begin_atom;
switch (rctx->b.chip_class) {
case SI:
case CIK:
si_init_state_functions(rctx);
LIST_INITHEAD(&rctx->active_nontimer_query_list);
rctx->max_db = 8;
si_init_config(rctx);
break;
default:
R600_ERR("Unsupported chip class %d.\n", rctx->b.chip_class);
goto fail;
}
rctx->b.ws->cs_set_flush_callback(rctx->b.rings.gfx.cs, r600_flush_from_winsys, rctx);
util_slab_create(&rctx->pool_transfers,
sizeof(struct pipe_transfer), 64,
UTIL_SLAB_SINGLETHREADED);
rctx->uploader = u_upload_create(&rctx->b.b, 1024 * 1024, 256,
PIPE_BIND_INDEX_BUFFER |
PIPE_BIND_CONSTANT_BUFFER);
if (!rctx->uploader)
goto fail;
rctx->blitter = util_blitter_create(&rctx->b.b);
if (rctx->blitter == NULL)
goto fail;
rctx->dummy_pixel_shader =
util_make_fragment_cloneinput_shader(&rctx->b.b, 0,
TGSI_SEMANTIC_GENERIC,
TGSI_INTERPOLATE_CONSTANT);
rctx->b.b.bind_fs_state(&rctx->b.b, rctx->dummy_pixel_shader);
/* these must be last */
si_begin_new_cs(rctx);
si_get_backend_mask(rctx);
/* CIK cannot unbind a constant buffer (S_BUFFER_LOAD is buggy
* with a NULL buffer). We need to use a dummy buffer instead. */
if (rctx->b.chip_class == CIK) {
rctx->null_const_buf.buffer = pipe_buffer_create(screen, PIPE_BIND_CONSTANT_BUFFER,
PIPE_USAGE_STATIC, 16);
rctx->null_const_buf.buffer_size = rctx->null_const_buf.buffer->width0;
for (shader = 0; shader < SI_NUM_SHADERS; shader++) {
for (i = 0; i < NUM_CONST_BUFFERS; i++) {
rctx->b.b.set_constant_buffer(&rctx->b.b, shader, i,
&rctx->null_const_buf);
}
}
/* Clear the NULL constant buffer, because loads should return zeros. */
rctx->b.clear_buffer(&rctx->b.b, rctx->null_const_buf.buffer, 0,
rctx->null_const_buf.buffer->width0, 0);
}
return &rctx->b.b;
fail:
r600_destroy_context(&rctx->b.b);
return NULL;
}