/**Function************************************************************* Synopsis [Computes initial values of the new latches.] Description [] SideEffects [] SeeAlso [] ***********************************************************************/ Vec_Int_t * Abc_NtkRetimeInitialValues( Abc_Ntk_t * pNtkCone, Vec_Int_t * vValues, int fVerbose ) { Vec_Int_t * vSolution; Abc_Ntk_t * pNtkMiter, * pNtkLogic; int RetValue; abctime clk; if ( pNtkCone == NULL ) return Vec_IntDup( vValues ); // convert the target network to AIG pNtkLogic = Abc_NtkDup( pNtkCone ); Abc_NtkToAig( pNtkLogic ); // get the miter pNtkMiter = Abc_NtkCreateTarget( pNtkLogic, pNtkLogic->vCos, vValues ); if ( fVerbose ) printf( "The miter for initial state computation has %d AIG nodes. ", Abc_NtkNodeNum(pNtkMiter) ); // solve the miter clk = Abc_Clock(); RetValue = Abc_NtkMiterSat( pNtkMiter, (ABC_INT64_T)500000, (ABC_INT64_T)50000000, 0, NULL, NULL ); if ( fVerbose ) { ABC_PRT( "SAT solving time", Abc_Clock() - clk ); } // analyze the result if ( RetValue == 1 ) printf( "Abc_NtkRetimeInitialValues(): The problem is unsatisfiable. DC latch values are used.\n" ); else if ( RetValue == -1 ) printf( "Abc_NtkRetimeInitialValues(): The SAT problem timed out. DC latch values are used.\n" ); else if ( !Abc_NtkRetimeVerifyModel( pNtkCone, vValues, pNtkMiter->pModel ) ) printf( "Abc_NtkRetimeInitialValues(): The computed counter-example is incorrect.\n" ); // set the values of the latches vSolution = RetValue? NULL : Vec_IntAllocArray( pNtkMiter->pModel, Abc_NtkPiNum(pNtkLogic) ); pNtkMiter->pModel = NULL; Abc_NtkDelete( pNtkMiter ); Abc_NtkDelete( pNtkLogic ); return vSolution; }
/**Function************************************************************* Synopsis [Interface with the FPGA mapping package.] Description [] SideEffects [] SeeAlso [] ***********************************************************************/ Abc_Ntk_t * Abc_NtkFpga( Abc_Ntk_t * pNtk, float DelayTarget, int fRecovery, int fSwitching, int fLatchPaths, int fVerbose ) { int fShowSwitching = 1; Abc_Ntk_t * pNtkNew; Fpga_Man_t * pMan; Vec_Int_t * vSwitching; float * pSwitching = NULL; assert( Abc_NtkIsStrash(pNtk) ); // print a warning about choice nodes if ( Abc_NtkGetChoiceNum( pNtk ) ) printf( "Performing FPGA mapping with choices.\n" ); // compute switching activity fShowSwitching |= fSwitching; if ( fShowSwitching ) { extern Vec_Int_t * Sim_NtkComputeSwitching( Abc_Ntk_t * pNtk, int nPatterns ); vSwitching = Sim_NtkComputeSwitching( pNtk, 4096 ); pSwitching = (float *)vSwitching->pArray; } // perform FPGA mapping pMan = Abc_NtkToFpga( pNtk, fRecovery, pSwitching, fLatchPaths, fVerbose ); if ( pSwitching ) Vec_IntFree( vSwitching ); if ( pMan == NULL ) return NULL; Fpga_ManSetSwitching( pMan, fSwitching ); Fpga_ManSetLatchPaths( pMan, fLatchPaths ); Fpga_ManSetLatchNum( pMan, Abc_NtkLatchNum(pNtk) ); Fpga_ManSetDelayTarget( pMan, DelayTarget ); if ( !Fpga_Mapping( pMan ) ) { Fpga_ManFree( pMan ); return NULL; } // transform the result of mapping into a BDD network pNtkNew = Abc_NtkFromFpga( pMan, pNtk ); if ( pNtkNew == NULL ) return NULL; Fpga_ManFree( pMan ); // make the network minimum base Abc_NtkMinimumBase( pNtkNew ); if ( pNtk->pExdc ) pNtkNew->pExdc = Abc_NtkDup( pNtk->pExdc ); // make sure that everything is okay if ( !Abc_NtkCheck( pNtkNew ) ) { printf( "Abc_NtkFpga: The network check has failed.\n" ); Abc_NtkDelete( pNtkNew ); return NULL; } return pNtkNew; }
/**Function************************************************************* Synopsis [Transforms the AIG into nodes.] Description [Threhold is the max number of nodes duplicated at a node.] SideEffects [] SeeAlso [] ***********************************************************************/ Abc_Ntk_t * Abc_NtkMulti( Abc_Ntk_t * pNtk, int nThresh, int nFaninMax, int fCnf, int fMulti, int fSimple, int fFactor ) { Abc_Ntk_t * pNtkNew; assert( Abc_NtkIsStrash(pNtk) ); assert( nThresh >= 0 ); assert( nFaninMax > 1 ); // print a warning about choice nodes if ( Abc_NtkGetChoiceNum( pNtk ) ) printf( "Warning: The choice nodes in the AIG are removed by renoding.\n" ); // define the boundary if ( fCnf ) Abc_NtkMultiSetBoundsCnf( pNtk ); else if ( fMulti ) Abc_NtkMultiSetBoundsMulti( pNtk, nThresh ); else if ( fSimple ) Abc_NtkMultiSetBoundsSimple( pNtk ); else if ( fFactor ) Abc_NtkMultiSetBoundsFactor( pNtk ); else Abc_NtkMultiSetBounds( pNtk, nThresh, nFaninMax ); // perform renoding for this boundary pNtkNew = Abc_NtkStartFrom( pNtk, ABC_NTK_LOGIC, ABC_FUNC_BDD ); Abc_NtkMultiInt( pNtk, pNtkNew ); Abc_NtkFinalize( pNtk, pNtkNew ); // make the network minimum base Abc_NtkMinimumBase( pNtkNew ); // fix the problem with complemented and duplicated CO edges Abc_NtkLogicMakeSimpleCos( pNtkNew, 0 ); // report the number of CNF objects if ( fCnf ) { // int nClauses = Abc_NtkGetClauseNum(pNtkNew) + 2*Abc_NtkPoNum(pNtkNew) + 2*Abc_NtkLatchNum(pNtkNew); // printf( "CNF variables = %d. CNF clauses = %d.\n", Abc_NtkNodeNum(pNtkNew), nClauses ); } //printf( "Maximum fanin = %d.\n", Abc_NtkGetFaninMax(pNtkNew) ); if ( pNtk->pExdc ) pNtkNew->pExdc = Abc_NtkDup( pNtk->pExdc ); // make sure everything is okay if ( !Abc_NtkCheck( pNtkNew ) ) { printf( "Abc_NtkMulti: The network check has failed.\n" ); Abc_NtkDelete( pNtkNew ); return NULL; } return pNtkNew; }
/**Function************************************************************* Synopsis [Used for automated debugging.] Description [] SideEffects [] SeeAlso [] ***********************************************************************/ int Abc_NtkRetimeDebug( Abc_Ntk_t * pNtk ) { extern int Abc_NtkSecFraig( Abc_Ntk_t * pNtk1, Abc_Ntk_t * pNtk2, int nSeconds, int nFrames, int fVerbose ); Abc_Ntk_t * pNtkRet; assert( Abc_NtkIsLogic(pNtk) ); Abc_NtkToSop( pNtk, 0 ); // if ( !Abc_NtkCheck( pNtk ) ) // fprintf( stdout, "Abc_NtkRetimeDebug(): Network check has failed.\n" ); // Io_WriteBlifLogic( pNtk, "debug_temp.blif", 1 ); pNtkRet = Abc_NtkDup( pNtk ); Abc_NtkRetime( pNtkRet, 3, 0, 1, 0, 0 ); // debugging backward flow return !Abc_NtkSecFraig( pNtk, pNtkRet, 10000, 3, 0 ); }
/**Function************************************************************* Synopsis [Performs retiming in one direction.] Description [Currently does not retime over black boxes.] SideEffects [] SeeAlso [] ***********************************************************************/ int Abc_NtkRetimeIncremental( Abc_Ntk_t * pNtk, int nDelayLim, int fForward, int fMinDelay, int fOneStep, int fVerbose ) { Abc_Ntk_t * pNtkCopy = NULL; Vec_Ptr_t * vBoxes; st__table * tLatches; int nLatches = Abc_NtkLatchNum(pNtk); int nIdMaxStart = Abc_NtkObjNumMax(pNtk); int RetValue; int nIterLimit = -1; // Suppress "might be used uninitialized" if ( Abc_NtkNodeNum(pNtk) == 0 ) return 0; // reorder CI/CO/latch inputs Abc_NtkOrderCisCos( pNtk ); if ( fMinDelay ) { nIterLimit = fOneStep? 1 : 2 * Abc_NtkLevel(pNtk); pNtkCopy = Abc_NtkDup( pNtk ); tLatches = Abc_NtkRetimePrepareLatches( pNtkCopy ); st__free_table( tLatches ); } // collect latches and remove CIs/COs tLatches = Abc_NtkRetimePrepareLatches( pNtk ); // share the latches Abc_NtkRetimeShareLatches( pNtk, 0 ); // save boxes vBoxes = pNtk->vBoxes; pNtk->vBoxes = NULL; // perform the retiming if ( fMinDelay ) Abc_NtkRetimeMinDelay( pNtk, pNtkCopy, nDelayLim, nIterLimit, fForward, fVerbose ); else Abc_NtkRetimeOneWay( pNtk, fForward, fVerbose ); if ( fMinDelay ) Abc_NtkDelete( pNtkCopy ); // share the latches Abc_NtkRetimeShareLatches( pNtk, 0 ); // restore boxes pNtk->vBoxes = vBoxes; // finalize the latches RetValue = Abc_NtkRetimeFinalizeLatches( pNtk, tLatches, nIdMaxStart ); st__free_table( tLatches ); if ( RetValue == 0 ) return 0; // fix the COs // Abc_NtkLogicMakeSimpleCos( pNtk, 0 ); // check for correctness if ( !Abc_NtkCheck( pNtk ) ) fprintf( stdout, "Abc_NtkRetimeForward(): Network check has failed.\n" ); // return the number of latches saved return nLatches - Abc_NtkLatchNum(pNtk); }
/**Function************************************************************* Synopsis [Creates the mapped network.] Description [] SideEffects [] SeeAlso [] ***********************************************************************/ Abc_Ntk_t * Abc_NtkFromMapSuperChoice( Map_Man_t * pMan, Abc_Ntk_t * pNtk ) { extern Abc_Ntk_t * Abc_NtkMulti( Abc_Ntk_t * pNtk, int nThresh, int nFaninMax, int fCnf, int fMulti, int fSimple, int fFactor ); ProgressBar * pProgress; Abc_Ntk_t * pNtkNew, * pNtkNew2; Abc_Obj_t * pNode; int i; // save the pointer to the mapped nodes Abc_NtkForEachCi( pNtk, pNode, i ) pNode->pNext = pNode->pCopy; Abc_NtkForEachPo( pNtk, pNode, i ) pNode->pNext = pNode->pCopy; Abc_NtkForEachNode( pNtk, pNode, i ) pNode->pNext = pNode->pCopy; // duplicate the network pNtkNew2 = Abc_NtkDup( pNtk ); pNtkNew = Abc_NtkMulti( pNtkNew2, 0, 20, 0, 0, 1, 0 ); if ( !Abc_NtkBddToSop( pNtkNew, -1, ABC_INFINITY ) ) { printf( "Abc_NtkFromMapSuperChoice(): Converting to SOPs has failed.\n" ); return NULL; } // set the old network to point to the new network Abc_NtkForEachCi( pNtk, pNode, i ) pNode->pCopy = pNode->pCopy->pCopy; Abc_NtkForEachPo( pNtk, pNode, i ) pNode->pCopy = pNode->pCopy->pCopy; Abc_NtkForEachNode( pNtk, pNode, i ) pNode->pCopy = pNode->pCopy->pCopy; Abc_NtkDelete( pNtkNew2 ); // set the pointers from the mapper to the new nodes Abc_NtkForEachCi( pNtk, pNode, i ) { Map_NodeSetData( Map_ManReadInputs(pMan)[i], 0, (char *)Abc_NtkCreateNodeInv(pNtkNew,pNode->pCopy) ); Map_NodeSetData( Map_ManReadInputs(pMan)[i], 1, (char *)pNode->pCopy ); }
/**Function************************************************************* Synopsis [Prepares the IVY package.] Description [] SideEffects [] SeeAlso [] ***********************************************************************/ Abc_Ntk_t * Abc_NtkIvyAfter( Abc_Ntk_t * pNtk, Ivy_Man_t * pMan, int fSeq, int fHaig ) { Abc_Ntk_t * pNtkAig; int nNodes, fCleanup = 1; // convert from the AIG manager if ( fSeq ) pNtkAig = Abc_NtkFromIvySeq( pNtk, pMan, fHaig ); else pNtkAig = Abc_NtkFromIvy( pNtk, pMan ); // report the cleanup results if ( !fHaig && fCleanup && (nNodes = Abc_AigCleanup(pNtkAig->pManFunc)) ) printf( "Warning: AIG cleanup removed %d nodes (this is not a bug).\n", nNodes ); // duplicate EXDC if ( pNtk->pExdc ) pNtkAig->pExdc = Abc_NtkDup( pNtk->pExdc ); // make sure everything is okay if ( !Abc_NtkCheck( pNtkAig ) ) { printf( "Abc_NtkStrash: The network check has failed.\n" ); Abc_NtkDelete( pNtkAig ); return NULL; } return pNtkAig; }
/**Function************************************************************* Synopsis [Interface with the mapping package.] Description [] SideEffects [] SeeAlso [] ***********************************************************************/ Abc_Ntk_t * Abc_NtkMap( Abc_Ntk_t * pNtk, double DelayTarget, double AreaMulti, double DelayMulti, float LogFan, float Slew, float Gain, int nGatesMin, int fRecovery, int fSwitching, int fSkipFanout, int fVerbose ) { static int fUseMulti = 0; int fShowSwitching = 1; Abc_Ntk_t * pNtkNew; Map_Man_t * pMan; Vec_Int_t * vSwitching = NULL; float * pSwitching = NULL; abctime clk, clkTotal = Abc_Clock(); Mio_Library_t * pLib = (Mio_Library_t *)Abc_FrameReadLibGen(); assert( Abc_NtkIsStrash(pNtk) ); // derive library from SCL // if the library is created here, it will be deleted when pSuperLib is deleted in Map_SuperLibFree() if ( Abc_FrameReadLibScl() && Abc_SclHasDelayInfo( Abc_FrameReadLibScl() ) ) { pLib = Abc_SclDeriveGenlib( Abc_FrameReadLibScl(), Slew, Gain, nGatesMin, fVerbose ); if ( Abc_FrameReadLibGen() ) Mio_LibraryTransferDelays( (Mio_Library_t *)Abc_FrameReadLibGen(), pLib ); // remove supergate library Map_SuperLibFree( (Map_SuperLib_t *)Abc_FrameReadLibSuper() ); Abc_FrameSetLibSuper( NULL ); } // quit if there is no library if ( pLib == NULL ) { printf( "The current library is not available.\n" ); return 0; } if ( AreaMulti != 0.0 ) fUseMulti = 1, printf( "The cell areas are multiplied by the factor: <num_fanins> ^ (%.2f).\n", AreaMulti ); if ( DelayMulti != 0.0 ) fUseMulti = 1, printf( "The cell delays are multiplied by the factor: <num_fanins> ^ (%.2f).\n", DelayMulti ); // penalize large gates by increasing their area if ( AreaMulti != 0.0 ) Mio_LibraryMultiArea( pLib, AreaMulti ); if ( DelayMulti != 0.0 ) Mio_LibraryMultiDelay( pLib, DelayMulti ); // derive the supergate library if ( fUseMulti || Abc_FrameReadLibSuper() == NULL ) { if ( fVerbose ) printf( "Converting \"%s\" into supergate library \"%s\".\n", Mio_LibraryReadName(pLib), Extra_FileNameGenericAppend(Mio_LibraryReadName(pLib), ".super") ); // compute supergate library to be used for mapping Map_SuperLibDeriveFromGenlib( pLib, fVerbose ); } // return the library to normal if ( AreaMulti != 0.0 ) Mio_LibraryMultiArea( (Mio_Library_t *)Abc_FrameReadLibGen(), -AreaMulti ); if ( DelayMulti != 0.0 ) Mio_LibraryMultiDelay( (Mio_Library_t *)Abc_FrameReadLibGen(), -DelayMulti ); // print a warning about choice nodes if ( fVerbose && Abc_NtkGetChoiceNum( pNtk ) ) printf( "Performing mapping with choices.\n" ); // compute switching activity fShowSwitching |= fSwitching; if ( fShowSwitching ) { extern Vec_Int_t * Sim_NtkComputeSwitching( Abc_Ntk_t * pNtk, int nPatterns ); vSwitching = Sim_NtkComputeSwitching( pNtk, 4096 ); pSwitching = (float *)vSwitching->pArray; } // perform the mapping pMan = Abc_NtkToMap( pNtk, DelayTarget, fRecovery, pSwitching, fVerbose ); if ( pSwitching ) Vec_IntFree( vSwitching ); if ( pMan == NULL ) return NULL; clk = Abc_Clock(); Map_ManSetSwitching( pMan, fSwitching ); Map_ManSetSkipFanout( pMan, fSkipFanout ); if ( LogFan != 0 ) Map_ManCreateNodeDelays( pMan, LogFan ); if ( !Map_Mapping( pMan ) ) { Map_ManFree( pMan ); return NULL; } // Map_ManPrintStatsToFile( pNtk->pSpec, Map_ManReadAreaFinal(pMan), Map_ManReadRequiredGlo(pMan), Abc_Clock()-clk ); // reconstruct the network after mapping pNtkNew = Abc_NtkFromMap( pMan, pNtk ); Map_ManFree( pMan ); if ( pNtkNew == NULL ) return NULL; if ( pNtk->pExdc ) pNtkNew->pExdc = Abc_NtkDup( pNtk->pExdc ); if ( fVerbose ) { ABC_PRT( "Total runtime", Abc_Clock() - clkTotal ); } // make sure that everything is okay if ( !Abc_NtkCheck( pNtkNew ) ) { printf( "Abc_NtkMap: The network check has failed.\n" ); Abc_NtkDelete( pNtkNew ); return NULL; } return pNtkNew; }
/**Function************************************************************* Synopsis [Write the network into file.] Description [] SideEffects [] SeeAlso [] ***********************************************************************/ void Io_Write( Abc_Ntk_t * pNtk, char * pFileName, Io_FileType_t FileType ) { Abc_Ntk_t * pNtkTemp, * pNtkCopy; // check if the current network is available if ( pNtk == NULL ) { fprintf( stdout, "Empty network.\n" ); return; } // check if the file extension if given if ( FileType == IO_FILE_NONE || FileType == IO_FILE_UNKNOWN ) { fprintf( stdout, "The generic file writer requires a known file extension.\n" ); return; } // write the AIG formats if ( FileType == IO_FILE_AIGER || FileType == IO_FILE_BAF ) { if ( !Abc_NtkIsStrash(pNtk) ) { fprintf( stdout, "Writing this format is only possible for structurally hashed AIGs.\n" ); return; } if ( FileType == IO_FILE_AIGER ) Io_WriteAiger( pNtk, pFileName, 1 ); else // if ( FileType == IO_FILE_BAF ) Io_WriteBaf( pNtk, pFileName ); return; } // write non-netlist types if ( FileType == IO_FILE_CNF ) { Io_WriteCnf( pNtk, pFileName, 0 ); return; } if ( FileType == IO_FILE_DOT ) { Io_WriteDot( pNtk, pFileName ); return; } if ( FileType == IO_FILE_GML ) { Io_WriteGml( pNtk, pFileName ); return; } /* if ( FileType == IO_FILE_BLIFMV ) { Io_WriteBlifMv( pNtk, pFileName ); return; } */ // convert logic network into netlist if ( FileType == IO_FILE_PLA ) { if ( Abc_NtkLevel(pNtk) > 1 ) { fprintf( stdout, "PLA writing is available for collapsed networks.\n" ); return; } if ( Abc_NtkIsComb(pNtk) ) pNtkTemp = Abc_NtkToNetlist( pNtk ); else { fprintf( stdout, "Latches are writen into the PLA file at PI/PO pairs.\n" ); pNtkCopy = Abc_NtkDup( pNtk ); Abc_NtkMakeComb( pNtkCopy ); pNtkTemp = Abc_NtkToNetlist( pNtk ); Abc_NtkDelete( pNtkCopy ); } if ( !Abc_NtkToSop( pNtk, 1 ) ) return; } else if ( FileType == IO_FILE_BENCH ) { if ( !Abc_NtkIsStrash(pNtk) ) { fprintf( stdout, "Writing traditional BENCH is available for AIGs only (use \"write_bench\").\n" ); return; } pNtkTemp = Abc_NtkToNetlistBench( pNtk ); } else pNtkTemp = Abc_NtkToNetlist( pNtk ); if ( pNtkTemp == NULL ) { fprintf( stdout, "Converting to netlist has failed.\n" ); return; } if ( FileType == IO_FILE_BLIF ) { if ( !Abc_NtkHasSop(pNtkTemp) && !Abc_NtkHasMapping(pNtkTemp) ) Abc_NtkToSop( pNtkTemp, 0 ); Io_WriteBlif( pNtkTemp, pFileName, 1 ); } else if ( FileType == IO_FILE_BLIFMV ) { if ( !Abc_NtkConvertToBlifMv( pNtkTemp ) ) return; Io_WriteBlifMv( pNtkTemp, pFileName ); } else if ( FileType == IO_FILE_BENCH ) Io_WriteBench( pNtkTemp, pFileName ); else if ( FileType == IO_FILE_PLA ) Io_WritePla( pNtkTemp, pFileName ); else if ( FileType == IO_FILE_EQN ) { if ( !Abc_NtkHasAig(pNtkTemp) ) Abc_NtkToAig( pNtkTemp ); Io_WriteEqn( pNtkTemp, pFileName ); } else if ( FileType == IO_FILE_VERILOG ) { if ( !Abc_NtkHasAig(pNtkTemp) && !Abc_NtkHasMapping(pNtkTemp) ) Abc_NtkToAig( pNtkTemp ); Io_WriteVerilog( pNtkTemp, pFileName ); } else fprintf( stderr, "Unknown file format.\n" ); Abc_NtkDelete( pNtkTemp ); }
/**Function************************************************************* Synopsis [Starts the record for the given network.] Description [] SideEffects [] SeeAlso [] ***********************************************************************/ void Abc_NtkRecStart( Abc_Ntk_t * pNtk, int nVars, int nCuts ) { Abc_ManRec_t * p; Abc_Obj_t * pObj, ** ppSpot; char Buffer[10]; unsigned * pTruth; int i, RetValue; int clkTotal = clock(), clk; assert( s_pMan == NULL ); if ( pNtk == NULL ) { assert( nVars > 2 && nVars <= 16 ); pNtk = Abc_NtkAlloc( ABC_NTK_STRASH, ABC_FUNC_AIG, 1 ); pNtk->pName = Extra_UtilStrsav( "record" ); } else { if ( Abc_NtkGetChoiceNum(pNtk) > 0 ) { printf( "The starting record should be a network without choice nodes.\n" ); return; } if ( Abc_NtkPiNum(pNtk) > 16 ) { printf( "The starting record should be a network with no more than %d primary inputs.\n", 16 ); return; } if ( Abc_NtkPiNum(pNtk) > nVars ) printf( "The starting record has %d inputs (warning only).\n", Abc_NtkPiNum(pNtk) ); pNtk = Abc_NtkDup( pNtk ); } // create the primary inputs for ( i = Abc_NtkPiNum(pNtk); i < nVars; i++ ) { pObj = Abc_NtkCreatePi( pNtk ); Buffer[0] = 'a' + i; Buffer[1] = 0; Abc_ObjAssignName( pObj, Buffer, NULL ); } Abc_NtkCleanCopy( pNtk ); Abc_NtkCleanEquiv( pNtk ); // start the manager p = ABC_ALLOC( Abc_ManRec_t, 1 ); memset( p, 0, sizeof(Abc_ManRec_t) ); p->pNtk = pNtk; p->nVars = Abc_NtkPiNum(pNtk); p->nWords = Kit_TruthWordNum( p->nVars ); p->nCuts = nCuts; p->nVarsInit = nVars; // create elementary truth tables p->vTtElems = Vec_PtrAlloc( 0 ); assert( p->vTtElems->pArray == NULL ); p->vTtElems->nSize = p->nVars; p->vTtElems->nCap = p->nVars; p->vTtElems->pArray = (void *)Extra_TruthElementary( p->nVars ); // allocate room for node truth tables if ( Abc_NtkObjNum(pNtk) > (1<<14) ) p->vTtNodes = Vec_PtrAllocSimInfo( 2 * Abc_NtkObjNum(pNtk), p->nWords ); else p->vTtNodes = Vec_PtrAllocSimInfo( 1<<14, p->nWords ); // create hash table p->nBins = 50011; p->pBins = ABC_ALLOC( Abc_Obj_t *, p->nBins ); memset( p->pBins, 0, sizeof(Abc_Obj_t *) * p->nBins ); // set elementary tables Kit_TruthFill( Vec_PtrEntry(p->vTtNodes, 0), p->nVars ); Abc_NtkForEachPi( pNtk, pObj, i ) Kit_TruthCopy( Vec_PtrEntry(p->vTtNodes, pObj->Id), Vec_PtrEntry(p->vTtElems, i), p->nVars ); // compute the tables clk = clock(); Abc_AigForEachAnd( pNtk, pObj, i ) { RetValue = Abc_NtkRecComputeTruth( pObj, p->vTtNodes, p->nVars ); assert( RetValue ); }