uint64_t Cache::access(MemReq& req) {
uint64_t respCycle = req.cycle;
bool skipAccess = cc->startAccess(req); //may need to skip access due to races (NOTE: may change req.type!)
if( skipAccess)
std::cout<<"skip access"<<std::endl;
if (likely(!skipAccess)) {
bool updateReplacement = (req.type == GETS) || (req.type == GETX);
int32_t lineId = array->lookup(req.lineAddr, &req, updateReplacement);
respCycle += accLat;
if (lineId == -1 && cc->shouldAllocate(req)) {
//Make space for new line
Address wbLineAddr;
lineId = array->preinsert(req.lineAddr, &req, &wbLineAddr); //find the lineId to replace
trace(Cache, "[%s] Evicting 0x%lx", name.c_str(), wbLineAddr);
//Evictions are not in the critical path in any sane implementation -- we do not include their delays
//NOTE: We might be "evicting" an invalid line for all we know. Coherence controllers will know what to do
cc->processEviction(req, wbLineAddr, lineId, respCycle); //1. if needed, send invalidates/downgrades to lower level
array->postinsert(req.lineAddr, &req, lineId); //do the actual insertion. NOTE: Now we must split insert into a 2-phase thing because cc unlocks us.
}
respCycle = cc->processAccess(req, lineId, respCycle);
}
cc->endAccess(req);
assert_msg(respCycle >= req.cycle, "[%s] resp < req? 0x%lx type %s childState %s, respCycle %ld reqCycle %ld",
name.c_str(), req.lineAddr, AccessTypeName(req.type), MESIStateName(*req.state), respCycle, req.cycle);
return respCycle;
}
int main(int argc, const char* argv[]) {
InitLog(""); //no log header
if (argc != 2) {
info("Prints an access trace");
info("Usage: %s <trace>", argv[0]);
exit(1);
}
gm_init(32<<20 /*32 MB, should be enough*/);
AccessTraceReader tr(argv[1]);
info("%12s %6s %6s %20s %10s", "Cycle", "Src", "Type", "LineAddr", "Latency");
while(!tr.empty()) {
AccessRecord acc = tr.read();
info("%12ld %6d %s %20p %10d", acc.reqCycle, acc.childId, AccessTypeName(acc.type), (uint64_t*)acc.lineAddr, acc.latency);
}
return 0;
}
uint64_t MESIBottomCC::processNonInclusiveWriteback(Address lineAddr, AccessType type, uint64_t cycle, MESIState* state, uint32_t srcId, uint32_t flags) {
if (!nonInclusiveHack) panic("Non-inclusive %s on line 0x%lx, this cache should be inclusive", AccessTypeName(type), lineAddr);
//info("Non-inclusive wback, forwarding");
MemReq req = {lineAddr, type, selfId, state, cycle, &ccLock, *state, srcId, flags | MemReq::NONINCLWB};
uint64_t respCycle = parents[getParentId(lineAddr)]->access(req);
return respCycle;
}
// TODO(dsm): This is copied verbatim from Cache. We should split Cache into different methods, then call those.
uint64_t TimingCache::access(MemReq& req) {
EventRecorder* evRec = zinfo->eventRecorders[req.srcId];
assert_msg(evRec, "TimingCache is not connected to TimingCore");
uint32_t initialRecords = evRec->numRecords();
bool hasWritebackRecord = false;
TimingRecord writebackRecord;
bool hasAccessRecord = false;
TimingRecord accessRecord;
uint64_t evDoneCycle = 0;
uint64_t respCycle = req.cycle;
bool skipAccess = cc->startAccess(req); //may need to skip access due to races (NOTE: may change req.type!)
if (likely(!skipAccess)) {
bool updateReplacement = (req.type == GETS) || (req.type == GETX);
int32_t lineId = array->lookup(req.lineAddr, &req, updateReplacement);
respCycle += accLat;
if (lineId == -1 /*&& cc->shouldAllocate(req)*/) {
assert(cc->shouldAllocate(req)); //dsm: for now, we don't deal with non-inclusion in TimingCache
//Make space for new line
Address wbLineAddr;
lineId = array->preinsert(req.lineAddr, &req, &wbLineAddr); //find the lineId to replace
trace(Cache, "[%s] Evicting 0x%lx", name.c_str(), wbLineAddr);
//Evictions are not in the critical path in any sane implementation -- we do not include their delays
//NOTE: We might be "evicting" an invalid line for all we know. Coherence controllers will know what to do
evDoneCycle = cc->processEviction(req, wbLineAddr, lineId, respCycle); //if needed, send invalidates/downgrades to lower level, and wb to upper level
array->postinsert(req.lineAddr, &req, lineId); //do the actual insertion. NOTE: Now we must split insert into a 2-phase thing because cc unlocks us.
if (evRec->numRecords() > initialRecords) {
assert_msg(evRec->numRecords() == initialRecords + 1, "evRec records on eviction %ld", evRec->numRecords());
writebackRecord = evRec->getRecord(initialRecords);
hasWritebackRecord = true;
evRec->popRecord();
}
}
uint64_t getDoneCycle = respCycle;
respCycle = cc->processAccess(req, lineId, respCycle, &getDoneCycle);
if (evRec->numRecords() > initialRecords) {
assert_msg(evRec->numRecords() == initialRecords + 1, "evRec records %ld", evRec->numRecords());
accessRecord = evRec->getRecord(initialRecords);
hasAccessRecord = true;
evRec->popRecord();
}
// At this point we have all the info we need to hammer out the timing record
TimingRecord tr = {req.lineAddr << lineBits, req.cycle, respCycle, req.type, NULL, NULL}; //note the end event is the response, not the wback
if (getDoneCycle - req.cycle == accLat) {
// Hit
assert(!hasWritebackRecord);
assert(!hasAccessRecord);
uint64_t hitLat = respCycle - req.cycle; // accLat + invLat
HitEvent* ev = new (evRec) HitEvent(this, hitLat, domain);
ev->setMinStartCycle(req.cycle);
tr.startEvent = tr.endEvent = ev;
} else {
assert_msg(getDoneCycle == respCycle, "gdc %ld rc %ld", getDoneCycle, respCycle);
// Miss events:
// MissStart (does high-prio lookup) -> getEvent || evictionEvent || replEvent (if needed) -> MissWriteback
MissStartEvent* mse = new (evRec) MissStartEvent(this, accLat, domain);
MissResponseEvent* mre = new (evRec) MissResponseEvent(this, mse, domain);
MissWritebackEvent* mwe = new (evRec) MissWritebackEvent(this, mse, accLat, domain);
mse->setMinStartCycle(req.cycle);
mre->setMinStartCycle(getDoneCycle);
mwe->setMinStartCycle(MAX(evDoneCycle, getDoneCycle));
// Tie two events to an optional timing record
// TODO: Promote to evRec if this is more generally useful
auto connect = [evRec](const TimingRecord* r, TimingEvent* startEv, TimingEvent* endEv, uint64_t startCycle, uint64_t endCycle) {
assert_msg(startCycle <= endCycle, "start > end? %ld %ld", startCycle, endCycle);
if (r) {
assert_msg(startCycle <= r->reqCycle, "%ld / %ld", startCycle, r->reqCycle);
assert_msg(r->respCycle <= endCycle, "%ld %ld %ld %ld", startCycle, r->reqCycle, r->respCycle, endCycle);
uint64_t upLat = r->reqCycle - startCycle;
uint64_t downLat = endCycle - r->respCycle;
if (upLat) {
DelayEvent* dUp = new (evRec) DelayEvent(upLat);
dUp->setMinStartCycle(startCycle);
startEv->addChild(dUp, evRec)->addChild(r->startEvent, evRec);
} else {
startEv->addChild(r->startEvent, evRec);
}
if (downLat) {
DelayEvent* dDown = new (evRec) DelayEvent(downLat);
dDown->setMinStartCycle(r->respCycle);
r->endEvent->addChild(dDown, evRec)->addChild(endEv, evRec);
} else {
r->endEvent->addChild(endEv, evRec);
}
} else {
if (startCycle == endCycle) {
startEv->addChild(endEv, evRec);
} else {
DelayEvent* dEv = new (evRec) DelayEvent(endCycle - startCycle);
dEv->setMinStartCycle(startCycle);
startEv->addChild(dEv, evRec)->addChild(endEv, evRec);
}
}
};
// Get path
connect(hasAccessRecord? &accessRecord : NULL, mse, mre, req.cycle + accLat, getDoneCycle);
mre->addChild(mwe, evRec);
// Eviction path
if (evDoneCycle) {
connect(hasWritebackRecord? &writebackRecord : NULL, mse, mwe, req.cycle + accLat, evDoneCycle);
}
// Replacement path
if (evDoneCycle && cands > ways) {
uint32_t replLookups = (cands + (ways-1))/ways - 1; // e.g., with 4 ways, 5-8 -> 1, 9-12 -> 2, etc.
assert(replLookups);
uint32_t fringeAccs = ways - 1;
uint32_t accsSoFar = 0;
TimingEvent* p = mse;
// Candidate lookup events
while (accsSoFar < replLookups) {
uint32_t preDelay = accsSoFar? 0 : tagLat;
uint32_t postDelay = tagLat - MIN(tagLat - 1, fringeAccs);
uint32_t accs = MIN(fringeAccs, replLookups - accsSoFar);
//info("ReplAccessEvent rl %d fa %d preD %d postD %d accs %d", replLookups, fringeAccs, preDelay, postDelay, accs);
ReplAccessEvent* raEv = new (evRec) ReplAccessEvent(this, accs, preDelay, postDelay, domain);
raEv->setMinStartCycle(req.cycle /*lax...*/);
accsSoFar += accs;
p->addChild(raEv, evRec);
p = raEv;
fringeAccs *= ways - 1;
}
// Swap events -- typically, one read and one write work for 1-2 swaps. Exact number depends on layout.
ReplAccessEvent* rdEv = new (evRec) ReplAccessEvent(this, 1, tagLat, tagLat, domain);
rdEv->setMinStartCycle(req.cycle /*lax...*/);
ReplAccessEvent* wrEv = new (evRec) ReplAccessEvent(this, 1, 0, 0, domain);
wrEv->setMinStartCycle(req.cycle /*lax...*/);
p->addChild(rdEv, evRec)->addChild(wrEv, evRec)->addChild(mwe, evRec);
}
tr.startEvent = mse;
tr.endEvent = mre; // note the end event is the response, not the wback
}
evRec->pushRecord(tr);
}
cc->endAccess(req);
assert_msg(respCycle >= req.cycle, "[%s] resp < req? 0x%lx type %s childState %s, respCycle %ld reqCycle %ld",
name.c_str(), req.lineAddr, AccessTypeName(req.type), MESIStateName(*req.state), respCycle, req.cycle);
return respCycle;
}
