/** * Main entry point for the AMD_S3LATE_RESTORE function. * * This entry point is responsible for restoring saved registers and preparing the * silicon components for OS restart. * * @param[in,out] S3LateParams Required input parameters for the AMD_S3LATE_RESTORE * entry point. * * @return Aggregated status across all internal AMD S3 late restore calls invoked. * */ AGESA_STATUS AmdS3LateRestore ( IN OUT AMD_S3LATE_PARAMS *S3LateParams ) { UINT8 *BufferPointer; VOID *OrMaskPtr; VOID *LateContextPtr; AGESA_STATUS ReturnStatus; AGESA_STATUS CalledStatus; AGESA_TESTPOINT (TpIfAmdS3LateRestoreEntry, &S3LateParams->StdHeader); IDS_HDT_CONSOLE (MAIN_FLOW, "AmdS3LateRestore: Start\n\n"); ReturnStatus = AGESA_SUCCESS; ASSERT (S3LateParams != NULL); BufferPointer = (UINT8 *) S3LateParams->S3DataBlock.VolatileStorage; S3LateParams->StdHeader.HeapBasePtr = &BufferPointer[((S3_VOLATILE_STORAGE_HEADER *) S3LateParams->S3DataBlock.VolatileStorage)->HeapOffset]; ASSERT (S3LateParams->StdHeader.HeapBasePtr != NULL); IDS_OPTION_HOOK (IDS_PLATFORMCFG_OVERRIDE, &S3LateParams->PlatformConfig, &S3LateParams->StdHeader); IDS_OPTION_HOOK (IDS_BEFORE_S3_RESTORE, S3LateParams, &(S3LateParams->StdHeader)); if (((S3_VOLATILE_STORAGE_HEADER *) S3LateParams->S3DataBlock.VolatileStorage)->RegisterDataSize != 0) { LateContextPtr = &BufferPointer[((S3_VOLATILE_STORAGE_HEADER *) S3LateParams->S3DataBlock.VolatileStorage)->RegisterDataOffset]; // Restore registers before exiting self refresh RestorePreESRContext (&OrMaskPtr, LateContextPtr, S3_LATE_RESTORE, &S3LateParams->StdHeader); // Restore registers after exiting self refresh RestorePostESRContext (OrMaskPtr, LateContextPtr, S3_LATE_RESTORE, &S3LateParams->StdHeader); } // Dispatch any features needing to run at this time point IDS_HDT_CONSOLE (CPU_TRACE, " Dispatch CPU features at S3 late restore end\n"); CalledStatus = DispatchCpuFeatures (CPU_FEAT_S3_LATE_RESTORE_END, &S3LateParams->PlatformConfig, &S3LateParams->StdHeader); if (CalledStatus > ReturnStatus) { ReturnStatus = CalledStatus; } CalledStatus = S3ScriptRestore (&S3LateParams->StdHeader); if (CalledStatus > ReturnStatus) { ReturnStatus = CalledStatus; } IDS_OPTION_HOOK (IDS_AFTER_S3_RESTORE, S3LateParams, &S3LateParams->StdHeader); AGESA_TESTPOINT (TpIfAmdS3LateRestoreExit, &S3LateParams->StdHeader); IDS_HDT_CONSOLE (MAIN_FLOW, "\nAmdS3LateRestore: End\n\n"); IDS_HDT_CONSOLE_S3_EXIT (&S3LateParams->StdHeader); return ReturnStatus; }
/** * Post Node id and other context info to AP cores via mailbox. * * @HtInterfaceMethod{::F_POST_MAP_TO_AP} * * Since Ap's can not view map until after mp communication is established, * provide them with initial context info via a mailbox register. A mailbox * register is one that can be written in PCI space and read in MSR space. * * @param[in] State Our state, access to socket, node maps */ VOID PostMapToAp ( IN STATE_DATA *State ) { UINT8 ModuleType; UINT8 Module; AP_MAILBOXES ApMailboxes; UINT8 Node; UINT32 Degree; AGESA_STATUS CalledStatus; // Dispatch any features (such as Preserve Mailbox) that need to run as soon as discovery is completed. IDS_HDT_CONSOLE (CPU_TRACE, " Dispatch CPU features after HT discovery\n"); CalledStatus = DispatchCpuFeatures (CPU_FEAT_AFTER_COHERENT_DISCOVERY, State->PlatformConfiguration, State->ConfigHandle); ASSERT (State->Fabric != NULL); Degree = 0; // Compute the degree of the system by finding the maximum degree of any node. for (Node = 0; Node < (State->NodesDiscovered + 1); Node++) { if (State->Fabric->SysDegree[Node] > Degree) { Degree = State->Fabric->SysDegree[Node]; } } // Post the information on all nodes. for (Node = 0; Node < (State->NodesDiscovered + 1); Node++) { ModuleType = 0; Module = 0; State->Nb->GetModuleInfo (Node, &ModuleType, &Module, State->Nb); ApMailboxes.ApMailInfo.Info = 0; ApMailboxes.ApMailInfo.Fields.Node = Node; ApMailboxes.ApMailInfo.Fields.Socket = State->HtInterface->GetSocketFromMap (Node, State); ApMailboxes.ApMailInfo.Fields.ModuleType = ModuleType; ApMailboxes.ApMailInfo.Fields.Module = Module; ApMailboxes.ApMailExtInfo.Info = 0; ApMailboxes.ApMailExtInfo.Fields.SystemDegree = Degree; // other fields of the extended info are used during ap init, and will be initialized at that time. State->Nb->PostMailbox (Node, ApMailboxes, State->Nb); } // Now that the mailboxes have been initialized, cache the info on the BSC. The APs // will cache during heap initialization. CacheApMailbox (State->ConfigHandle); }
/** * Main entry point for the AMD_INIT_MID function. * * This entry point is responsible for performing any necessary functions needed * after PCI bus enumeration and just before control is passed to the video option ROM. * * @param[in,out] MidParams Required input parameters for the AMD_INIT_MID * entry point. * * @return Aggregated status across all internal AMD mid calls invoked. * */ AGESA_STATUS AmdInitMid ( IN OUT AMD_MID_PARAMS *MidParams ) { AGESA_STATUS AgesaStatus; AGESA_STATUS CalledStatus; IDS_HDT_CONSOLE (MAIN_FLOW, "AmdInitMid: Start\n\n"); AGESA_TESTPOINT (TpIfAmdInitMidEntry, &MidParams->StdHeader); IDS_PERF_TIME_MEASURE (&MidParams->StdHeader); AgesaStatus = AGESA_SUCCESS; ASSERT (MidParams != NULL); IDS_OPTION_HOOK (IDS_INIT_MID_BEFORE, MidParams, &MidParams->StdHeader); IDS_HDT_CONSOLE (MAIN_FLOW, "DispatchCpuFeatures: MidStart\n"); CalledStatus = DispatchCpuFeatures (CPU_FEAT_INIT_MID_END, &MidParams->PlatformConfig, &MidParams->StdHeader); IDS_HDT_CONSOLE (MAIN_FLOW, "DispatchCpuFeatures: MidEnd\n"); if (CalledStatus > AgesaStatus) { AgesaStatus = CalledStatus; } CalledStatus = GnbInitAtMid (MidParams); if (CalledStatus > AgesaStatus) { AgesaStatus = CalledStatus; } IDS_OPTION_HOOK (IDS_INIT_MID_AFTER, MidParams, &MidParams->StdHeader); IDS_PERF_TIME_MEASURE (&MidParams->StdHeader); AGESA_TESTPOINT (TpIfAmdInitMidExit, &MidParams->StdHeader); IDS_HDT_CONSOLE (MAIN_FLOW, "\nAmdInitMid: End\n\n"); IDS_HDT_CONSOLE_FLUSH_BUFFER (&MidParams->StdHeader); return AgesaStatus; }
/** * Main entry point for the AMD_INIT_LATE function. * * This entry point is responsible for creating any desired ACPI tables, providing * information for DMI, and to prepare the processors for the operating system * bootstrap load process. * * @param[in,out] LateParams Required input parameters for the AMD_INIT_LATE * entry point. * * @return Aggregated status across all internal AMD late calls invoked. * */ AGESA_STATUS AmdInitLate ( IN OUT AMD_LATE_PARAMS *LateParams ) { AGESA_STATUS AgesaStatus; AGESA_STATUS AmdInitLateStatus; IDS_HDT_CONSOLE (MAIN_FLOW, "AmdInitLate: Start\n\n"); AGESA_TESTPOINT (TpIfAmdInitLateEntry, &LateParams->StdHeader); IDS_PERF_TIME_MEASURE (&LateParams->StdHeader); ASSERT (LateParams != NULL); AmdInitLateStatus = AGESA_SUCCESS; IDS_OPTION_HOOK (IDS_INIT_LATE_BEFORE, LateParams, &LateParams->StdHeader); IDS_HDT_CONSOLE (MAIN_FLOW, "CreatSystemTable: Start\n"); // _PSS, XPSS, _PCT, _PSD, _PPC, _CST, _CSD Tables if ((LateParams->PlatformConfig.UserOptionPState) || (IsFeatureEnabled (IoCstate, &LateParams->PlatformConfig, &LateParams->StdHeader))) { AgesaStatus = ((*(OptionPstateLateConfiguration.SsdtFeature)) (&LateParams->StdHeader, &LateParams->PlatformConfig, &LateParams->AcpiPState)); if (AgesaStatus > AmdInitLateStatus) { AmdInitLateStatus = AgesaStatus; } } // SRAT Table Generation if (LateParams->PlatformConfig.UserOptionSrat) { AgesaStatus = CreateAcpiSrat (&LateParams->StdHeader, &LateParams->AcpiSrat); if (AgesaStatus > AmdInitLateStatus) { AmdInitLateStatus = AgesaStatus; } } // SLIT Table Generation if (LateParams->PlatformConfig.UserOptionSlit) { AgesaStatus = CreateAcpiSlit (&LateParams->StdHeader, &LateParams->PlatformConfig, &LateParams->AcpiSlit); if (AgesaStatus > AmdInitLateStatus) { AmdInitLateStatus = AgesaStatus; } } // WHEA Table Generation if (LateParams->PlatformConfig.UserOptionWhea) { AgesaStatus = CreateAcpiWhea (&LateParams->StdHeader, &LateParams->AcpiWheaMce, &LateParams->AcpiWheaCmc); if (AgesaStatus > AmdInitLateStatus) { AmdInitLateStatus = AgesaStatus; } } // DMI Table Generation if (LateParams->PlatformConfig.UserOptionDmi) { AgesaStatus = CreateDmiRecords (&LateParams->StdHeader, &LateParams->DmiTable); if (AgesaStatus > AmdInitLateStatus) { AmdInitLateStatus = AgesaStatus; } } IDS_HDT_CONSOLE (MAIN_FLOW, "CreatSystemTable: End\n"); // Cpu Features IDS_HDT_CONSOLE (MAIN_FLOW, "DispatchCpuFeatures: LateStart\n"); AgesaStatus = DispatchCpuFeatures (CPU_FEAT_INIT_LATE_END, &LateParams->PlatformConfig, &LateParams->StdHeader); IDS_HDT_CONSOLE (MAIN_FLOW, "DispatchCpuFeatures: LateEnd\n"); if (AgesaStatus > AmdInitLateStatus) { AmdInitLateStatus = AgesaStatus; } // It is the last function run by the AGESA CPU module and prepares the processor // for the operating system bootstrap load process. IDS_HDT_CONSOLE (MAIN_FLOW, "AmdCpuLate: Start\n"); AgesaStatus = AmdCpuLate (&LateParams->StdHeader); IDS_HDT_CONSOLE (MAIN_FLOW, "AmdCpuLate: End\n"); if (AgesaStatus > AmdInitLateStatus) { AmdInitLateStatus = AgesaStatus; } AgesaStatus = GnbInitAtLate (LateParams); if (AgesaStatus > AmdInitLateStatus) { AmdInitLateStatus = AgesaStatus; } IDS_OPTION_HOOK (IDS_INIT_LATE_AFTER, LateParams, &LateParams->StdHeader); IDS_OPTION_HOOK (IDS_BEFORE_OS, LateParams, &LateParams->StdHeader); IDS_PERF_TIME_MEASURE (&LateParams->StdHeader); AGESA_TESTPOINT (TpIfAmdInitLateExit, &LateParams->StdHeader); IDS_HDT_CONSOLE (MAIN_FLOW, "\nAmdInitLate: End\n\n"); AGESA_TESTPOINT (EndAgesaTps, &LateParams->StdHeader); //End Debug Print Service IDS_HDT_CONSOLE_EXIT (&LateParams->StdHeader); return AmdInitLateStatus; }
/** * Main entry point for the AMD_INIT_LATE function. * * This entry point is responsible for creating any desired ACPI tables, providing * information for DMI, and to prepare the processors for the operating system * bootstrap load process. * * @param[in,out] LateParams Required input parameters for the AMD_INIT_LATE * entry point. * * @return Aggregated status across all internal AMD late calls invoked. * */ AGESA_STATUS AmdInitLate ( IN OUT AMD_LATE_PARAMS *LateParams ) { AGESA_STATUS AgesaStatus; AGESA_STATUS AmdInitLateStatus; AGESA_TESTPOINT (TpIfAmdInitLateEntry, &LateParams->StdHeader); IDS_PERF_TIME_MEASURE (&LateParams->StdHeader); ASSERT (LateParams != NULL); AmdInitLateStatus = AGESA_SUCCESS; IDS_OPTION_HOOK (IDS_INIT_LATE_BEFORE, LateParams, &LateParams->StdHeader); // _PSS, XPSS, _PCT, _PSD, _PPC Tables if (LateParams->PlatformConfig.UserOptionPState) { AgesaStatus = CreateAcpiTables (&LateParams->StdHeader, &LateParams->PlatformConfig, &LateParams->AcpiPState); if (AgesaStatus > AmdInitLateStatus) { AmdInitLateStatus = AgesaStatus; } } // SRAT Table Generation if (LateParams->PlatformConfig.UserOptionSrat) { AgesaStatus = CreateAcpiSrat (&LateParams->StdHeader, &LateParams->AcpiSrat); if (AgesaStatus > AmdInitLateStatus) { AmdInitLateStatus = AgesaStatus; } } // SLIT Table Generation if (LateParams->PlatformConfig.UserOptionSlit) { AgesaStatus = CreateAcpiSlit (&LateParams->StdHeader, &LateParams->PlatformConfig, &LateParams->AcpiSlit); if (AgesaStatus > AmdInitLateStatus) { AmdInitLateStatus = AgesaStatus; } } // WHEA Table Generation if (LateParams->PlatformConfig.UserOptionWhea) { AgesaStatus = CreateAcpiWhea (&LateParams->StdHeader, &LateParams->AcpiWheaMce, &LateParams->AcpiWheaCmc); if (AgesaStatus > AmdInitLateStatus) { AmdInitLateStatus = AgesaStatus; } } // DMI Table Generation if (LateParams->PlatformConfig.UserOptionDmi) { AgesaStatus = CreateDmiRecords (&LateParams->StdHeader, &LateParams->DmiTable); if (AgesaStatus > AmdInitLateStatus) { AmdInitLateStatus = AgesaStatus; } } // Cpu Features AgesaStatus = DispatchCpuFeatures (CPU_FEAT_INIT_LATE_END, &LateParams->PlatformConfig, &LateParams->StdHeader); if (AgesaStatus > AmdInitLateStatus) { AmdInitLateStatus = AgesaStatus; } // It is the last function run by the AGESA CPU module and prepares the processor // for the operating system bootstrap load process. AgesaStatus = AmdCpuLate (&LateParams->StdHeader); if (AgesaStatus > AmdInitLateStatus) { AmdInitLateStatus = AgesaStatus; } IDS_OPTION_HOOK (IDS_INIT_LATE_AFTER, LateParams, &LateParams->StdHeader); IDS_OPTION_HOOK (IDS_BEFORE_OS, LateParams, &LateParams->StdHeader); IDS_PERF_TIME_MEASURE (&LateParams->StdHeader); AGESA_TESTPOINT (TpIfAmdInitLateExit, &LateParams->StdHeader); AGESA_TESTPOINT (EndAgesaTps, &LateParams->StdHeader); return AmdInitLateStatus; }
/** * Performs CPU related initialization at the early entry point * * This function performs a large list of initialization items. These items * include: * * -1 local APIC initialization * -2 MSR table initialization * -3 PCI table initialization * -4 HT Phy PCI table initialization * -5 microcode patch loading * -6 namestring determination/programming * -7 AP initialization * -8 power management initialization * -9 core leveling * * This routine must be run by all cores in the system. Please note that * all APs that enter will never exit. * * @param[in] StdHeader Config handle for library and services * @param[in] PlatformConfig Config handle for platform specific information * * @retval AGESA_SUCCESS * */ AGESA_STATUS AmdCpuEarly ( IN AMD_CONFIG_PARAMS *StdHeader, IN PLATFORM_CONFIGURATION *PlatformConfig ) { UINT8 WaitStatus; UINT8 i; UINT8 StartCore; UINT8 EndCore; UINT32 NodeNum; UINT32 PrimaryCore; UINT32 SocketNum; UINT32 ModuleNum; UINT32 HighCore; UINT32 ApHeapIndex; UINT32 CurrentPerformEarlyFlag; UINT32 TargetApicId; AP_WAIT_FOR_STATUS WaitForStatus; AGESA_STATUS Status; AGESA_STATUS CalledStatus; CPU_SPECIFIC_SERVICES *FamilySpecificServices; AMD_CPU_EARLY_PARAMS CpuEarlyParams; S_PERFORM_EARLY_INIT_ON_CORE *EarlyTableOnCore; Status = AGESA_SUCCESS; CalledStatus = AGESA_SUCCESS; AmdCpuEarlyInitializer (StdHeader, PlatformConfig, &CpuEarlyParams); IDS_OPTION_HOOK (IDS_CPU_Early_Override, &CpuEarlyParams, StdHeader); GetCpuServicesOfCurrentCore ((CONST CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader); EarlyTableOnCore = NULL; FamilySpecificServices->GetEarlyInitOnCoreTable (FamilySpecificServices, (CONST S_PERFORM_EARLY_INIT_ON_CORE **)&EarlyTableOnCore, &CpuEarlyParams, StdHeader); if (EarlyTableOnCore != NULL) { GetPerformEarlyFlag (&CurrentPerformEarlyFlag, StdHeader); for (i = 0; EarlyTableOnCore[i].PerformEarlyInitOnCore != NULL; i++) { if ((EarlyTableOnCore[i].PerformEarlyInitFlag & CurrentPerformEarlyFlag) != 0) { IDS_HDT_CONSOLE (CPU_TRACE, " Perform core init step %d\n", i); EarlyTableOnCore[i].PerformEarlyInitOnCore (FamilySpecificServices, &CpuEarlyParams, StdHeader); } } } // B S P C O D E T O I N I T I A L I Z E A Ps // ------------------------------------------------------- // ------------------------------------------------------- // IMPORTANT: Here we determine if we are BSP or AP if (IsBsp (StdHeader, &CalledStatus)) { // Even though the bsc does not need to send itself a heap index, this sequence performs other important initialization. // Use '0' as a dummy heap index value. GetSocketModuleOfNode (0, &SocketNum, &ModuleNum, StdHeader); GetCpuServicesOfSocket (SocketNum, (CONST CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader); FamilySpecificServices->SetApCoreNumber (FamilySpecificServices, SocketNum, ModuleNum, 0, StdHeader); FamilySpecificServices->TransferApCoreNumber (FamilySpecificServices, StdHeader); // Clear BSP's Status Byte ApUtilWriteControlByte (CORE_ACTIVE, StdHeader); NodeNum = 0; ApHeapIndex = 1; while (NodeNum < MAX_NODES && GetSocketModuleOfNode (NodeNum, &SocketNum, &ModuleNum, StdHeader)) { GetCpuServicesOfSocket (SocketNum, (CONST CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader); GetGivenModuleCoreRange (SocketNum, ModuleNum, &PrimaryCore, &HighCore, StdHeader); if (NodeNum == 0) { StartCore = (UINT8) PrimaryCore + 1; } else { StartCore = (UINT8) PrimaryCore; } EndCore = (UINT8) HighCore; for (i = StartCore; i <= EndCore; i++) { FamilySpecificServices->SetApCoreNumber (FamilySpecificServices, SocketNum, ModuleNum, ApHeapIndex, StdHeader); IDS_HDT_CONSOLE (CPU_TRACE, " Launch socket %d core %d\n", SocketNum, i); if (FamilySpecificServices->LaunchApCore (FamilySpecificServices, SocketNum, ModuleNum, i, PrimaryCore, StdHeader)) { IDS_HDT_CONSOLE (CPU_TRACE, " Waiting for socket %d core %d\n", SocketNum, i); GetLocalApicIdForCore (SocketNum, i, &TargetApicId, StdHeader); WaitStatus = CORE_IDLE; WaitForStatus.Status = &WaitStatus; WaitForStatus.NumberOfElements = 1; WaitForStatus.RetryCount = WAIT_INFINITELY; WaitForStatus.WaitForStatusFlags = WAIT_STATUS_EQUALITY; ApUtilWaitForCoreStatus (TargetApicId, &WaitForStatus, StdHeader); ApHeapIndex++; } } NodeNum++; } // B S P P h a s e - 1 E N D IDS_OPTION_HOOK (IDS_BEFORE_PM_INIT, &CpuEarlyParams, StdHeader); AGESA_TESTPOINT (TpProcCpuBeforePMFeatureInit, StdHeader); IDS_HDT_CONSOLE (CPU_TRACE, " Dispatch CPU features before early power mgmt init\n"); CalledStatus = DispatchCpuFeatures (CPU_FEAT_BEFORE_PM_INIT, PlatformConfig, StdHeader); if (CalledStatus > Status) { Status = CalledStatus; } AGESA_TESTPOINT (TpProcCpuPowerMgmtInit, StdHeader); CalledStatus = PmInitializationAtEarly (&CpuEarlyParams, StdHeader); if (CalledStatus > Status) { Status = CalledStatus; } AGESA_TESTPOINT (TpProcCpuEarlyFeatureInit, StdHeader); IDS_HDT_CONSOLE (CPU_TRACE, " Dispatch CPU features after early power mgmt init\n"); CalledStatus = DispatchCpuFeatures (CPU_FEAT_AFTER_PM_INIT, PlatformConfig, StdHeader); IDS_OPTION_HOOK (IDS_BEFORE_AP_EARLY_HALT, &CpuEarlyParams, StdHeader); // Sleep all APs IDS_HDT_CONSOLE (CPU_TRACE, " Halting all APs\n"); ApUtilWriteControlByte (CORE_IDLE_HLT, StdHeader); } else { ApEntry (StdHeader, &CpuEarlyParams); } if (CalledStatus > Status) { Status = CalledStatus; } return (Status); }