int setup(void) {
// Optimize system timings
SYSTEMConfig(SYSCLK, SYS_CFG_WAIT_STATES | SYS_CFG_PCACHE);
// Setup interrupts
//INTConfigureSystem(INT_SYSTEM_CONFIG_MULT_VECTOR);
//INTEnableInterrupts();
// Setup LEDs, these pins need to be outputs
TRISEbits.TRISE0 = 0;
TRISEbits.TRISE1 = 0;
TRISEbits.TRISE2 = 0;
TRISEbits.TRISE3 = 0;
// Set all analog pins to be digital I/O
AD1PCFG = 0xFFFF;
//Configure SPI
SpiChnOpen(1, SPI_CON_MSTEN | SPICON_CKE | SPI_CON_MODE8 | SPI_CON_ON, 200);
PORTSetPinsDigitalIn(IOPORT_E, BIT_4);
//PORTSetPinsDigitalIn(IOPORT_D, BIT_10);
//PORTSetPinsDigitalIn(IOPORT_D, BIT_0);
//PORTSetPinsDigitalIn(IOPORT_C, BIT_4);
int rData = SPI1BUF; //Clears receive buffer
IFS0CLR = 0x03800000; //Clears any existing event (rx / tx/ fault interrupt)
SPI1STATCLR = 0x40; //Clears overflow
ad7466_cs = 1; //Make sure CS pin is high
YLED = 1; //1 is off, 0 is on
RLED = 1;
WLED = 1;
GLED = 1;
setupSerial();
SendDataBuffer("Radiometer Configuration Complete.\n\r", sizeof("Radiometer Configuration Complete.\n\r"));
return 0;
}
void setup()
{
ANSELBbits.ANSB0 = 0; // sets pin RB0 as digital
TRISBbits.TRISB0 = 0; // configure pin RB as an output
PPSOutput(2, RPB5, SDO1); // map SDO1 to RA1
//#define config1 SPI_MODE16_ON | SPI_CKE_ON | MASTER_ENABLE_ON
// /* FRAME_ENABLE_OFF
// * ENABLE_SDO_PIN -> SPI Output pin enabled
// * SPI_MODE16_ON -> 16-bit SPI mode
// * SPI_SMP_OFF -> Sample at middle of data output time
// * SPI_CKE_ON -> Output data changes on transition from active clock
// * to idle clock state
// * SLAVE_ENABLE_OFF -> Manual SW control of SS
// * MASTER_ENABLE_ON -> Master mode enable
// */
//#define config2 SPI_ENABLE
// /* SPI_ENABLE -> Enable SPI module
// */
//// OpenSPI2(config1, config2);
// // see pg 193 in plib reference
#define spi_channel 1
// Use channel 2 since channel 1 is used by TFT display
#define spi_brg 0
// Divider = 2 * (spi_brg + 1)
// Divide by 2 to get SPI clock of FPBDIV/2 -> max SPI clock
// SpiChnSetBrg(spi_channel, spi_brg);
// see pg 203 in plib reference
//////
//////
#define spi_divider 6
/* Unlike OpenSPIx(), config for SpiChnOpen describes the non-default
* settings. eg for OpenSPI2(), use SPI_SMP_OFF (default) to sample
* at the middle of the data output, use SPI_SMP_ON to sample at end. For
* SpiChnOpen, using SPICON_SMP as a parameter will use the non-default
* SPI_SMP_ON setting.
*/
#define config SPI_OPEN_MSTEN | SPI_OPEN_MODE8 | SPI_OPEN_DISSDI | SPI_OPEN_CKE_REV
/* SPI_OPEN_MSTEN -> Master mode enable
* SPI_OPEN_MODE16 -> 16-bit SPI mode
* SPI_OPEN_DISSDI -> Disable SDI pin since PIC32 to DAC is a
* master-to-slave only communication
* SPI_OPEN_CKE_REV -> Output data changes on transition from active
* clock to idle clock state
*/
SpiChnOpen(spi_channel, config, spi_divider);
}
void setupSPIMaster()
{
//Clears receive buffer
int rData = SPI1BUF;
//Clears any existing event (rx / tx/ fault interrupt)
IFS0CLR = 0x03800000;
//Clears overflow
SPI1STATCLR = 0x40;
//Enables the SPI channel (channel, master mode enable | use 8 bit mode | turn on, clock divider)
// divide fpb by 1024, configure the I/O ports
SpiChnOpen(1, SPI_CON_MSTEN | SPI_CON_MODE8 | SPI_CON_ON, 1024);
}
int main(void)
{
// === config the uart, DMA, SPI ===========
PT_setup();
// == SPI ==
//enable SPI at 10 MHz clock to meet digital potentiometer specifications
SpiChnOpen(spiChn, SPI_OPEN_ON | SPI_OPEN_MODE16 | SPI_OPEN_MSTEN | SPI_OPEN_CKE_REV , spiClkDiv);
// === setup system wide interrupts ====================
INTEnableSystemMultiVectoredInt();
// === set up i/o port pin ===============================
//Port B bits, 3,7,8, and 9 are used to select digital output
//Port B bit 4 is used as chip select for treble digital potentiometer
//Port B bit 13 is used as a select signal for output effect selection multiplexer
//Additional functionality would use the TFT to display which output was being
//selected
mPORTBSetPinsDigitalOut(BIT_4 | BIT_3|BIT_7 | BIT_8 | BIT_9 |BIT_13); //Set port as output
//Port A Bits 0,2,and 3 are used to configure digital potentiometers (chip selects). Port A bit 4 is used
//for multiplexing whether to have input from Digital effector chip, distortion,
//or pure tonestack sound
mPORTASetPinsDigitalOut(BIT_0 | BIT_2 | BIT_3 | BIT_4);
// === now the threads ===================================
// init the threads
PT_INIT(&pt_cmd);
PT_INIT(&pt_time);
//==Digipot spi stuff
// SCK2 is pin 26
// SDO1 (MOSI) is in PPS output group 1, could be connected to RB5 which is pin 14
PPSOutput(2, RPB5, SDO1);
// control CS for DAC
//mPORTBSetPinsDigitalOut(BIT_4); //CS
mPORTBSetBits(BIT_4 | BIT_6);
//===
mPORTASetBits(BIT_0 | BIT_2 | BIT_3 | BIT_4); //CS pins active high
mPORTAClearBits(BIT_4);
mPORTBClearBits(BIT_13);
mPORTBSetBits(BIT_13);
// schedule the threads
while(1) {
//cmd used as command center for all effects
PT_SCHEDULE(protothread_cmd(&pt_cmd));
}
} // main
int16_t motor_command(int16_t command) {
unsigned int config = SPI_CON_MODE16 | SPI_CON_MSTEN | SPI_CON_CKE;
// the last number is the clock divider
SpiChnOpen(SPI_CHANNEL2, config, 256); //256 works // 4 doesn't //8 doesn't //16 doesn't //32 doesn't //64 doesn't //128 doesn't
MDBSS = 0;
waitabit(WAIT_TIME);
SpiChnPutC(2, command);
int16_t velocity = SpiChnGetC(2);
MDBSS = 1;
SpiChnClose(SPI_CHANNEL2);
return velocity;
}
BOOL ConfigSPIComms(void)
{
SpiChnClose(RPI_SPI_CHANNEL);
/* do I need to configure this? */
INTEnable(INT_SOURCE_SPI_RX(RPI_SPI_CHANNEL),INT_DISABLED);
INTEnable(INT_SOURCE_SPI_TX(RPI_SPI_CHANNEL),INT_DISABLED);
INTEnable(INT_SOURCE_SPI_ERROR(RPI_SPI_CHANNEL),INT_DISABLED);
INTEnable(INT_SOURCE_SPI(RPI_SPI_CHANNEL),INT_DISABLED);
SPI_DATA_IN_DIRECTION = TRIS_IN;
SPI_DATA_OUT_DIRECTION = TRIS_OUT;
SPI_CLOCK_IN_DIRECTION = TRIS_IN;
SPI_SELECT_IN_DIRECTION = TRIS_IN;
SPI.RXCount=0;
SPI.TXCount=0;
SPI.address=0;
SPI.command=TRISTHIS_SPI_NO_COMMAND;
SpiChnOpen(RPI_SPI_CHANNEL,
SPI_OPEN_SLVEN|SPI_OPEN_CKE_REV|SPI_OPEN_MODE8|SPI_OPEN_SSEN,
0);
//TODO: Not acting consistently? RPI needs to send -b 8 -H parameters to spidev
/* configure interrupts */
INTSetVectorPriority(INT_VECTOR_SPI(RPI_SPI_CHANNEL), INT_PRIORITY_LEVEL_3);
INTSetVectorSubPriority(INT_VECTOR_SPI(RPI_SPI_CHANNEL),
INT_SUB_PRIORITY_LEVEL_1);
INTClearFlag(INT_SOURCE_SPI_RX(RPI_SPI_CHANNEL));
INTEnable(INT_SOURCE_SPI_RX(RPI_SPI_CHANNEL),INT_ENABLED);
INTClearFlag(INT_SOURCE_SPI_TX(RPI_SPI_CHANNEL));
INTClearFlag(INT_SOURCE_SPI_ERROR(RPI_SPI_CHANNEL));
INTClearFlag(INT_SOURCE_SPI(RPI_SPI_CHANNEL));
//INTEnable(INT_SOURCE_SPI(RPI_SPI_CHANNEL),INT_ENABLED);
/* configure change notice, as I can't figure out any other way to */
/* trigger the beginning of the slave select with just the SPI peripheral */
/* buuut the change notice pins are not on the SS pins, so a white wire is*/
/* needed */
/* tie chip enable CE0 to pin20/RE5 CE1 */
SPI_SELECT_CN_DIRECTION=TRIS_IN;
CNCONbits.w=0;
CNCONSET=_CNCON_ON_MASK;
CNENbits.w=0;
CNENSET=_CNEN_CNEN7_MASK;
CNTemp=CE_PORT; /* read for change notice */
RPI_SPI_RX_OVERFLOW_CLEAR;
SPI1CONbits.STXISEL=0b01;
SPI.status.w=0;
INTClearFlag(INT_CN);
INTSetVectorPriority(INT_CHANGE_NOTICE_VECTOR, INT_PRIORITY_LEVEL_2);
INTSetVectorSubPriority(INT_CHANGE_NOTICE_VECTOR, INT_SUB_PRIORITY_LEVEL_1);
return TRUE;
}
/****************************************************************************
Function:
bool DRV_SPI_Initialize(SpiChannel chn, SpiOpenFlags oFlags, unsigned int fpbDiv)
Summary:
This function initializes the SPI channel and also sets the brg register.
Description:
This function initializes the SPI channel and also sets the brg register.
The SPI baudrate BR is given by: BR=Fpb/(2*(SPIBRG+1))
The input parametes fpbDiv specifies the Fpb divisor term (2*(SPIBRG+1)),
so the BRG is calculated as SPIBRG=fpbDiv/2-1.
Precondition:
None
Parameters:
chn - the channel to set
oFlags - a SpiOpenFlags or __SPIxCONbits_t structure that sets the module behavior
fpbDiv - Fpb divisor to extract the baud rate: BR=Fpb/fpbDiv.
Returns:
true if success
false otherwise
Remarks:
- The baud rate is always obtained by dividing the Fpb to an even number
between 2 and 1024.
- When selecting the number of bits per character, SPI_OPEN_MODE32 has the highest priority.
If SPI_OPEN_MODE32 is not set, then SPI_OPEN_MODE16 selects the character width.
- The SPI_OPEN_SSEN is taken into account even in master mode. If it is set the library
will properly se the SS pin as an digital output.
***************************************************************************/
bool DRV_SPI_Initialize(SpiChannel chn, SpiOpenFlags oFlags, unsigned int fpbDiv)
{
#if defined (__C32__)
SpiChnOpen(chn, oFlags, fpbDiv);
#elif defined (__C30__)
volatile uint16_t con1 = 0;
uint16_t con2 = 0;
uint16_t con3 = 0;
uint8_t i;
if((SYS_CLK_PeripheralClockGet()/fpbDiv) > 10000000ul)
{
SYS_ASSERT(false, "Requested SPI frequency is not supported!");
return false;
// the SPI clock is selected more than 10MHz.
// Select the frequency as per the data sheet of the particular 16bit device.
}
for(i = 0; i < SPI_CLK_TBL_ELEMENT_COUNT; i++)
{
if((SYS_CLK_PeripheralClockGet()/fpbDiv) <= SpiClkTbl[i].clock)
{
con1 = SpiClkTbl[i].scale;
break;
}
}
con1 |= oFlags;
con3 |= SPI_EN;
switch(chn)
{
case 1:
OpenSPI1(con1,con2,con3);
break;
case 2:
SPI2STAT &= 0x7FFF;
OpenSPI2(con1,con2,con3);
break;
default:
SYS_ASSERT(false, "Requested SPI channel is not supported!");
return false;
}
#endif
return true;
}
/*********************************************************************
* Function: void SpiInitDevice(SpiChannel, int, int, int)
*
* PreCondition: none
*
* Input: none
*
* Output: none
*
* Side Effects: none
*
* Overview: Initializes SPI Channels
*
*
*
* Note:
**********************************************************************/
void SpiInitDevice(SpiChannel chn, int isMaster, int frmEn, int frmMaster) {
SpiOpenFlags oFlags = SPI_OPEN_MODE16 | SPI_OPEN_SMP_END; // SPI open mode
if (isMaster) {
oFlags |= SPI_OPEN_MSTEN;
}
if (frmEn) {
oFlags |= SPI_OPEN_FRMEN;
if (!frmMaster) {
oFlags |= SPI_OPEN_FSP_IN;
}
}
SpiChnOpen(chn, oFlags, 2); // divide fpb by 4, configure the I/O ports. Not using SS in this example
}
// Initializes SPI communications
void SPIAccelInit() {
int garbage;
SpiChnOpen(SPI_CHANNEL4,
SPI_OPEN_MSTEN |
SPI_OPEN_CKP_HIGH |
SPI_OPEN_ENHBUF,
2);
SpiChnPutC(SPI_CHANNEL4, 0x80);
garbage = SpiChnGetC(SPI_CHANNEL4);
SPIAccelWriteToReg(0x2C, 0x0A);
SPIAccelWriteToReg(0x2D, 0x08);
}
// init the SPI port and initialize the LCD
void LcdInitialize(void) {
mInitLCDPins();
SpiChnOpen(SPI_CHANNEL2, SPI_OPEN_MSTEN|SPI_OPEN_MODE8|SPI_OPEN_ON, 4000000/2000000); // will open SPI2 and set clock to 4mhz
mRESET_Low();
mRESET_High();
mSCE_High();
LcdWrite(LCD_C, 0x21 ); // LCD Extended Commands.
LcdWrite(LCD_C, 185 ); // Set LCD Vop (Contrast).
LcdWrite(LCD_C, 0x04 ); // Set Temp coefficent.
LcdWrite(LCD_C, 0x14 ); // LCD bias mode 1:48.
LcdWrite(LCD_C, 0x0C ); // LCD in normal mode. 0x0d for inverse
LcdWrite(LCD_C, 0x20);
LcdWrite(LCD_C, 0x0C);
}
void SpiInitDevice(int chn, int isMaster, int frmEn, int frmMaster)
{
unsigned int config = SPI_CON_MODE8 | SPI_CON_SMP | SPI_CON_ON; // SPI configuration word
if (isMaster)
{
config |= SPI_CON_MSTEN;
}
if (frmEn)
{
config |= SPI_CON_FRMEN;
if (!frmMaster)
{
config |= SPI_CON_FRMSYNC;
}
}
SpiChnOpen(chn, config, 160); // divide fpb by 4, configure the I/O ports. Not using SS in this example
}
/**
* Initialize the PIC32MX to communicate with the UG-23832HSWEG04 OLED display through the SSD1306
* display controller.
*/
void OledHostInit(void)
{
// Open SPI2 as a master in 1-byte mode running at 10MHz.
// The peripheral bus is running at 10Mhz, and we want a 10MHz SPI bus clock.
int pbClkDiv = 20000000 / 10000000;
SpiChnOpen(SPI_CHANNEL2, SPI_OPEN_MSTEN | SPI_OPEN_CKP_HIGH | SPI_OPEN_MODE8, pbClkDiv);
// Set RF4-6 as digital outputs for controlling data/command selection, logic power, and display
// power. They're all initialized high beforehand, because that disables power.
PORTSetBits(IOPORT_F, OLED_DRIVER_CNTLR_POWER_BIT | OLED_DRIVER_OLED_POWER_BIT | OLED_DRIVER_MODE_BIT);
PORTSetPinsDigitalOut(OLED_DRIVER_MODE_PORT, OLED_DRIVER_MODE_BIT); // RF4 sets whether the next SPI byte is a data or command byte.
PORTSetPinsDigitalOut(OLED_DRIVER_CNTLR_POWER_PORT, OLED_DRIVER_CNTLR_POWER_BIT); // RF5 controls power to the SSD1306 display controller.
PORTSetPinsDigitalOut(OLED_DRIVER_OLED_POWER_PORT, OLED_DRIVER_OLED_POWER_BIT); // RF6 controls power to the UG-23832HSWEG04 OLED display.
// Set RG9 as a digital output, tied to the reset pin on the SG1306 controller, low => reset.
PORTSetBits(OLED_DRIVER_RESET_PORT, OLED_DRIVER_RESET_BIT);
PORTSetPinsDigitalOut(OLED_DRIVER_RESET_PORT, OLED_DRIVER_RESET_BIT);
}
void setupSPISlave()
{
TRISCbits.TRISC4 = 1;
TRISDbits.TRISD0 = 0;
TRISDbits.TRISD9 = 0;
TRISDbits.TRISD10 = 1;
//Clears config register
SPI1CON = 0;
//Clears receive buffer
int rData = SPI1BUF;
//Clears any existing event (rx / tx/ fault interrupt)
IFS0CLR = 0x03800000;
//Clears overflow
SPI1STATCLR = 0x40;
//Enables the SPI channel (channel, master mode enable | use 8 bit mode | turn on, clock divider)
// divide fpb by 1024, configure the I/O ports.
SpiChnOpen(1, SPI_CON_SLVEN | SPI_CON_MODE8 | SPI_CON_ON, 1024);
}
error_t spiInit(void)
{
//Configure ENC624J600 MDIX (RB3)
LATBCLR = _LATB_LATB3_MASK;
TRISBCLR = _TRISB_TRISB3_MASK;
//Configure ENC624J600 CS (RD14)
LATDSET = _LATD_LATD14_MASK;
TRISDCLR = _TRISD_TRISD14_MASK;
//Configure ENC624J600 SHDN (RD15)
LATDSET = _LATD_LATD15_MASK;
TRISDCLR = _TRISD_TRISD15_MASK;
//Configure SPI1
SpiChnOpen(1, SPI_CON_MSTEN | SPI_CON_MODE8 | SPI_CON_ON, 16);
//Successful processing
return NO_ERROR;
}
int main(void)
{
initPic32();
PORTSetPinsDigitalIn(IOPORT_A, BIT_0);
PORTSetPinsDigitalIn(IOPORT_A, BIT_1);
PORTSetPinsDigitalIn(IOPORT_B, BIT_14);
PPSInput(1, SS1, RPA0);
PPSInput(2, SDI1, RPA1);
#ifndef NO_SDO
PPSOutput(3, RPA2, SDO1);
#endif
SpiChnOpen(1, SPI_OPEN_MODE8|SPI_OPEN_SLVEN|SPI_OPEN_SSEN
#ifdef NO_SDO
|SPI_OPEN_DISSDO
#endif
, 2);
init();
uint8_t lastByteReceived = 0;
uint8_t cmd[8];
uint8_t length=0;
uint8_t toRead = 1;
while(1) {
if(SpiChnTxBuffEmpty(1))
SpiChnPutC(1, lastByteReceived);
lastByteReceived = 0;
while(!SpiChnDataRdy(1))
loop();
uint8_t byte = SpiChnGetC(1);
cmd[length++] = byte;
toRead--;
if(toRead==0)
toRead = commandReceived(cmd, length);
}
}
void glcd_init(void)
{
#if defined(GLCD_CONTROLLER_PCD8544)
/* Set up remappable outputs for PIC32, SPI: DO and SCK */
SpiChnOpen(SPI_CHANNEL2, SPI_CON_ON|SPI_CON_MSTEN, 4);
/* Set SS, DC and RST pins as output */
PORTSetPinsDigitalOut(LCD_CS_PORT, LCD_CS_PIN);
PORTSetPinsDigitalOut(LCD_DC_RESET_PORT, LCD_DC_PIN | LCD_RESET_PIN);
/* Deselect LCD */
GLCD_DESELECT();
/* Send reset pulse to LCD */
glcd_reset();
/* Initialise the display */
glcd_PCD8544_init();
#else
#error "Controller not supported"
#endif /* GLCD_CONTROLLER_* */
}
void setup_counters() {
//Init I/O
//D1 has been set to slave select in 7366.h
TRISDbits.TRISD1 = 0; //Output for SS3
TRISEbits.TRISE9 = 0; //Output for SS2
TRISEbits.TRISE6 = 0; //Output for SS1
ss_high(MOT); ss_high(MAG1); ss_high(MAG2); // start all slave selects on high
//SPI setup
int rData = SPI1BUF; //Clears receive buffer
IFS0CLR = 0x03800000; //Clears any existing event (rx / tx/ fault interrupt)
SPI1STATCLR = 0x40; //Clears overflow
//Enables the SPI channel (channel, master mode enable | use 8 bit mode | turn on, clock divider)
SpiChnOpen(SPICHN, SPI_CON_MSTEN | SPI_CON_MODE8 | SPI_CON_ON|SPI_CKE_ON, 128); // divide fpb by 128, configure the I/O ports.
//Init 7366R
enable_7366(MAG1,QUADRATURE_X4 | MODULO_N | DISABLE_INDX,NO_FLAGS);
enable_7366(MAG2,QUADRATURE_X4 | MODULO_N | DISABLE_INDX,NO_FLAGS);
enable_7366(MOT,QUADRATURE_X4 | MODULO_N | DISABLE_INDX,NO_FLAGS);
unsigned char writebuf[COUNTER_BYTES];
//Note that MSB should be in slot 0
writebuf[1] = 0x58;
writebuf[0] = 0x98;
//Sets up DTR to contain 0x9858 = 39,000 (ticks/rev)
write_7366(MAG1,DTR, writebuf);
write_7366(MAG2,DTR, writebuf);
write_7366(MOT,DTR, writebuf);
clear_reg_7366(MAG1,STR);
clear_reg_7366(MAG2,STR);
clear_reg_7366(MOT,STR);
clear_reg_7366(MAG1,CNTR);
clear_reg_7366(MAG2,CNTR);
clear_reg_7366(MOT,CNTR);
}
void MySPI_Init(void)
{
volatile int Debug;
// SpiChnOpen onfigures SPI Pins
// SPI_OPEN_MSTEN : Master Mode
// SPI_OPEN_CKE : Clock Edge Select bit - 1 = Serial output data changes on
// transition from active clock state to Idle clock state
// (cfr page 18 of PIC32 Family Ref. Manual Sect 23 SPI)
// SPI_OPEN_SMP : SPI Data Input Sample Phase bit
// 0 = Input data sampled at middle of data output time
// Set SPI Clock to 1MHz
SpiChnOpen(SPI_CHANNEL1A, SPI_OPEN_MSTEN | SPI_OPEN_CKE_REV | SPI_OPEN_MODE8, GetPeripheralClock()/(80ul));
/*
PIC32 SPI clock speed:
---------------------
Fsck = Fpb
------------------
2 * (SPIxBRG + 1)
Note that the maximum possible baud rate is
Fpb/2 (SPIXBRG = 0) and the minimum possible baud
rate is Fpb /1024.
WF_MAX_SPI_FREQ = (10000000ul) (10MHz)
SPIFLASH_MAX_SPI_FREQ = (16000000ul) (16MHz)
The SPI clock for Wifi Module is set locally
The SPI Clock speed is limited to 5MHz due to Cyclone limitations
*/
SPI1ABRG = (GetPeripheralClock()-1ul)/2ul/(5000000ul);
}
/**************************************************************************************************
Initialise the video components
***************************************************************************************************/
void initVideo(void) {
AutoLineWrap = 1;
// test if there is a monitor plugged into the VGA connector
CNPUASET = (1 << 4); // set a pullup on the video output pin
uSec(300); // allow it to settle
//vga = !PORTAbits.RA4; // the pin will be pulled low if the monitor is there
CNPUACLR = (1 << 4);
////////////////////////////
// setup SPI2 which is the video generator. the output of this module is a stream of bits which are the pixels in a horiz scan line
//if(vga)
PPSOutput(3, RPA4, SDO2); // B5 is the video out for VGA [color]]
//else
// PPSOutput(3, RPB2, SDO2); // B2 is the video out for composite
PPSInput(4, SS2, RPB9); // B9 is the framing input [horizontal synch]
#define P_VIDEO_SPI 2 // the SPI peripheral used for video
#define P_SPI_INPUT SPI2BUF // input buffer for the SPI peripheral
#define P_SPI_INTERRUPT _SPI2_TX_IRQ // interrupt used by the SPI peripheral when it needs more data
////////////////////////////
// the horizontal sync uses Timer 3 and Output Compare 3 to generate the pulse and interrupt level 7
PPSOutput(4, RPB14, OC3); // B14 is the horizontal sync output (ie, the output from OC3)
#define P_VID_OC_OPEN OpenOC3 // the function used to open the output compare
#define P_VID_OC_REG OC3R // the output compare register
////////////////////////////
// the vertical sync uses B13
TRISBCLR = (1<<13); // Vert sync output used by VGA
#define P_VERT_SET_HI LATBSET = (1 << 13) // set vert sync hi
#define P_VERT_SET_LO LATBCLR = (1 << 13) // set vert sync lo
// calculate the paramaters for each video mode and setup Timer 3 to generate the horiz synch and interrupt on its leading edge
//if(vga) {
// set up for VGA output
HRes = VGA_HRES; // HRes is the number of horiz pixels to use
HBuf = VGA_HBUFF * 32; // HBuf is the horiz buffer size (in pixels)
ConfigBuffers(Option[O_LINES24]); // setup the buffer pointers and VBuf, VRes
VC[0] = VGA_VSYNC_N; // setup the table used to count lines
VC[1] = VGA_POSTEQ_N;
P_VID_OC_OPEN(OC_ON | OC_TIMER3_SRC | OC_CONTINUE_PULSE, 0, VGA_HSYNC_T); // enable the output compare which is used to time the width of the horiz sync pulse
OpenTimer3( T3_ON | T3_PS_1_1 | T3_SOURCE_INT, VGA_LINE_T-1); // enable timer 3 and set to the horizontal scanning frequency
//}
/*else if(Option[O_PAL]) {
// this is for the PAL composite output and is the same as VGA with timing differences
VBuf = VRes = PAL_VRES;
HRes = PAL_HRES;
HBuf = PAL_HBUFF * 32; // HBuf is the horiz buffer size (in pixels)
ConfigBuffers(0);
SvSyncT = PAL_LINE_T - C_HSYNC_T;
VC[0] = C_VSYNC_N;
VC[1] = PAL_POSTEQ_N;
VC[2] = PAL_VRES;
VC[3] = PAL_PREEQ_N;
P_VID_OC_OPEN(OC_ON | OC_TIMER3_SRC | OC_CONTINUE_PULSE, 0, C_HSYNC_T); // enable the output compare which is used to time the width of the horiz sync pulse
OpenTimer3(T3_ON | T3_PS_1_1 | T3_SOURCE_INT, PAL_LINE_T-1); // enable timer 3 and set to the horizontal scanning frequency
}
*/
/*
else {
// this is for the NTSC composite output and is similar again
VBuf = VRes = NTSC_VRES;
HRes = NTSC_HRES;
HBuf = NTSC_HBUFF * 32; // HBuf is the horiz buffer size (in pixels)
ConfigBuffers(0);
SvSyncT = NTSC_LINE_T - C_HSYNC_T;
VC[0] = C_VSYNC_N;
VC[1] = NTSC_POSTEQ_N;
VC[2] = NTSC_VRES;
VC[3] = NTSC_PREEQ_N;
P_VID_OC_OPEN(OC_ON | OC_TIMER3_SRC | OC_CONTINUE_PULSE, 0, C_HSYNC_T); // enable the output compare which is used to time the width of the horiz sync pulse
OpenTimer3(T3_ON | T3_PS_1_1 | T3_SOURCE_INT, NTSC_LINE_T-1); // enable timer 3 and set to the horizontal scanning frequency
}
*/
// set priority level 7 for the timer 3 interrupt (horiz synch) and enable it
mT3SetIntPriority(7);
mT3IntEnable(1);
// initialise the state machine and set the count so that the first interrupt will increment the state
VState = SV_PREEQ;
VCount = 1;
// setup the SPI channel then DMA channel which will copy the memory bitmap buffer to the SPI channel
//if(vga) {
// open the SPI in framing mode. Note that SPI_OPEN_DISSDI will disable the input (which we do not need)
SpiChnOpen(P_VIDEO_SPI, SPICON_ON | SPICON_MSTEN | SPICON_MODE32 | SPICON_FRMEN | SPICON_FRMSYNC | SPICON_FRMPOL | SPI_OPEN_DISSDI, VGA_PIX_T);
SPI2CON2 = (1<<9) | (1<<8); // instruct the SPI module to ignore any errors that might occur
DmaChnOpen(1, 1, DMA_OPEN_DEFAULT); // setup DMA 1 to send data to SPI channel 2
DmaChnSetEventControl(1, DMA_EV_START_IRQ_EN | DMA_EV_START_IRQ(P_SPI_INTERRUPT));
DmaChnSetTxfer(1, (void*)VideoBuf, (void *)&P_SPI_INPUT, HBuf/8, 4, 4);
//}
/*
else {
SpiChnOpen(P_VIDEO_SPI, SPICON_ON | SPICON_MSTEN | SPICON_MODE32 | SPICON_FRMEN | SPICON_FRMSYNC | SPICON_FRMPOL | SPI_OPEN_DISSDI, C_PIX_T);
SPI2CON2 = (1<<9) | (1<<8); // instruct the SPI module to ignore any errors that might occur
DmaChnOpen(1, 1, DMA_OPEN_DEFAULT); // setup DMA 1 is the blank padding at the start of a scan line
DmaChnSetEventControl(1, DMA_EV_START_IRQ_EN | DMA_EV_START_IRQ(P_SPI_INTERRUPT));
DmaChnSetTxfer(1, (void*)zero, (void *)&P_SPI_INPUT, C_BLANKPAD, 4, 4);
DmaChnOpen( 0, 0, DMA_OPEN_DEFAULT); // setup DMA 0 to pump the data from the graphics buffer to the SPI peripheral
DmaChnSetEventControl(0, DMA_EV_START_IRQ_EN | DMA_EV_START_IRQ(P_SPI_INTERRUPT));
DmaChnSetTxfer(0, (void*)VideoBuf, (void *)&P_SPI_INPUT, HBuf/8 + 6, 4, 4);
DmaChnSetControlFlags(0, DMA_CTL_CHAIN_EN | DMA_CTL_CHAIN_DIR); // chain DMA 0 so that it will start on completion of the DMA 1 transfer
}
*/
}
/* PmodDA2Init
**
** Synopsis:
** Initailzes the PmodDA2 and all the buffers needed for playback
**
** Input: SpiChannel chn - spi channel initialize
** uint32_t pbClock - peripheral bus clock in Hz
** uint32_t bitRate - bit rate desired in Hz
**
** Returns: none
**
** Errors: none
*/
void PmodDA2Init(SpiChannel chn,uint32_t pbClock,uint32_t bitRate)
{
SpiChnOpen(chn, SPI_OPEN_MSTEN | SPI_OPEN_SSEN | SPI_OPEN_MODE8 , pbClock/bitRate);
}