void spi_config_0_irq(void) { #ifdef CONFIG_SPI_DW_INTERRUPT_SINGLE_LINE IRQ_CONNECT(CONFIG_SPI_DW_PORT_0_IRQ, CONFIG_SPI_DW_PORT_0_PRI, spi_dw_isr, DEVICE_GET(spi_dw_port_0), SPI_DW_IRQ_FLAGS); irq_enable(CONFIG_SPI_DW_PORT_0_IRQ); _spi_int_unmask(SPI_DW_PORT_0_INT_MASK); #else /* SPI_DW_INTERRUPT_SEPARATED_LINES */ IRQ_CONNECT(CONFIG_SPI_DW_PORT_0_RX_IRQ, CONFIG_SPI_DW_PORT_0_PRI, spi_dw_isr, DEVICE_GET(spi_dw_port_0), SPI_DW_IRQ_FLAGS); IRQ_CONNECT(CONFIG_SPI_DW_PORT_0_TX_IRQ, CONFIG_SPI_DW_PORT_0_PRI, spi_dw_isr, DEVICE_GET(spi_dw_port_0), SPI_DW_IRQ_FLAGS); IRQ_CONNECT(CONFIG_SPI_DW_PORT_0_ERROR_IRQ, CONFIG_SPI_DW_PORT_0_PRI, spi_dw_isr, DEVICE_GET(spi_dw_port_0), SPI_DW_IRQ_FLAGS); irq_enable(CONFIG_SPI_DW_PORT_0_RX_IRQ); irq_enable(CONFIG_SPI_DW_PORT_0_TX_IRQ); irq_enable(CONFIG_SPI_DW_PORT_0_ERROR_IRQ); _spi_int_unmask(SPI_DW_PORT_0_RX_INT_MASK); _spi_int_unmask(SPI_DW_PORT_0_TX_INT_MASK); _spi_int_unmask(SPI_DW_PORT_0_ERROR_INT_MASK); #endif }
void spi_config_1_irq(void) { #ifdef CONFIG_SPI_DW_INTERRUPT_SINGLE_LINE IRQ_CONNECT(SPI_DW_PORT_1_IRQ, CONFIG_SPI_1_IRQ_PRI, spi_dw_isr, DEVICE_GET(spi_dw_port_1), SPI_DW_IRQ_FLAGS); irq_enable(SPI_DW_PORT_1_IRQ); _spi_int_unmask(SPI_DW_PORT_1_INT_MASK); #else /* SPI_DW_INTERRUPT_SEPARATED_LINES */ IRQ_CONNECT(IRQ_SPI1_RX_AVAIL, CONFIG_SPI_1_IRQ_PRI, spi_dw_isr, DEVICE_GET(spi_dw_port_1), SPI_DW_IRQ_FLAGS); IRQ_CONNECT(IRQ_SPI1_TX_REQ, CONFIG_SPI_1_IRQ_PRI, spi_dw_isr, DEVICE_GET(spi_dw_port_1), SPI_DW_IRQ_FLAGS); IRQ_CONNECT(IRQ_SPI1_ERR_INT, CONFIG_SPI_1_IRQ_PRI, spi_dw_isr, DEVICE_GET(spi_dw_port_1), SPI_DW_IRQ_FLAGS); irq_enable(IRQ_SPI1_RX_AVAIL); irq_enable(IRQ_SPI1_TX_REQ); irq_enable(IRQ_SPI1_ERR_INT); _spi_int_unmask(SPI_DW_PORT_1_RX_INT_MASK); _spi_int_unmask(SPI_DW_PORT_1_TX_INT_MASK); _spi_int_unmask(SPI_DW_PORT_1_ERROR_INT_MASK); #endif }
void spi_config_3_irq(void) { #ifdef CONFIG_SPI_DW_PORT_3_INTERRUPT_SINGLE_LINE IRQ_CONNECT(DT_SPI_3_IRQ, DT_SPI_3_IRQ_PRI, spi_dw_isr, DEVICE_GET(spi_dw_port_3), DT_SPI_DW_IRQ_FLAGS); irq_enable(DT_SPI_3_IRQ); _spi_int_unmask(SPI_DW_PORT_3_INT_MASK); #else IRQ_CONNECT(DT_SPI_3_IRQ_RX_AVAIL, DT_SPI_3_IRQ_RX_AVAIL_PRI, spi_dw_isr, DEVICE_GET(spi_dw_port_3), DT_SPI_DW_IRQ_FLAGS); IRQ_CONNECT(DT_SPI_3_IRQ_TX_REQ, DT_SPI_3_IRQ_TX_REQ_PRI, spi_dw_isr, DEVICE_GET(spi_dw_port_3), DT_SPI_DW_IRQ_FLAGS); IRQ_CONNECT(DT_SPI_3_IRQ_ERR_INT, DT_SPI_3_IRQ_ERR_INT_PRI, spi_dw_isr, DEVICE_GET(spi_dw_port_3), DT_SPI_DW_IRQ_FLAGS); irq_enable(DT_SPI_3_IRQ_RX_AVAIL); irq_enable(DT_SPI_3_IRQ_TX_REQ); irq_enable(DT_SPI_3_IRQ_ERR_INT); _spi_int_unmask(SPI_DW_PORT_3_RX_INT_MASK); _spi_int_unmask(SPI_DW_PORT_3_TX_INT_MASK); _spi_int_unmask(SPI_DW_PORT_3_ERROR_INT_MASK); #endif }