static void ddramc_init(void) { struct ddramc_register ddramc_reg; unsigned int reg; ddramc_reg_config(&ddramc_reg); pmc_sam9x5_enable_periph_clk(AT91C_ID_MPDDRC); pmc_enable_system_clock(AT91C_PMC_DDR); /* MPDDRC I/O Calibration Register */ reg = readl(AT91C_BASE_MPDDRC + MPDDRC_IO_CALIBR); reg &= ~AT91C_MPDDRC_RDIV; reg |= AT91C_MPDDRC_RDIV_DDR2_RZQ_50; reg &= ~AT91C_MPDDRC_TZQIO; reg |= AT91C_MPDDRC_TZQIO_(100); writel(reg, (AT91C_BASE_MPDDRC + MPDDRC_IO_CALIBR)); writel(AT91C_MPDDRC_RD_DATA_PATH_TWO_CYCLES, (AT91C_BASE_MPDDRC + MPDDRC_RD_DATA_PATH)); ddr3_sdram_initialize(AT91C_BASE_MPDDRC, AT91C_BASE_DDRCS, &ddramc_reg); ddramc_dump_regs(AT91C_BASE_MPDDRC); }
static void ddramc_init(void) { struct ddramc_register ddramc_reg; unsigned int reg; ddramc_reg_config(&ddramc_reg); /* enable ddr2 clock */ pmc_enable_periph_clock(AT91C_ID_MPDDRC); pmc_enable_system_clock(AT91C_PMC_DDR); /* configure Shift Sampling Point of Data */ #if defined(CONFIG_BUS_SPEED_148MHZ) reg = AT91C_MPDDRC_RD_DATA_PATH_NO_SHIFT; #elif defined(CONFIG_BUS_SPEED_200MHZ) reg = AT91C_MPDDRC_RD_DATA_PATH_TWO_CYCLES; #else reg = AT91C_MPDDRC_RD_DATA_PATH_ONE_CYCLES; #endif writel(reg, (AT91C_BASE_MPDDRC + MPDDRC_RD_DATA_PATH)); /* MPDDRC I/O Calibration Register */ reg = readl(AT91C_BASE_MPDDRC + MPDDRC_IO_CALIBR); reg &= ~AT91C_MPDDRC_RDIV; reg &= ~AT91C_MPDDRC_TZQIO; reg &= ~AT91C_MPDDRC_CALCODEP; reg &= ~AT91C_MPDDRC_CALCODEN; reg |= AT91C_MPDDRC_RDIV_DDR2_RZQ_50; #if defined(CONFIG_BUS_SPEED_148MHZ) reg |= AT91C_MPDDRC_TZQIO_4; /* @ 133 & 148 MHz */ #else reg |= AT91C_MPDDRC_TZQIO_5; /* @ 170 & 176 MHz */ #endif reg |= AT91C_MPDDRC_EN_CALIB; writel(reg, (AT91C_BASE_MPDDRC + MPDDRC_IO_CALIBR)); /* DDRAM2 Controller initialize */ ddram_initialize(AT91C_BASE_MPDDRC, AT91C_BASE_DDRCS, &ddramc_reg); ddramc_dump_regs(AT91C_BASE_MPDDRC); }
static void lpddr1_init(void) { struct ddramc_register ddramc_reg; unsigned int reg; lpddr1_reg_config(&ddramc_reg); pmc_sam9x5_enable_periph_clk(AT91C_ID_MPDDRC); pmc_enable_system_clock(AT91C_PMC_DDR); /* * Before starting the initialization sequence, the user must force * the DDR_DQ and DDR_DQS input buffers to always on by setting * the FDQIEN and FDQSIEN bits in the SFR_DDRCFG register. */ pmc_sam9x5_enable_periph_clk(AT91C_ID_SFR); reg = readl(AT91C_BASE_SFR + SFR_DDRCFG); reg |= AT91C_DDRCFG_FDQIEN; reg |= AT91C_DDRCFG_FDQSIEN; writel(reg, AT91C_BASE_SFR + SFR_DDRCFG); /* MPDDRC I/O Calibration Register */ reg = readl(AT91C_BASE_MPDDRC + MPDDRC_IO_CALIBR); reg &= ~AT91C_MPDDRC_RDIV; reg |= AT91C_MPDDRC_RDIV_DDR2_RZQ_50; reg &= ~AT91C_MPDDRC_TZQIO; reg |= AT91C_MPDDRC_TZQIO_(100); writel(reg, AT91C_BASE_MPDDRC + MPDDRC_IO_CALIBR); writel(AT91C_MPDDRC_RD_DATA_PATH_ONE_CYCLES, AT91C_BASE_MPDDRC + MPDDRC_RD_DATA_PATH); lpddr1_sdram_initialize(AT91C_BASE_MPDDRC, AT91C_BASE_DDRCS, &ddramc_reg); ddramc_dump_regs(AT91C_BASE_MPDDRC); }