コード例 #1
0
void hw_data_init(void)
{
	*prcm = &dra7xx_prcm;
	if (is_dra72x())
		*dplls_data = &dra72x_dplls;
	else if (is_dra76x())
		*dplls_data = &dra76x_dplls;
	else
		*dplls_data = &dra7xx_dplls;
	*ctrl = &dra7xx_ctrl;
}
コード例 #2
0
ファイル: evm.c プロジェクト: analogdevicesinc/u-boot-xlnx
int board_fit_config_name_match(const char *name)
{
	if (is_dra72x()) {
		if (board_is_dra71x_evm()) {
			if (!strcmp(name, "dra71-evm"))
				return 0;
		}else if(board_is_dra72x_revc_or_later()) {
			if (!strcmp(name, "dra72-evm-revc"))
				return 0;
		} else if (!strcmp(name, "dra72-evm")) {
			return 0;
		}
	} else if (is_dra76x() && !strcmp(name, "dra76-evm")) {
		return 0;
	} else if (!is_dra72x() && !is_dra76x() && !strcmp(name, "dra7-evm")) {
		return 0;
	}

	return -1;
}
コード例 #3
0
ファイル: evm.c プロジェクト: jiapei100/u-boot
/* VTT regulator enable */
static inline void vtt_regulator_enable(void)
{
	if (omap_hw_init_context() == OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL)
		return;

	/* Do not enable VTT for DRA722 or DRA76x */
	if (is_dra72x() || is_dra76x())
		return;

	/*
	 * EVM Rev G and later use gpio7_11 for DDR3 termination.
	 * This is safe enough to do on older revs.
	 */
	gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en");
	gpio_direction_output(GPIO_DDR_VTT_EN, 1);
}
コード例 #4
0
ファイル: evm.c プロジェクト: analogdevicesinc/u-boot-xlnx
int board_late_init(void)
{
#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
	char *name = "unknown";

	if (is_dra72x()) {
		if (board_is_dra72x_revc_or_later())
			name = "dra72x-revc";
		else if (board_is_dra71x_evm())
			name = "dra71x";
		else
			name = "dra72x";
	} else if (is_dra76x()) {
		name = "dra76x";
	} else {
		name = "dra7xx";
	}

	set_board_info_env(name);

	/*
	 * Default FIT boot on HS devices. Non FIT images are not allowed
	 * on HS devices.
	 */
	if (get_device_type() == HS_DEVICE)
		env_set("boot_fit", "1");

	omap_die_id_serial();
	omap_set_fastboot_vars();

	/*
	 * Hook the LDO1 regulator to EN pin. This applies only to LP8733
	 * Rest all regulators are hooked to EN Pin at reset.
	 */
	if (board_is_dra71x_evm())
		palmas_i2c_write_u8(LP873X_I2C_SLAVE_ADDR, 0x9, 0x7);
#endif
	return 0;
}
コード例 #5
0
ファイル: evm.c プロジェクト: jiapei100/u-boot
void recalibrate_iodelay(void)
{
	struct pad_conf_entry const *pads, *delta_pads = NULL;
	struct iodelay_cfg_entry const *iodelay;
	int npads, niodelays, delta_npads = 0;
	int ret;

	switch (omap_revision()) {
	case DRA722_ES1_0:
	case DRA722_ES2_0:
	case DRA722_ES2_1:
		pads = dra72x_core_padconf_array_common;
		npads = ARRAY_SIZE(dra72x_core_padconf_array_common);
		if (board_is_dra71x_evm()) {
			pads = dra71x_core_padconf_array;
			npads = ARRAY_SIZE(dra71x_core_padconf_array);
			iodelay = dra71_iodelay_cfg_array;
			niodelays = ARRAY_SIZE(dra71_iodelay_cfg_array);
		} else if (board_is_dra72x_revc_or_later()) {
			delta_pads = dra72x_rgmii_padconf_array_revc;
			delta_npads =
				ARRAY_SIZE(dra72x_rgmii_padconf_array_revc);
			iodelay = dra72_iodelay_cfg_array_revc;
			niodelays = ARRAY_SIZE(dra72_iodelay_cfg_array_revc);
		} else {
			delta_pads = dra72x_rgmii_padconf_array_revb;
			delta_npads =
				ARRAY_SIZE(dra72x_rgmii_padconf_array_revb);
			iodelay = dra72_iodelay_cfg_array_revb;
			niodelays = ARRAY_SIZE(dra72_iodelay_cfg_array_revb);
		}
		break;
	case DRA752_ES1_0:
	case DRA752_ES1_1:
		pads = dra74x_core_padconf_array;
		npads = ARRAY_SIZE(dra74x_core_padconf_array);
		iodelay = dra742_es1_1_iodelay_cfg_array;
		niodelays = ARRAY_SIZE(dra742_es1_1_iodelay_cfg_array);
		break;
	case DRA762_ACD_ES1_0:
	case DRA762_ES1_0:
		pads = dra76x_core_padconf_array;
		npads = ARRAY_SIZE(dra76x_core_padconf_array);
		iodelay = dra76x_es1_0_iodelay_cfg_array;
		niodelays = ARRAY_SIZE(dra76x_es1_0_iodelay_cfg_array);
		break;
	default:
	case DRA752_ES2_0:
	case DRA762_ABZ_ES1_0:
		pads = dra74x_core_padconf_array;
		npads = ARRAY_SIZE(dra74x_core_padconf_array);
		iodelay = dra742_es2_0_iodelay_cfg_array;
		niodelays = ARRAY_SIZE(dra742_es2_0_iodelay_cfg_array);
		/* Setup port1 and port2 for rgmii with 'no-id' mode */
		clrset_spare_register(1, 0, RGMII2_ID_MODE_N_MASK |
				      RGMII1_ID_MODE_N_MASK);
		break;
	}
	/* Setup I/O isolation */
	ret = __recalibrate_iodelay_start();
	if (ret)
		goto err;

	/* Do the muxing here */
	do_set_mux32((*ctrl)->control_padconf_core_base, pads, npads);

	/* Now do the weird minor deltas that should be safe */
	if (delta_npads)
		do_set_mux32((*ctrl)->control_padconf_core_base,
			     delta_pads, delta_npads);

	if (is_dra76x())
		/* Set mux for MCAN instead of DCAN1 */
		clrsetbits_le32((*ctrl)->control_core_control_spare_rw,
				MCAN_SEL_ALT_MASK, MCAN_SEL);

	/* Setup IOdelay configuration */
	ret = do_set_iodelay((*ctrl)->iodelay_config_base, iodelay, niodelays);
err:
	/* Closeup.. remove isolation */
	__recalibrate_iodelay_end(ret);
}