static void setup_iomux_uart(void)
{
/* UART1 RXD */
mxc_request_iomux(MX53_PIN_CSI0_D11, IOMUX_CONFIG_ALT2);
mxc_iomux_set_pad(MX53_PIN_CSI0_D11,
PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU |
PAD_CTL_ODE_OPENDRAIN_ENABLE);
mxc_iomux_set_input(MX53_UART1_IPP_UART_RXD_MUX_SELECT_INPUT, 0x1);
/* UART1 TXD */
mxc_request_iomux(MX53_PIN_CSI0_D10, IOMUX_CONFIG_ALT2);
mxc_iomux_set_pad(MX53_PIN_CSI0_D10,
PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU |
PAD_CTL_ODE_OPENDRAIN_ENABLE);
}
static void setup_iomux_i2c(void)
{
int pad;
mxc_request_iomux(MX35_PIN_I2C1_CLK, MUX_CONFIG_SION);
mxc_request_iomux(MX35_PIN_I2C1_DAT, MUX_CONFIG_SION);
pad = (PAD_CTL_HYS_SCHMITZ | PAD_CTL_PKE_ENABLE \
| PAD_CTL_PUE_PUD | PAD_CTL_ODE_OpenDrain);
mxc_iomux_set_pad(MX35_PIN_I2C1_CLK, pad);
mxc_iomux_set_pad(MX35_PIN_I2C1_DAT, pad);
mxc_request_iomux(MX35_PIN_TX3_RX2, MUX_CONFIG_ALT1);
mxc_request_iomux(MX35_PIN_TX2_RX3, MUX_CONFIG_ALT1);
mxc_iomux_set_pad(MX35_PIN_TX3_RX2, pad);
mxc_iomux_set_pad(MX35_PIN_TX2_RX3, pad);
}
/* workaround for ecspi chipselect pin may not keep correct level when idle */
void gpio_spi_chipselect_active(int cspi_mode, int status, int chipselect)
{
switch (cspi_mode) {
case 1:
switch (chipselect) {
case 0x1:
mxc_request_iomux(MX51_PIN_CSPI1_SS0,
IOMUX_CONFIG_ALT0);
mxc_iomux_set_pad(MX51_PIN_CSPI1_SS0,
PAD_CTL_HYS_ENABLE |
PAD_CTL_PKE_ENABLE |
PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
mxc_request_iomux(MX51_PIN_CSPI1_SS1,
IOMUX_CONFIG_GPIO);
mxc_set_gpio_direction(MX51_PIN_CSPI1_SS1, 0);
mxc_set_gpio_dataout(MX51_PIN_CSPI1_SS1, 2 & (~status));
break;
case 0x2:
mxc_request_iomux(MX51_PIN_CSPI1_SS1,
IOMUX_CONFIG_ALT0);
mxc_iomux_set_pad(MX51_PIN_CSPI1_SS1,
PAD_CTL_HYS_ENABLE |
PAD_CTL_PKE_ENABLE |
PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
mxc_request_iomux(MX51_PIN_CSPI1_SS0,
IOMUX_CONFIG_GPIO);
mxc_set_gpio_direction(MX51_PIN_CSPI1_SS0, 0);
mxc_set_gpio_dataout(MX51_PIN_CSPI1_SS0, 1 & (~status));
break;
default:
break;
}
break;
case 2:
break;
case 3:
break;
default:
break;
}
}
static int mxc_init_ch7024(void)
{
/* request gpio for phone jack detect */
mxc_request_iomux(MX31_PIN_BATT_LINE, OUTPUTCONFIG_GPIO,
INPUTCONFIG_GPIO);
mxc_iomux_set_pad(MX31_PIN_BATT_LINE, PAD_CTL_PKE_NONE);
mxc_set_gpio_direction(MX31_PIN_BATT_LINE, 1);
return 0;
}
void gpio_usbh1_setback_stp(void)
{
/* setback USBH1_STP to be function */
mxc_request_iomux(MX51_PIN_USBH1_STP, IOMUX_CONFIG_ALT0);
mxc_iomux_set_pad(MX51_PIN_USBH1_STP, PAD_CTL_SRE_FAST |
PAD_CTL_DRV_HIGH | PAD_CTL_ODE_OPENDRAIN_NONE |
PAD_CTL_PUE_KEEPER | PAD_CTL_PKE_ENABLE |
PAD_CTL_HYS_ENABLE | PAD_CTL_DDR_INPUT_CMOS |
PAD_CTL_DRV_VOT_LOW);
gpio_free(IOMUX_TO_GPIO(MX51_PIN_USBH1_STP));
}
static int __init mxc_init_touchscreen(void)
{
int pad_val;
mxc_request_iomux(MX37_PIN_AUD5_RXFS, IOMUX_CONFIG_GPIO);
pad_val = PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PU;
mxc_iomux_set_pad(MX37_PIN_AUD5_RXFS, pad_val);
mxc_set_gpio_direction(MX37_PIN_AUD5_RXFS, 1);
return 0;
}
static int mxc_init_ch7024(void)
{
/* request gpio for phone jack detect */
mxc_request_iomux(MX31_PIN_BATT_LINE, OUTPUTCONFIG_GPIO,
INPUTCONFIG_GPIO);
mxc_iomux_set_pad(MX31_PIN_BATT_LINE, PAD_CTL_PKE_NONE);
gpio_request(IOMUX_TO_GPIO(MX31_PIN_BATT_LINE), "batt_line");
gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_BATT_LINE));
return 0;
}
static void fiveway_set_gpio_pads(iomux_pin_name_t gpio)
{
unsigned int FIVEWAY_pad_enable = PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_PULL |
PAD_CTL_ODE_OPENDRAIN_NONE | PAD_CTL_DRV_HIGH;
if (mx50_board_is(BOARD_ID_TEQUILA))
FIVEWAY_pad_enable |= PAD_CTL_100K_PD;
mxc_iomux_set_pad(gpio, FIVEWAY_pad_enable);
}
void gpio_spdif_active(void)
{
#if 0
iomux_pad_config_t regval = 0;
regval =
PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH | PAD_CTL_PKE_ENABLE |
PAD_CTL_100K_PU;
mxc_iomux_set_pad(MX37_PIN_AUD3_BB_RXD, regval);
mxc_request_iomux(MX37_PIN_AUD3_BB_RXD, IOMUX_CONFIG_ALT1);
#endif
}
/*!
* This function activates DAM ports 5 to enable
* audio I/O.
*/
void gpio_activate_bt_audio_port(void)
{
unsigned int pad_val;
mxc_request_iomux(MX35_PIN_STXD5, MUX_CONFIG_FUNC);
mxc_request_iomux(MX35_PIN_SRXD5, MUX_CONFIG_FUNC);
mxc_request_iomux(MX35_PIN_SCK5, MUX_CONFIG_FUNC);
mxc_request_iomux(MX35_PIN_STXFS5, MUX_CONFIG_FUNC);
pad_val = PAD_CTL_HYS_SCHMITZ | PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PU |
PAD_CTL_PUE_PUD;
mxc_iomux_set_pad(MX35_PIN_STXD5, pad_val);
mxc_iomux_set_pad(MX35_PIN_SRXD5, pad_val);
mxc_iomux_set_pad(MX35_PIN_SCK5, pad_val);
mxc_iomux_set_pad(MX35_PIN_STXFS5, pad_val);
if (board_is_mx35(BOARD_REV_2))
pmic_gpio_set_bit_val(MCU_GPIO_REG_GPIO_CONTROL_2, 5, 0);
else
pmic_gpio_set_bit_val(MCU_GPIO_REG_RESET_2, 0, 0);
}
static void setup_iomux_spi(void)
{
/* 000: Select mux mode: ALT0 mux port: MOSI of instance: ecspi1 */
mxc_request_iomux(MX51_PIN_CSPI1_MOSI, IOMUX_CONFIG_ALT0);
mxc_iomux_set_pad(MX51_PIN_CSPI1_MOSI, 0x105);
/* 000: Select mux mode: ALT0 mux port: MISO of instance: ecspi1. */
mxc_request_iomux(MX51_PIN_CSPI1_MISO, IOMUX_CONFIG_ALT0);
mxc_iomux_set_pad(MX51_PIN_CSPI1_MISO, 0x105);
/* de-select SS1 of instance: ecspi1. */
mxc_request_iomux(MX51_PIN_CSPI1_SS1, IOMUX_CONFIG_ALT3);
mxc_iomux_set_pad(MX51_PIN_CSPI1_SS1, 0x85);
/* 000: Select mux mode: ALT0 mux port: SS0 ecspi1 */
mxc_request_iomux(MX51_PIN_CSPI1_SS0, IOMUX_CONFIG_ALT0);
mxc_iomux_set_pad(MX51_PIN_CSPI1_SS0, 0x185);
/* 000: Select mux mode: ALT0 mux port: RDY of instance: ecspi1. */
mxc_request_iomux(MX51_PIN_CSPI1_RDY, IOMUX_CONFIG_ALT0);
mxc_iomux_set_pad(MX51_PIN_CSPI1_RDY, 0x180);
/* 000: Select mux mode: ALT0 mux port: SCLK of instance: ecspi1. */
mxc_request_iomux(MX51_PIN_CSPI1_SCLK, IOMUX_CONFIG_ALT0);
mxc_iomux_set_pad(MX51_PIN_CSPI1_SCLK, 0x105);
}
/*!
* Setup GPIO for an I2C device to be active
*
* @param i2c_num an I2C device
*/
void gpio_i2c_active(int i2c_num)
{
#define PAD_CONFIG (PAD_CTL_HYS_SCHMITZ | PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_PUD | PAD_CTL_ODE_OpenDrain)
switch (i2c_num) {
case 0:
mxc_request_iomux(MX35_PIN_I2C1_CLK, MUX_CONFIG_SION);
mxc_request_iomux(MX35_PIN_I2C1_DAT, MUX_CONFIG_SION);
mxc_iomux_set_pad(MX35_PIN_I2C1_CLK, PAD_CONFIG);
mxc_iomux_set_pad(MX35_PIN_I2C1_DAT, PAD_CONFIG);
break;
case 1:
mxc_request_iomux(MX35_PIN_I2C2_CLK, MUX_CONFIG_SION);
mxc_request_iomux(MX35_PIN_I2C2_DAT, MUX_CONFIG_SION);
mxc_iomux_set_pad(MX35_PIN_I2C2_CLK, PAD_CONFIG);
mxc_iomux_set_pad(MX35_PIN_I2C2_DAT, PAD_CONFIG);
break;
case 2:
mxc_request_iomux(MX35_PIN_TX3_RX2, MUX_CONFIG_ALT1);
mxc_request_iomux(MX35_PIN_TX2_RX3, MUX_CONFIG_ALT1);
mxc_iomux_set_pad(MX35_PIN_TX3_RX2, PAD_CONFIG);
mxc_iomux_set_pad(MX35_PIN_TX2_RX3, PAD_CONFIG);
break;
default:
break;
}
#undef PAD_CONFIG
}
void gpio_i2c_active(int i2c_num)
{
if (i2c_num == 0) {
mxc_request_iomux(MX50_PIN_I2C1_SCL, IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
mxc_iomux_set_pad(MX50_PIN_I2C1_SCL, PAD_CTL_HYS_ENABLE |
PAD_CTL_DRV_MAX | PAD_CTL_ODE_OPENDRAIN_ENABLE);
mxc_request_iomux(MX50_PIN_I2C1_SDA, IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
mxc_iomux_set_pad(MX50_PIN_I2C1_SDA, PAD_CTL_HYS_ENABLE |
PAD_CTL_DRV_MAX | PAD_CTL_ODE_OPENDRAIN_ENABLE);
}
if (i2c_num == 1) {
mxc_request_iomux(MX50_PIN_I2C2_SCL, IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
mxc_iomux_set_pad(MX50_PIN_I2C2_SCL, PAD_CTL_HYS_ENABLE |
PAD_CTL_DRV_MAX | PAD_CTL_ODE_OPENDRAIN_ENABLE);
mxc_request_iomux(MX50_PIN_I2C2_SDA, IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
mxc_iomux_set_pad(MX50_PIN_I2C2_SDA, PAD_CTL_HYS_ENABLE |
PAD_CTL_DRV_MAX | PAD_CTL_ODE_OPENDRAIN_ENABLE);
}
if (i2c_num == 2) {
mxc_request_iomux(MX50_PIN_I2C3_SCL, IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
mxc_iomux_set_pad(MX50_PIN_I2C3_SCL, PAD_CTL_HYS_ENABLE |
PAD_CTL_DRV_MAX | PAD_CTL_ODE_OPENDRAIN_ENABLE);
mxc_request_iomux(MX50_PIN_I2C3_SDA, IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
mxc_iomux_set_pad(MX50_PIN_I2C3_SDA, PAD_CTL_HYS_ENABLE |
PAD_CTL_DRV_MAX | PAD_CTL_ODE_OPENDRAIN_ENABLE);
}
}
static int devboard_usbh1_hw_init(struct platform_device *pdev)
{
mxc_iomux_set_gpr(MUX_PGP_USB_SUSPEND, true);
mxc_iomux_set_pad(MX31_PIN_CSPI1_MISO, USB_PAD_CFG);
mxc_iomux_set_pad(MX31_PIN_CSPI1_MOSI, USB_PAD_CFG);
mxc_iomux_set_pad(MX31_PIN_CSPI1_SS0, USB_PAD_CFG);
mxc_iomux_set_pad(MX31_PIN_CSPI1_SS1, USB_PAD_CFG);
mxc_iomux_set_pad(MX31_PIN_CSPI1_SS2, USB_PAD_CFG);
mxc_iomux_set_pad(MX31_PIN_CSPI1_SCLK, USB_PAD_CFG);
mxc_iomux_set_pad(MX31_PIN_CSPI1_SPI_RDY, USB_PAD_CFG);
mxc_iomux_set_pad(MX31_PIN_SFS6, USB_PAD_CFG);
return 0;
}
int board_mmc_init(bd_t *bis)
{
u32 index;
s32 status = 0;
for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM; index++) {
switch (index) {
case 0:
mxc_request_iomux(MX53_PIN_SD1_CMD, IOMUX_CONFIG_ALT0);
mxc_request_iomux(MX53_PIN_SD1_CLK, IOMUX_CONFIG_ALT0);
mxc_request_iomux(MX53_PIN_SD1_DATA0,
IOMUX_CONFIG_ALT0);
mxc_request_iomux(MX53_PIN_SD1_DATA1,
IOMUX_CONFIG_ALT0);
mxc_request_iomux(MX53_PIN_SD1_DATA2,
IOMUX_CONFIG_ALT0);
mxc_request_iomux(MX53_PIN_SD1_DATA3,
IOMUX_CONFIG_ALT0);
mxc_request_iomux(MX53_PIN_EIM_DA13,
IOMUX_CONFIG_ALT1);
mxc_iomux_set_pad(MX53_PIN_SD1_CMD,
PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU);
mxc_iomux_set_pad(MX53_PIN_SD1_CLK,
PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
PAD_CTL_DRV_HIGH);
mxc_iomux_set_pad(MX53_PIN_SD1_DATA0,
PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
mxc_iomux_set_pad(MX53_PIN_SD1_DATA1,
PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
mxc_iomux_set_pad(MX53_PIN_SD1_DATA2,
PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
mxc_iomux_set_pad(MX53_PIN_SD1_DATA3,
PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
break;
default:
printf("Warning: you configured more ESDHC controller"
"(%d) as supported by the board(1)\n",
CONFIG_SYS_FSL_ESDHC_NUM);
return status;
}
status |= fsl_esdhc_initialize(bis, &esdhc_cfg[index]);
}
return status;
}
/* Audio */
void gpio_audio_output(int enable)
{
#ifdef CONFIG_SND_MXC_SOC
if (!enable) {
/* Configure as GPIO, output and pull it low */
mxc_free_iomux(MX50_PIN_SSI_TXC, IOMUX_CONFIG_ALT0);
mxc_request_iomux(MX50_PIN_SSI_TXC, IOMUX_CONFIG_ALT1);
mxc_iomux_set_pad(MX50_PIN_SSI_TXC, PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
PAD_CTL_DRV_HIGH | PAD_CTL_ODE_OPENDRAIN_NONE);
gpio_request(IOMUX_TO_GPIO(MX50_PIN_SSI_TXC), "ssi_txc");
gpio_direction_output(IOMUX_TO_GPIO(MX50_PIN_SSI_TXC), 0);
gpio_set_value(IOMUX_TO_GPIO(MX50_PIN_SSI_TXC), 0);
/* ccm clko2 - gpio input */
mxc_free_iomux(MX50_PIN_SD1_CMD, IOMUX_CONFIG_ALT7);
mxc_request_iomux(MX50_PIN_SD1_CMD, IOMUX_CONFIG_ALT1);
gpio_request(IOMUX_TO_GPIO(MX50_PIN_SD1_CMD), "sd1_cmd");
gpio_direction_input(IOMUX_TO_GPIO(MX50_PIN_SD1_CMD));
} else {
/* Reconfigure as a function pin */
/* ccm clko2 - audio clock output */
gpio_free(IOMUX_TO_GPIO(MX50_PIN_SD1_CMD));
mxc_free_iomux(MX50_PIN_SD1_CMD, IOMUX_CONFIG_ALT1);
mxc_request_iomux(MX50_PIN_SD1_CMD, IOMUX_CONFIG_ALT7);
mxc_iomux_set_pad(MX50_PIN_SD1_CMD, PAD_CTL_PKE_ENABLE |
PAD_CTL_PUE_KEEPER |
PAD_CTL_DRV_MAX | PAD_CTL_ODE_OPENDRAIN_NONE |
PAD_CTL_SRE_FAST);
/* ssi_txc - audmux pin */
gpio_free(IOMUX_TO_GPIO(MX50_PIN_SSI_TXC));
mxc_free_iomux(MX50_PIN_SSI_TXC, IOMUX_CONFIG_ALT1);
mxc_request_iomux(MX50_PIN_SSI_TXC, IOMUX_CONFIG_ALT0);
mxc_iomux_set_pad(MX50_PIN_SSI_TXC, PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
PAD_CTL_DRV_HIGH | PAD_CTL_ODE_OPENDRAIN_NONE);
}
#endif
}
void gpio_i2c_active(int i2c_num)
{
if (i2c_num == 0) {
gpio_free(IOMUX_TO_GPIO(MX50_PIN_I2C1_SCL));
mxc_free_iomux(MX50_PIN_I2C1_SCL, IOMUX_CONFIG_ALT1);
gpio_free(IOMUX_TO_GPIO(MX50_PIN_I2C1_SDA));
mxc_free_iomux(MX50_PIN_I2C1_SDA, IOMUX_CONFIG_ALT1);
mxc_request_iomux(MX50_PIN_I2C1_SCL, IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
mxc_iomux_set_pad(MX50_PIN_I2C1_SCL, PAD_CTL_HYS_ENABLE |
PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_PULL |
PAD_CTL_DRV_HIGH | PAD_CTL_ODE_OPENDRAIN_ENABLE |
PAD_CTL_100K_PU);
mxc_request_iomux(MX50_PIN_I2C1_SDA, IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
mxc_iomux_set_pad(MX50_PIN_I2C1_SDA, PAD_CTL_DRV_MAX |
PAD_CTL_ODE_OPENDRAIN_ENABLE |
PAD_CTL_100K_PU);
}
if (i2c_num == 1) {
gpio_free(IOMUX_TO_GPIO(MX50_PIN_I2C2_SCL));
mxc_free_iomux(MX50_PIN_I2C2_SCL, IOMUX_CONFIG_ALT1);
gpio_free(IOMUX_TO_GPIO(MX50_PIN_I2C2_SDA));
mxc_free_iomux(MX50_PIN_I2C3_SDA, IOMUX_CONFIG_ALT1);
mxc_request_iomux(MX50_PIN_I2C2_SCL, IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
mxc_iomux_set_pad(MX50_PIN_I2C2_SCL, PAD_CTL_HYS_ENABLE |
PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_PULL |
PAD_CTL_DRV_HIGH | PAD_CTL_ODE_OPENDRAIN_ENABLE |
PAD_CTL_100K_PU);
mxc_request_iomux(MX50_PIN_I2C2_SDA, IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
mxc_iomux_set_pad(MX50_PIN_I2C2_SDA, PAD_CTL_DRV_MAX |
PAD_CTL_ODE_OPENDRAIN_ENABLE |
PAD_CTL_100K_PU);
}
}
static int fsl_usb_host_init_ext(struct platform_device *pdev)
{
iomux_v3_cfg_t usbh1stp_func = MX51_PAD_USBH1_STP__USBH1_STP;
int ret;
struct clk *usb_clk;
/* the usb_ahb_clk will be enabled in usb_otg_init */
usb_ahb_clk = clk_get(NULL, "usb_ahb_clk");
if (cpu_is_mx53()) {
usb_clk = clk_get(NULL, "usboh3_clk");
clk_enable(usb_clk);
usb_oh3_clk = usb_clk;
usb_clk = clk_get(NULL, "usb_phy2_clk");
clk_enable(usb_clk);
usb_phy2_clk = usb_clk;
} else if (cpu_is_mx50()) {
usb_clk = clk_get(NULL, "usb_phy2_clk");
clk_enable(usb_clk);
usb_phy2_clk = usb_clk;
} else if (cpu_is_mx51()) {
usb_clk = clk_get(NULL, "usboh3_clk");
clk_enable(usb_clk);
usb_oh3_clk = usb_clk;
}
ret = fsl_usb_host_init(pdev);
if (ret)
return ret;
if (cpu_is_mx51()) {
/* setback USBH1_STP to be function */
#if 0 /* Jasper: Need to do... */
mxc_request_iomux(MX51_PIN_USBH1_STP, IOMUX_CONFIG_ALT0);
mxc_iomux_set_pad(MX51_PIN_USBH1_STP, PAD_CTL_SRE_FAST |
PAD_CTL_DRV_HIGH | PAD_CTL_ODE_OPENDRAIN_NONE |
PAD_CTL_PUE_KEEPER | PAD_CTL_PKE_ENABLE |
PAD_CTL_HYS_ENABLE | PAD_CTL_DDR_INPUT_CMOS |
PAD_CTL_DRV_VOT_LOW);
gpio_free(IOMUX_TO_GPIO(MX51_PIN_USBH1_STP));
#endif
mxc_iomux_v3_setup_pad(usbh1stp_func);
gpio_free(MX5X_USBH1_STP);
}
/* disable remote wakeup irq */
USBCTRL &= ~UCTRL_H1WIE;
return 0;
}
static void setup_iomux_i2c(void)
{
/* I2C1 SDA */
mxc_request_iomux(MX53_PIN_CSI0_D8,
IOMUX_CONFIG_ALT5 | IOMUX_CONFIG_SION);
mxc_iomux_set_input(MX53_I2C1_IPP_SDA_IN_SELECT_INPUT,
INPUT_CTL_PATH0);
mxc_iomux_set_pad(MX53_PIN_CSI0_D8,
PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH |
PAD_CTL_100K_PU | PAD_CTL_PKE_ENABLE |
PAD_CTL_PUE_PULL |
PAD_CTL_ODE_OPENDRAIN_ENABLE);
/* I2C1 SCL */
mxc_request_iomux(MX53_PIN_CSI0_D9,
IOMUX_CONFIG_ALT5 | IOMUX_CONFIG_SION);
mxc_iomux_set_input(MX53_I2C1_IPP_SCL_IN_SELECT_INPUT,
INPUT_CTL_PATH0);
mxc_iomux_set_pad(MX53_PIN_CSI0_D9,
PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH |
PAD_CTL_100K_PU | PAD_CTL_PKE_ENABLE |
PAD_CTL_PUE_PULL |
PAD_CTL_ODE_OPENDRAIN_ENABLE);
}
static int devboard_usbh1_hw_init(struct platform_device *pdev)
{
mxc_iomux_set_gpr(MUX_PGP_USB_SUSPEND, true);
mxc_iomux_set_pad(MX31_PIN_CSPI1_MISO, USB_PAD_CFG);
mxc_iomux_set_pad(MX31_PIN_CSPI1_MOSI, USB_PAD_CFG);
mxc_iomux_set_pad(MX31_PIN_CSPI1_SS0, USB_PAD_CFG);
mxc_iomux_set_pad(MX31_PIN_CSPI1_SS1, USB_PAD_CFG);
mxc_iomux_set_pad(MX31_PIN_CSPI1_SS2, USB_PAD_CFG);
mxc_iomux_set_pad(MX31_PIN_CSPI1_SCLK, USB_PAD_CFG);
mxc_iomux_set_pad(MX31_PIN_CSPI1_SPI_RDY, USB_PAD_CFG);
mxc_iomux_set_pad(MX31_PIN_SFS6, USB_PAD_CFG);
mdelay(10);
return mx31_initialize_usb_hw(pdev->id, MXC_EHCI_POWER_PINS_ENABLED |
MXC_EHCI_INTERFACE_SINGLE_UNI);
}
/*!
* Setup GPIO for SDHC1 to be inactive
*
* @param module SDHC module number
*/
void gpio_sdhc_inactive(int module)
{
switch (module) {
case 0:
mxc_free_iomux(MX31_PIN_SD1_CLK, OUTPUTCONFIG_FUNC,
INPUTCONFIG_FUNC);
mxc_free_iomux(MX31_PIN_SD1_CMD, OUTPUTCONFIG_FUNC,
INPUTCONFIG_FUNC);
mxc_free_iomux(MX31_PIN_SD1_DATA0, OUTPUTCONFIG_FUNC,
INPUTCONFIG_FUNC);
mxc_free_iomux(MX31_PIN_SD1_DATA1, OUTPUTCONFIG_FUNC,
INPUTCONFIG_FUNC);
mxc_free_iomux(MX31_PIN_SD1_DATA2, OUTPUTCONFIG_FUNC,
INPUTCONFIG_FUNC);
mxc_free_iomux(MX31_PIN_SD1_DATA3, OUTPUTCONFIG_FUNC,
INPUTCONFIG_FUNC);
mxc_free_iomux(MX31_PIN_SIMPD0, OUTPUTCONFIG_GPIO,
INPUTCONFIG_GPIO);
mxc_iomux_set_pad(MX31_PIN_SD1_CLK,
(PAD_CTL_DRV_NORMAL | PAD_CTL_SRE_SLOW));
mxc_iomux_set_pad(MX31_PIN_SD1_CMD,
(PAD_CTL_DRV_NORMAL | PAD_CTL_SRE_SLOW));
mxc_iomux_set_pad(MX31_PIN_SD1_DATA0,
(PAD_CTL_DRV_NORMAL | PAD_CTL_SRE_SLOW));
mxc_iomux_set_pad(MX31_PIN_SD1_DATA1,
(PAD_CTL_DRV_NORMAL | PAD_CTL_SRE_SLOW));
mxc_iomux_set_pad(MX31_PIN_SD1_DATA2,
(PAD_CTL_DRV_NORMAL | PAD_CTL_SRE_SLOW));
mxc_iomux_set_pad(MX31_PIN_SD1_DATA3,
(PAD_CTL_DRV_NORMAL | PAD_CTL_SRE_SLOW));
break;
case 1:
/* TODO:what are the pins for SDHC2? */
mxc_free_iomux(MX31_PIN_PC_CD2_B, OUTPUTCONFIG_FUNC,
INPUTCONFIG_NONE);
mxc_free_iomux(MX31_PIN_PC_CD1_B, OUTPUTCONFIG_FUNC,
INPUTCONFIG_NONE);
mxc_free_iomux(MX31_PIN_PC_WAIT_B, OUTPUTCONFIG_FUNC,
INPUTCONFIG_NONE);
mxc_free_iomux(MX31_PIN_PC_READY, OUTPUTCONFIG_FUNC,
INPUTCONFIG_NONE);
mxc_free_iomux(MX31_PIN_PC_VS1, OUTPUTCONFIG_FUNC,
INPUTCONFIG_NONE);
mxc_free_iomux(MX31_PIN_PC_PWRON, OUTPUTCONFIG_FUNC,
INPUTCONFIG_NONE);
mxc_set_gpio_direction(MX31_PIN_DSR_DCE1, 0);
mxc_set_gpio_dataout(MX31_PIN_DSR_DCE1, 0);
break;
default:
break;
}
}
static inline void mxc_init_wm8350(void)
{
int i;
for (i = 0; i < ARRAY_SIZE(mxc_wm8350_devices); i++) {
if (platform_device_register(&mxc_wm8350_devices[i]) < 0)
dev_err(&mxc_wm8350_devices[i].dev,
"Unable to register WM8350 device\n");
}
/*set INT pin*/
mxc_request_iomux(MX37_PIN_GPIO1_4, IOMUX_CONFIG_ALT0);
mxc_iomux_set_pad(MX37_PIN_GPIO1_4, PAD_CTL_SRE_FAST |
PAD_CTL_DRV_HIGH | PAD_CTL_22K_PU |
PAD_CTL_ODE_OPENDRAIN_ENABLE | PAD_CTL_HYS_NONE |
PAD_CTL_DDR_INPUT_CMOS | PAD_CTL_DRV_VOT_LOW);
}
static void mxc_init_sgtl5000(void)
{
int err, pin;
struct clk *cko1, *parent;
unsigned long rate;
/* for board v1.1 do nothing */
if (!board_is_mx37(BOARD_REV_2))
return;
pin = MX37_PIN_AUD5_RXFS;
err = mxc_request_iomux(pin, IOMUX_CONFIG_GPIO);
if (err) {
sgtl5000_data.hp_irq = -1;
printk(KERN_ERR "Error: sgtl5000_init request gpio failed!\n");
return;
}
mxc_iomux_set_pad(pin, PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PU);
mxc_set_gpio_direction(pin, 1);
/* cko1 clock */
mxc_request_iomux(MX37_PIN_GPIO1_6, IOMUX_CONFIG_ALT2);
cko1 = clk_get(NULL, "cko1_clk");
if (IS_ERR(cko1))
return;
parent = clk_get(NULL, "ipg_perclk");
if (IS_ERR(parent))
return;
clk_set_parent(cko1, parent);
rate = clk_round_rate(cko1, 13000000);
if (rate < 8000000 || rate > 27000000) {
printk(KERN_ERR "Error: SGTL5000 mclk freq %d out of range!\n",
rate);
clk_put(parent);
clk_put(cko1);
return;
}
clk_set_rate(cko1, rate);
clk_enable(cko1);
sgtl5000_data.sysclk = rate;
platform_device_register(&mxc_sgtl5000_device);
}
static int fsl_usb_host_init_ext(struct platform_device *pdev)
{
int ret;
struct clk *usb_clk;
if (cpu_is_mx53()) {
usb_clk = clk_get(NULL, "usboh3_clk");
clk_enable(usb_clk);
clk_put(usb_clk);
usb_clk = clk_get(&pdev->dev, "usb_phy2_clk");
clk_enable(usb_clk);
clk_put(usb_clk);
/*derive clock from oscillator */
usb_clk = clk_get(NULL, "usb_utmi_clk");
clk_disable(usb_clk);
clk_put(usb_clk);
} else if (cpu_is_mx50()) {
usb_clk = clk_get(&pdev->dev, "usb_phy2_clk");
clk_enable(usb_clk);
clk_put(usb_clk);
}
ret = fsl_usb_host_init(pdev);
if (ret)
return ret;
if (cpu_is_mx51()) {
/* setback USBH1_STP to be function */
mxc_request_iomux(MX51_PIN_USBH1_STP, IOMUX_CONFIG_ALT0);
mxc_iomux_set_pad(MX51_PIN_USBH1_STP, PAD_CTL_SRE_FAST |
PAD_CTL_DRV_HIGH | PAD_CTL_ODE_OPENDRAIN_NONE |
PAD_CTL_PUE_KEEPER | PAD_CTL_PKE_ENABLE |
PAD_CTL_HYS_ENABLE | PAD_CTL_DDR_INPUT_CMOS |
PAD_CTL_DRV_VOT_LOW);
gpio_free(IOMUX_TO_GPIO(MX51_PIN_USBH1_STP));
}
/* disable remote wakeup irq */
USBCTRL &= ~UCTRL_H1WIE;
return 0;
}
/*
* Return the card detect pin.
*/
int sdhc_init_card_det(int id)
{
#if defined(GPIO_SDHC_ENABLE)
if (id == 0) {
int ret = 0;
mxc_request_iomux(MX37_PIN_UART1_CTS, IOMUX_CONFIG_ALT4);
mxc_iomux_set_pad(MX37_PIN_UART1_CTS, PAD_CTL_DRV_HIGH |
PAD_CTL_HYS_NONE | PAD_CTL_PKE_NONE | PAD_CTL_SRE_FAST);
mxc_set_gpio_direction(MX37_PIN_UART1_CTS, 1);
pr_info("[Henry/0206] SD detect pin initialized!!\n");
ret = IOMUX_TO_IRQ(MX37_PIN_UART1_CTS);
mxc_free_iomux(MX37_PIN_UART1_CTS, IOMUX_CONFIG_ALT4);
return ret;
} else { /* config the det pin for SDHC2 */
return 0;
}
#endif
}
/*!
* Power Key initialization.
*/
static int __init mxc_init_power_key(void)
{
/*Set power key as wakeup resource */
int irq, ret;
mxc_request_iomux(MX25_PIN_A25, MUX_CONFIG_ALT5);
mxc_iomux_set_pad(MX25_PIN_A25, PAD_CTL_DRV_NORMAL);
gpio_request(IOMUX_TO_GPIO(MX25_PIN_A25), NULL);
gpio_direction_input(IOMUX_TO_GPIO(MX25_PIN_A25));
irq = IOMUX_TO_IRQ(MX25_PIN_A25);
set_irq_type(irq, IRQF_TRIGGER_RISING);
ret = request_irq(irq, power_key_int, 0, "power_key", 0);
if (ret)
pr_info("register on-off key interrupt failed\n");
else
enable_irq_wake(irq);
return ret;
}
/*!
* This function activates DAM ports 4 & 5 to enable
* audio I/O.
*/
void gpio_activate_audio_ports(void)
{
//
// AUD5_WB_TXD AUD_DATA_OUT
// AUD5_WB_RXD AUD_DATA_IN
// AUD5_WB_CK AUD_BCLK
// AUD5_WB_FS AUD_LRCK
// GPIO1_6 AUD_MCLK
unsigned int pad_val;
#if 0
/* AUD4_TXD */
mxc_request_iomux(MX37_PIN_DISP1_DAT20, IOMUX_CONFIG_ALT5);
/* AUD4_RXD */
mxc_request_iomux(MX37_PIN_DISP1_DAT21, IOMUX_CONFIG_ALT5);
/* AUD4_TXC */
mxc_request_iomux(MX37_PIN_DISP1_DAT22, IOMUX_CONFIG_ALT5);
/* AUD4_TXFS */
mxc_request_iomux(MX37_PIN_DISP1_DAT23, IOMUX_CONFIG_ALT5);
#endif
pad_val = PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_PULL | PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST;
mxc_iomux_set_pad(MX37_PIN_AUD5_WB_CK, PAD_CTL_100K_PU | pad_val);
mxc_request_iomux(MX37_PIN_AUD5_WB_CK, IOMUX_CONFIG_ALT0);
mxc_iomux_set_pad(MX37_PIN_AUD5_WB_RXD, pad_val);
mxc_request_iomux(MX37_PIN_AUD5_WB_RXD, IOMUX_CONFIG_ALT0);
mxc_iomux_set_pad(MX37_PIN_AUD5_WB_TXD, pad_val);
mxc_request_iomux(MX37_PIN_AUD5_WB_TXD, IOMUX_CONFIG_ALT0);
mxc_iomux_set_pad(MX37_PIN_AUD5_WB_FS, PAD_CTL_100K_PU | pad_val);
mxc_request_iomux(MX37_PIN_AUD5_WB_FS, IOMUX_CONFIG_ALT0);
/* Enable hysteresis for AUD5_WB_CK, AUD5_WB_RXD, AUD5_WB_TXD, AUD5_WB_FS */
mxc_iomux_set_pad(MX37_PIN_GRP_H5, PAD_CTL_HYS_ENABLE);
/* CLKO */
mxc_request_iomux(MX37_PIN_GPIO1_6, IOMUX_CONFIG_ALT2);
/* Mute */
mxc_request_iomux(MX37_PIN_AUD3_BB_FS, IOMUX_CONFIG_ALT4);
mxc_set_gpio_direction(MX37_PIN_AUD3_BB_FS, 0); // Output
mxc_set_gpio_dataout(MX37_PIN_AUD3_BB_FS, 0); // Mute On
mxc_free_iomux(MX37_PIN_AUD3_BB_FS, IOMUX_CONFIG_ALT4);
/* EARPHONE_DET */
mxc_request_iomux(MX37_PIN_GPIO1_5, IOMUX_CONFIG_ALT0);
mxc_iomux_set_pad(MX37_PIN_GPIO1_5, PAD_CTL_HYS_ENABLE);
mxc_set_gpio_direction(MX37_PIN_GPIO1_5, 1); // Input
mxc_free_iomux(MX37_PIN_GPIO1_5, IOMUX_CONFIG_ALT0);
}
static int mxc_mmc1_init(struct device *dev,
irq_handler_t detect_irq, void *data)
{
int ret;
gpio_det = IOMUX_TO_GPIO(MX31_PIN_DCD_DCE1);
gpio_wp = IOMUX_TO_GPIO(MX31_PIN_GPIO1_6);
mxc_iomux_set_pad(MX31_PIN_SD1_DATA0,
MMC_PAD_CFG | PAD_CTL_PUE_PUD | PAD_CTL_100K_PU);
mxc_iomux_set_pad(MX31_PIN_SD1_DATA1,
MMC_PAD_CFG | PAD_CTL_PUE_PUD | PAD_CTL_100K_PU);
mxc_iomux_set_pad(MX31_PIN_SD1_DATA2,
MMC_PAD_CFG | PAD_CTL_PUE_PUD | PAD_CTL_100K_PU);
mxc_iomux_set_pad(MX31_PIN_SD1_DATA3,
MMC_PAD_CFG | PAD_CTL_PUE_PUD | PAD_CTL_100K_PU);
mxc_iomux_set_pad(MX31_PIN_SD1_CMD,
MMC_PAD_CFG | PAD_CTL_PUE_PUD | PAD_CTL_100K_PU);
mxc_iomux_set_pad(MX31_PIN_SD1_CLK, MMC_PAD_CFG);
ret = gpio_request(gpio_det, "MMC detect");
if (ret)
return ret;
ret = gpio_request(gpio_wp, "MMC w/p");
if (ret)
goto exit_free_det;
gpio_direction_input(gpio_det);
gpio_direction_input(gpio_wp);
ret = request_irq(gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_DCD_DCE1)),
detect_irq,
IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING,
"MMC detect", data);
if (ret)
goto exit_free_wp;
return 0;
exit_free_wp:
gpio_free(gpio_wp);
exit_free_det:
gpio_free(gpio_det);
return ret;
}
/*!
* Setup GPIO for SDHC1 to be inactive
*
* @param module SDHC module number
*/
void gpio_sdhc_inactive(int module)
{
#if defined(GPIO_SDHC_ENABLE)
switch (module) {
case 0:
mxc_free_iomux(MX37_PIN_SD1_CLK,
IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
mxc_free_iomux(MX37_PIN_SD1_CMD,
IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
mxc_free_iomux(MX37_PIN_SD1_DATA0, IOMUX_CONFIG_ALT0);
mxc_free_iomux(MX37_PIN_SD1_DATA1, IOMUX_CONFIG_ALT0);
mxc_free_iomux(MX37_PIN_SD1_DATA2, IOMUX_CONFIG_ALT0);
mxc_free_iomux(MX37_PIN_SD1_DATA3, IOMUX_CONFIG_ALT0);
mxc_iomux_set_pad(MX37_PIN_SD1_CLK,
(PAD_CTL_DRV_LOW | PAD_CTL_SRE_SLOW));
mxc_iomux_set_pad(MX37_PIN_SD1_CMD,
(PAD_CTL_DRV_LOW | PAD_CTL_SRE_SLOW));
mxc_iomux_set_pad(MX37_PIN_SD1_DATA0,
(PAD_CTL_DRV_LOW | PAD_CTL_SRE_SLOW));
mxc_iomux_set_pad(MX37_PIN_SD1_DATA1,
(PAD_CTL_DRV_LOW | PAD_CTL_SRE_SLOW));
mxc_iomux_set_pad(MX37_PIN_SD1_DATA2,
(PAD_CTL_DRV_LOW | PAD_CTL_SRE_SLOW));
mxc_iomux_set_pad(MX37_PIN_SD1_DATA3,
(PAD_CTL_DRV_LOW | PAD_CTL_SRE_SLOW));
#if 0
/* Free Write Protected Pin */
mxc_free_iomux(MX37_PIN_CSPI1_SS0,
IOMUX_CONFIG_SION | IOMUX_CONFIG_ALT4);
mxc_iomux_set_pad(MX37_PIN_CSPI1_SS0,
(PAD_CTL_DRV_LOW | PAD_CTL_SRE_SLOW));
#endif
break;
case 1:
/* TODO:what are the pins for SDHC2? */
break;
default:
break;
}
#endif
}
/*!
* Get irq for gpio pins
* @param pin GPIO pin name
* @param trigger_flag [out] The initial trigger flag.
* @return The irq associated with gpio pin.
*/
u32 get_gpio_irq(iomux_pin_name_t pin, unsigned long* trigger_flag)
{
int val;
mxc_request_iomux(pin, OUTPUTCONFIG_GPIO, INPUTCONFIG_GPIO);
if ((pin != MX31_PIN_DTR_DCE1) && (pin != MX31_PIN_KEY_ROW4))
mxc_iomux_set_pad(pin, PAD_CTL_PKE_NONE);
mxc_set_gpio_direction(pin, 1);
val = mxc_get_gpio_datain(pin);
if (val == 0)
{
// Now the gpio pin is in low electrical level, should be trigger by high
*trigger_flag = IRQF_TRIGGER_RISING;
}
else
{
// Now the gpio pin is in high electrical level, should be trigger by low
*trigger_flag = IRQF_TRIGGER_FALLING;
}
return IOMUX_TO_IRQ(pin);
}