/****************************************************************
* Name: Pci2000_QueueCommand
*
* Description: Process a queued command from the SCSI manager.
*
* Parameters: SCpnt - Pointer to SCSI command structure.
* done - Pointer to done function to call.
*
* Returns: Status code.
*
****************************************************************/
int Pci2000_QueueCommand (Scsi_Cmnd *SCpnt, void (*done)(Scsi_Cmnd *))
{
UCHAR *cdb = (UCHAR *)SCpnt->cmnd; // Pointer to SCSI CDB
PADAPTER2000 padapter = HOSTDATA(SCpnt->host); // Pointer to adapter control structure
int rc = -1; // command return code
UCHAR bus = SCpnt->channel;
UCHAR pun = SCpnt->target;
UCHAR lun = SCpnt->lun;
UCHAR cmd;
PDEV2000 pdev = &padapter->dev[bus][pun];
if ( !done )
{
printk("pci2000_queuecommand: %02X: done can't be NULL\n", *cdb);
return 0;
}
SCpnt->scsi_done = done;
SCpnt->SCp.have_data_in = 0;
pdev->SCpnt = SCpnt; // Save this command data
if ( WaitReady (padapter) )
{
rc = DID_ERROR;
goto finished;
}
outw_p (pun | (lun << 8), padapter->mb0);
if ( bus )
{
DEB (if(*cdb) printk ("\nCDB: %X- %X %X %X %X %X %X %X %X %X %X ", SCpnt->cmd_len, cdb[0], cdb[1], cdb[2], cdb[3], cdb[4], cdb[5], cdb[6], cdb[7], cdb[8], cdb[9]));
DEB (if(*cdb) printk ("\ntimeout_per_command: %d, timeout_total: %d, timeout: %d, internal_timout: %d", SCpnt->timeout_per_command,
SCpnt->timeout_total, SCpnt->timeout, SCpnt->internal_timeout));
outl (SCpnt->timeout_per_command, padapter->mb1);
outb_p (CMD_SCSI_TIMEOUT, padapter->cmd);
if ( WaitReady (padapter) )
{
rc = DID_ERROR;
goto finished;
}
outw_p (pun | (lun << 8), padapter->mb0);
outw_p (SCpnt->cmd_len << 8, padapter->mb0 + 2);
memcpy (pdev->cdb, cdb, MAX_COMMAND_SIZE);
outl (pdev->cdbDma, padapter->mb1);
if ( BuildSgList (SCpnt, padapter, pdev) )
cmd = CMD_SCSI_THRU;
else
cmd = CMD_SCSI_THRU_SG;
if ( (pdev->tag = Command (padapter, cmd)) == 0 )
rc = DID_TIME_OUT;
goto finished;
}
else
{
if ( lun )
static u16 sonypi_ecrget(u16 addr) {
wait_on_command(1, inw_p(SONYPI_CST_IOPORT) & 3);
outw_p(0x80, SONYPI_CST_IOPORT);
wait_on_command(0, inw_p(SONYPI_CST_IOPORT) & 2);
outw_p(addr, SONYPI_DATA_IOPORT);
wait_on_command(0, inw_p(SONYPI_CST_IOPORT) & 2);
return inw_p(SONYPI_DATA_IOPORT);
}
static void sonypi_ecrset(u16 addr, u16 value) {
wait_on_command(1, inw_p(SONYPI_CST_IOPORT) & 3);
outw_p(0x81, SONYPI_CST_IOPORT);
wait_on_command(0, inw_p(SONYPI_CST_IOPORT) & 2);
outw_p(addr, SONYPI_DATA_IOPORT);
wait_on_command(0, inw_p(SONYPI_CST_IOPORT) & 2);
outw_p(value, SONYPI_DATA_IOPORT);
wait_on_command(0, inw_p(SONYPI_CST_IOPORT) & 2);
}
static int nortel_pci_hw_init(struct nortel_pci_card *card)
{
int i;
u32 reg;
/* setup bridge */
if (inw(card->iobase1) & 1) {
printk(KERN_ERR PFX "brg1 answer1 wrong\n");
return -EBUSY;
}
outw_p(0x118, card->iobase1 + 2);
outw_p(0x108, card->iobase1 + 2);
mdelay(30);
outw_p(0x8, card->iobase1 + 2);
for (i = 0; i < 30; i++) {
mdelay(30);
if (inw(card->iobase1) & 0x10) {
break;
}
}
if (i == 30) {
printk(KERN_ERR PFX "brg1 timed out\n");
return -EBUSY;
}
if (inw(card->iobase2 + 0xe0) & 1) {
printk(KERN_ERR PFX "brg2 answer1 wrong\n");
return -EBUSY;
}
if (inw(card->iobase2 + 0xe2) & 1) {
printk(KERN_ERR PFX "brg2 answer2 wrong\n");
return -EBUSY;
}
if (inw(card->iobase2 + 0xe4) & 1) {
printk(KERN_ERR PFX "brg2 answer3 wrong\n");
return -EBUSY;
}
/* set the PCMCIA COR-Register */
outw_p(COR_VALUE, card->iobase2 + COR_OFFSET);
mdelay(1);
reg = inw(card->iobase2 + COR_OFFSET);
if (reg != COR_VALUE) {
printk(KERN_ERR PFX "Error setting COR value (reg=%x)\n",
reg);
return -EBUSY;
}
/* set leds */
outw_p(1, card->iobase1 + 10);
return 0;
}
static void mask_and_ack_cqreek(unsigned int irq)
{
unsigned short stat_port = cqreek_irq_data[irq].stat_port;
unsigned short bit = cqreek_irq_data[irq].bit;
disable_cqreek_irq(irq);
/* Clear IRQ (it might be edge IRQ) */
inw(stat_port);
outw_p(bit, stat_port);
}
static PyObject *
chwtest_outw(PyObject *self, PyObject *args)
{
unsigned long int address;
unsigned short int value;
if (!PyArg_ParseTuple(args, "lh", &address, &value)) {
return NULL;
}
outw_p(value, address);
Py_RETURN_NONE;
}
void write_pci_adc1602_8800( unsigned int base_status, unsigned char addr, unsigned char value )
{
int i;
/* write 3 bits MSB first of address, keep SEL8800 low */
for ( i = 0; i < 3; i++) {
if ( addr & 0x4 ) {
outw_p(CALEN | SDI, CALIBRATE_REG );
} else {
outw_p(CALEN | 0x0, CALIBRATE_REG );
}
udelay(10);
addr <<= 1;
}
/* write 8 bits MSB first of data, keep SEL8800 low */
for ( i = 0; i < 8; i++) {
if ( value & 0x80 ) {
outw_p(CALEN | SDI, CALIBRATE_REG );
} else {
outw_p(CALEN | 0x0, CALIBRATE_REG );
}
udelay(10);
value <<= 1;
}
/* SEL8800 to set load clock */
outw_p( SEL8800, CALIBRATE_REG );
udelay(10);
/* SEL8800 to reset load clock and update output */
outw_p( 0x0, CALIBRATE_REG );
}
static void enable_cqreek_irq(unsigned int irq)
{
unsigned long flags;
unsigned short mask;
unsigned short mask_port = cqreek_irq_data[irq].mask_port;
unsigned short bit = cqreek_irq_data[irq].bit;
local_irq_save(flags);
/* Enable IRQ */
mask = inw(mask_port) | bit;
outw_p(mask, mask_port);
local_irq_restore(flags);
}
static void disable_cqreek_irq(unsigned int irq)
{
unsigned long flags;
unsigned short mask;
unsigned short mask_port = cqreek_irq_data[irq].mask_port;
unsigned short bit = cqreek_irq_data[irq].bit;
save_and_cli(flags);
/* Disable IRQ */
mask = inw(mask_port) & ~bit;
outw_p(mask, mask_port);
restore_flags(flags);
}
static void __devexit nortel_pci_remove_one(struct pci_dev *pdev)
{
struct net_device *dev = pci_get_drvdata(pdev);
struct orinoco_private *priv = netdev_priv(dev);
struct nortel_pci_card *card = priv->card;
/* clear leds */
outw_p(0, card->iobase1 + 10);
unregister_netdev(dev);
free_irq(dev->irq, dev);
pci_set_drvdata(pdev, NULL);
free_orinocodev(dev);
pci_iounmap(pdev, priv->hw.iobase);
pci_release_regions(pdev);
pci_disable_device(pdev);
}
static int dyna_pci10xx_do_insn_bits(struct comedi_device *dev,
struct comedi_subdevice *s,
struct comedi_insn *insn,
unsigned int *data)
{
struct dyna_pci10xx_private *devpriv = dev->private;
mutex_lock(&devpriv->mutex);
if (comedi_dio_update_state(s, data)) {
smp_mb();
outw_p(s->state, devpriv->BADR3);
udelay(10);
}
data[1] = s->state;
mutex_unlock(&devpriv->mutex);
return insn->n;
}
/* analog output callback */
static int dyna_pci10xx_insn_write_ao(struct comedi_device *dev,
struct comedi_subdevice *s,
struct comedi_insn *insn,
unsigned int *data)
{
struct dyna_pci10xx_private *devpriv = dev->private;
int n;
unsigned int chan, range;
chan = CR_CHAN(insn->chanspec);
range = range_codes_pci1050_ai[CR_RANGE((insn->chanspec))];
mutex_lock(&devpriv->mutex);
for (n = 0; n < insn->n; n++) {
smp_mb();
/* trigger conversion and write data */
outw_p(data[n], dev->iobase);
udelay(10);
}
mutex_unlock(&devpriv->mutex);
return n;
}
static int dyna_pci10xx_insn_read_ai(struct comedi_device *dev,
struct comedi_subdevice *s,
struct comedi_insn *insn,
unsigned int *data)
{
struct dyna_pci10xx_private *devpriv = dev->private;
int n;
u16 d = 0;
int ret = 0;
unsigned int chan, range;
/* get the channel number and range */
chan = CR_CHAN(insn->chanspec);
range = range_codes_pci1050_ai[CR_RANGE((insn->chanspec))];
mutex_lock(&devpriv->mutex);
/* convert n samples */
for (n = 0; n < insn->n; n++) {
/* trigger conversion */
smp_mb();
outw_p(0x0000 + range + chan, dev->iobase + 2);
udelay(10);
ret = comedi_timeout(dev, s, insn, dyna_pci10xx_ai_eoc, 0);
if (ret)
break;
/* read data */
d = inw_p(dev->iobase);
/* mask the first 4 bits - EOC bits */
d &= 0x0FFF;
data[n] = d;
}
mutex_unlock(&devpriv->mutex);
/* return the number of samples read/written */
return ret ? ret : n;
}
int vga_set_mode(int xres, int yres, int bitdepth)
{
int i;
outb_p(0x63, MiscOutputReg);
outb_p(0x00, 0x3da);
for (i=0; i < 5; i++) {
outb_p(i, 0x3c4);
outb_p(mode13[0][i], 0x3c4+1);
}
outw_p(0x0e11, 0x3d4);
for (i=0; i < 0x19; i++) {
outb_p(i, 0x3d4);
outb_p(mode13[1][i], (0x3d4 + 1));
}
for (i=0; i < 0x9; i++) {
outb_p(i, 0x3ce);
outb_p(mode13[2][i], (0x3ce + 1));
}
inb_p(0x3da);
for (i=0; i < 0x15; i++) {
inw(DataReg);
outb_p(i, AddressReg);
outb_p(mode13[3][i], DataReg);
}
outb_p(0x20, 0x3c0);
return 1;
}
/*
* Do a soft reset of the PCI card using the Configuration Option Register
* We need this to get going...
* This is the part of the code that is strongly inspired from wlan-ng
*
* Note bis : Don't try to access HERMES_CMD during the reset phase.
* It just won't work !
*/
static int nortel_pci_cor_reset(struct orinoco_private *priv)
{
struct nortel_pci_card *card = priv->card;
/* Assert the reset until the card notice */
outw_p(8, card->iobase1 + 2);
inw(card->iobase2 + COR_OFFSET);
outw_p(0x80, card->iobase2 + COR_OFFSET);
mdelay(1);
/* Give time for the card to recover from this hard effort */
outw_p(0, card->iobase2 + COR_OFFSET);
outw_p(0, card->iobase2 + COR_OFFSET);
mdelay(1);
/* set COR as usual */
outw_p(COR_VALUE, card->iobase2 + COR_OFFSET);
outw_p(COR_VALUE, card->iobase2 + COR_OFFSET);
mdelay(1);
outw_p(0x228, card->iobase1 + 2);
return 0;
}
static int amd756_transaction(struct i2c_adapter *adap)
{
int temp;
int result = 0;
int timeout = 0;
dev_dbg(&adap->dev, "Transaction (pre): GS=%04x, GE=%04x, ADD=%04x, "
"DAT=%04x\n", inw_p(SMB_GLOBAL_STATUS),
inw_p(SMB_GLOBAL_ENABLE), inw_p(SMB_HOST_ADDRESS),
inb_p(SMB_HOST_DATA));
/* Make sure the SMBus host is ready to start transmitting */
if ((temp = inw_p(SMB_GLOBAL_STATUS)) & (GS_HST_STS | GS_SMB_STS)) {
dev_dbg(&adap->dev, "SMBus busy (%04x). Waiting...\n", temp);
do {
msleep(1);
temp = inw_p(SMB_GLOBAL_STATUS);
} while ((temp & (GS_HST_STS | GS_SMB_STS)) &&
(timeout++ < MAX_TIMEOUT));
/* If the SMBus is still busy, we give up */
if (timeout > MAX_TIMEOUT) {
dev_dbg(&adap->dev, "Busy wait timeout (%04x)\n", temp);
goto abort;
}
timeout = 0;
}
/* start the transaction by setting the start bit */
outw_p(inw(SMB_GLOBAL_ENABLE) | GE_HOST_STC, SMB_GLOBAL_ENABLE);
/* We will always wait for a fraction of a second! */
do {
msleep(1);
temp = inw_p(SMB_GLOBAL_STATUS);
} while ((temp & GS_HST_STS) && (timeout++ < MAX_TIMEOUT));
/* If the SMBus is still busy, we give up */
if (timeout > MAX_TIMEOUT) {
dev_dbg(&adap->dev, "Completion timeout!\n");
goto abort;
}
if (temp & GS_PRERR_STS) {
result = -ENXIO;
dev_dbg(&adap->dev, "SMBus Protocol error (no response)!\n");
}
if (temp & GS_COL_STS) {
result = -EIO;
dev_warn(&adap->dev, "SMBus collision!\n");
}
if (temp & GS_TO_STS) {
result = -ETIMEDOUT;
dev_dbg(&adap->dev, "SMBus protocol timeout!\n");
}
if (temp & GS_HCYC_STS)
dev_dbg(&adap->dev, "SMBus protocol success!\n");
outw_p(GS_CLEAR_STS, SMB_GLOBAL_STATUS);
#ifdef DEBUG
if (((temp = inw_p(SMB_GLOBAL_STATUS)) & GS_CLEAR_STS) != 0x00) {
dev_dbg(&adap->dev,
"Failed reset at end of transaction (%04x)\n", temp);
}
#endif
dev_dbg(&adap->dev,
"Transaction (post): GS=%04x, GE=%04x, ADD=%04x, DAT=%04x\n",
inw_p(SMB_GLOBAL_STATUS), inw_p(SMB_GLOBAL_ENABLE),
inw_p(SMB_HOST_ADDRESS), inb_p(SMB_HOST_DATA));
return result;
abort:
dev_warn(&adap->dev, "Sending abort\n");
outw_p(inw(SMB_GLOBAL_ENABLE) | GE_ABORT, SMB_GLOBAL_ENABLE);
msleep(100);
outw_p(GS_CLEAR_STS, SMB_GLOBAL_STATUS);
return -EIO;
}
/* Return negative errno on error. */
static s32 amd756_access(struct i2c_adapter * adap, u16 addr,
unsigned short flags, char read_write,
u8 command, int size, union i2c_smbus_data * data)
{
int i, len;
int status;
switch (size) {
case I2C_SMBUS_QUICK:
outw_p(((addr & 0x7f) << 1) | (read_write & 0x01),
SMB_HOST_ADDRESS);
size = AMD756_QUICK;
break;
case I2C_SMBUS_BYTE:
outw_p(((addr & 0x7f) << 1) | (read_write & 0x01),
SMB_HOST_ADDRESS);
if (read_write == I2C_SMBUS_WRITE)
outb_p(command, SMB_HOST_DATA);
size = AMD756_BYTE;
break;
case I2C_SMBUS_BYTE_DATA:
outw_p(((addr & 0x7f) << 1) | (read_write & 0x01),
SMB_HOST_ADDRESS);
outb_p(command, SMB_HOST_COMMAND);
if (read_write == I2C_SMBUS_WRITE)
outw_p(data->byte, SMB_HOST_DATA);
size = AMD756_BYTE_DATA;
break;
case I2C_SMBUS_WORD_DATA:
outw_p(((addr & 0x7f) << 1) | (read_write & 0x01),
SMB_HOST_ADDRESS);
outb_p(command, SMB_HOST_COMMAND);
if (read_write == I2C_SMBUS_WRITE)
outw_p(data->word, SMB_HOST_DATA); /* TODO: endian???? */
size = AMD756_WORD_DATA;
break;
case I2C_SMBUS_BLOCK_DATA:
outw_p(((addr & 0x7f) << 1) | (read_write & 0x01),
SMB_HOST_ADDRESS);
outb_p(command, SMB_HOST_COMMAND);
if (read_write == I2C_SMBUS_WRITE) {
len = data->block[0];
if (len < 0)
len = 0;
if (len > 32)
len = 32;
outw_p(len, SMB_HOST_DATA);
/* i = inw_p(SMBHSTCNT); Reset SMBBLKDAT */
for (i = 1; i <= len; i++)
outb_p(data->block[i],
SMB_HOST_BLOCK_DATA);
}
size = AMD756_BLOCK_DATA;
break;
default:
dev_warn(&adap->dev, "Unsupported transaction %d\n", size);
return -EOPNOTSUPP;
}
/* How about enabling interrupts... */
outw_p(size & GE_CYC_TYPE_MASK, SMB_GLOBAL_ENABLE);
status = amd756_transaction(adap);
if (status)
return status;
if ((read_write == I2C_SMBUS_WRITE) || (size == AMD756_QUICK))
return 0;
switch (size) {
case AMD756_BYTE:
data->byte = inw_p(SMB_HOST_DATA);
break;
case AMD756_BYTE_DATA:
data->byte = inw_p(SMB_HOST_DATA);
break;
case AMD756_WORD_DATA:
data->word = inw_p(SMB_HOST_DATA); /* TODO: endian???? */
break;
case AMD756_BLOCK_DATA:
data->block[0] = inw_p(SMB_HOST_DATA) & 0x3f;
if(data->block[0] > 32)
data->block[0] = 32;
/* i = inw_p(SMBHSTCNT); Reset SMBBLKDAT */
for (i = 1; i <= data->block[0]; i++)
data->block[i] = inb_p(SMB_HOST_BLOCK_DATA);
break;
}
return 0;
}
/* Return -1 on error. */
static s32 amd756_access(struct i2c_adapter * adap, u16 addr,
unsigned short flags, char read_write,
u8 command, int size, union i2c_smbus_data * data)
{
int i, len;
/** TODO: Should I supporte the 10-bit transfers? */
switch (size) {
case I2C_SMBUS_PROC_CALL:
dev_dbg(&adap->dev, "I2C_SMBUS_PROC_CALL not supported!\n");
/* TODO: Well... It is supported, I'm just not sure what to do here... */
return -1;
case I2C_SMBUS_QUICK:
outw_p(((addr & 0x7f) << 1) | (read_write & 0x01),
SMB_HOST_ADDRESS);
size = AMD756_QUICK;
break;
case I2C_SMBUS_BYTE:
outw_p(((addr & 0x7f) << 1) | (read_write & 0x01),
SMB_HOST_ADDRESS);
if (read_write == I2C_SMBUS_WRITE)
outb_p(command, SMB_HOST_DATA);
size = AMD756_BYTE;
break;
case I2C_SMBUS_BYTE_DATA:
outw_p(((addr & 0x7f) << 1) | (read_write & 0x01),
SMB_HOST_ADDRESS);
outb_p(command, SMB_HOST_COMMAND);
if (read_write == I2C_SMBUS_WRITE)
outw_p(data->byte, SMB_HOST_DATA);
size = AMD756_BYTE_DATA;
break;
case I2C_SMBUS_WORD_DATA:
outw_p(((addr & 0x7f) << 1) | (read_write & 0x01),
SMB_HOST_ADDRESS);
outb_p(command, SMB_HOST_COMMAND);
if (read_write == I2C_SMBUS_WRITE)
outw_p(data->word, SMB_HOST_DATA); /* TODO: endian???? */
size = AMD756_WORD_DATA;
break;
case I2C_SMBUS_BLOCK_DATA:
outw_p(((addr & 0x7f) << 1) | (read_write & 0x01),
SMB_HOST_ADDRESS);
outb_p(command, SMB_HOST_COMMAND);
if (read_write == I2C_SMBUS_WRITE) {
len = data->block[0];
if (len < 0)
len = 0;
if (len > 32)
len = 32;
outw_p(len, SMB_HOST_DATA);
/* i = inw_p(SMBHSTCNT); Reset SMBBLKDAT */
for (i = 1; i <= len; i++)
outb_p(data->block[i],
SMB_HOST_BLOCK_DATA);
}
size = AMD756_BLOCK_DATA;
break;
}
/* How about enabling interrupts... */
outw_p(size & GE_CYC_TYPE_MASK, SMB_GLOBAL_ENABLE);
if (amd756_transaction(adap)) /* Error in transaction */
return -1;
if ((read_write == I2C_SMBUS_WRITE) || (size == AMD756_QUICK))
return 0;
switch (size) {
case AMD756_BYTE:
data->byte = inw_p(SMB_HOST_DATA);
break;
case AMD756_BYTE_DATA:
data->byte = inw_p(SMB_HOST_DATA);
break;
case AMD756_WORD_DATA:
data->word = inw_p(SMB_HOST_DATA); /* TODO: endian???? */
break;
case AMD756_BLOCK_DATA:
data->block[0] = inw_p(SMB_HOST_DATA) & 0x3f;
if(data->block[0] > 32)
data->block[0] = 32;
/* i = inw_p(SMBHSTCNT); Reset SMBBLKDAT */
for (i = 1; i <= data->block[0]; i++)
data->block[i] = inb_p(SMB_HOST_BLOCK_DATA);
break;
}
return 0;
}
/*
* Initialize the board
*/
void __init setup_cqreek(void)
{
int i;
/* udelay is not available at setup time yet... */
#define DELAY() do {for (i=0; i<10000; i++) ctrl_inw(0xa0000000);} while(0)
if ((inw (BRIDGE_FEATURE) & 1)) { /* We have IDE interface */
outw_p(0, BRIDGE_IDE_INTR_LVL);
outw_p(0, BRIDGE_IDE_INTR_MASK);
outw_p(0, BRIDGE_IDE_CTRL);
DELAY();
outw_p(0x8000, BRIDGE_IDE_CTRL);
DELAY();
outw_p(0xffff, BRIDGE_IDE_INTR_STAT); /* Clear interrupt status */
outw_p(0x0f-14, BRIDGE_IDE_INTR_LVL); /* Use 14 IPR */
outw_p(1, BRIDGE_IDE_INTR_MASK); /* Enable interrupt */
has_ide=1;
}
if ((inw (BRIDGE_FEATURE) & 2)) { /* We have ISA interface */
outw_p(0, BRIDGE_ISA_INTR_LVL);
outw_p(0, BRIDGE_ISA_INTR_MASK);
outw_p(0, BRIDGE_ISA_CTRL);
DELAY();
outw_p(0x8000, BRIDGE_ISA_CTRL);
DELAY();
outw_p(0xffff, BRIDGE_ISA_INTR_STAT); /* Clear interrupt status */
outw_p(0x0f-10, BRIDGE_ISA_INTR_LVL); /* Use 10 IPR */
outw_p(0xfff8, BRIDGE_ISA_INTR_MASK); /* Enable interrupt */
has_isa=1;
}
printk(KERN_INFO "CqREEK Setup (IDE=%d, ISA=%d)...done\n", has_ide, has_isa);
}