static int phytec_pfla02_init(void) { if (!of_machine_is_compatible("phytec,imx6q-pfla02") && !of_machine_is_compatible("phytec,imx6dl-pfla02") && !of_machine_is_compatible("phytec,imx6s-pfla02")) return 0; phyflex_err006282_workaround(); eth_phy_reset(); phy_register_fixup_for_uid(PHY_ID_KSZ9031, MICREL_PHY_ID_MASK, ksz9031rn_phy_fixup); imx6_bbu_nand_register_handler("nand", BBU_HANDLER_FLAG_DEFAULT); return 0; }
void board_init_f(ulong dummy) { unsigned int ramchip; struct mx6_ddr_sysinfo sysinfo = { /* width of data bus:0=16,1=32,2=64 */ .dsize = 2, /* config for full 4GB range so that get_mem_size() works */ .cs_density = 32, /* 512 MB */ /* single chip select */ #if IS_ENABLED(CONFIG_SPL_DRAM_1_BANK) .ncs = 1, #else .ncs = 2, #endif .cs1_mirror = 1, .rtt_wr = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Wr = RZQ/4 */ .rtt_nom = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Nom = RZQ/4 */ .walat = 1, /* Write additional latency */ .ralat = 5, /* Read additional latency */ .mif3_mode = 3, /* Command prediction working mode */ .bi_on = 1, /* Bank interleaving enabled */ .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */ .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */ .ddr_type = DDR_TYPE_DDR3, .refsel = 1, /* Refresh cycles at 32KHz */ .refr = 7, /* 8 refresh commands per refresh cycle */ }; #ifdef CONFIG_CMD_NAND /* Enable NAND */ setup_gpmi_nand(); #endif /* setup clock gating */ ccgr_init(); /* setup AIPS and disable watchdog */ arch_cpu_init(); /* setup AXI */ gpr_init(); board_early_init_f(); /* setup GP timer */ timer_init(); /* UART clocks enabled and gd valid - init serial console */ preloader_console_init(); setup_spi(); setup_gpios(); /* DDR initialization */ spl_dram_init(&sysinfo, &mt41k_xx[RAM_MT256K]); ramchip = pfla02_detect_chiptype(); debug("Detected chip %d\n", ramchip); #if !IS_ENABLED(CONFIG_SPL_DRAM_1_BANK) switch (ramchip) { case RAM_MT64K: sysinfo.cs_density = 6; break; case RAM_MT128K: sysinfo.cs_density = 10; break; case RAM_MT256K: sysinfo.cs_density = 18; break; } #endif spl_dram_init(&sysinfo, &mt41k_xx[ramchip]); /* Clear the BSS. */ memset(__bss_start, 0, __bss_end - __bss_start); phyflex_err006282_workaround(); /* load/boot image from boot device */ board_init_r(NULL, 0); }