void NES_mapper248::SNSS_fixup() // HACK HACK HACK HACK
{
nes6502_context *context;
context = nes6502_get_current_context ();
prg0 = MAP248_ROM(context->mem_page[prg_swap() ? 6 : 4]);
prg1 = MAP248_ROM(context->mem_page[5]);
if(chr_swap())
{
chr01 = MAP248_VROM(attached_ppu->PPU_VRAM_banks[4]);
chr23 = MAP248_VROM(attached_ppu->PPU_VRAM_banks[6]);
chr4 = MAP248_VROM(attached_ppu->PPU_VRAM_banks[0]);
chr5 = MAP248_VROM(attached_ppu->PPU_VRAM_banks[1]);
chr6 = MAP248_VROM(attached_ppu->PPU_VRAM_banks[2]);
chr7 = MAP248_VROM(attached_ppu->PPU_VRAM_banks[3]);
}
else
{
chr01 = MAP248_VROM(attached_ppu->PPU_VRAM_banks[0]);
chr23 = MAP248_VROM(attached_ppu->PPU_VRAM_banks[2]);
chr4 = MAP248_VROM(attached_ppu->PPU_VRAM_banks[4]);
chr5 = MAP248_VROM(attached_ppu->PPU_VRAM_banks[5]);
chr6 = MAP248_VROM(attached_ppu->PPU_VRAM_banks[6]);
chr7 = MAP248_VROM(attached_ppu->PPU_VRAM_banks[7]);
}
}
void NES_mapper248::MMC3_set_CPU_banks()
{
if(prg_swap())
{
set_CPU_banks(num_8k_ROM_banks-2,prg1,prg0,num_8k_ROM_banks-1);
}
else
{
set_CPU_banks(prg0,prg1,num_8k_ROM_banks-2,num_8k_ROM_banks-1);
}
}
void extcl_cpu_wr_mem_MMC5(WORD address, BYTE value) {
if (address < 0x5000) {
return;
}
switch (address) {
case 0x5000:
square_reg0(mmc5.S3);
return;
case 0x5001:
/* lo sweep non e' utilizzato */
return;
case 0x5002:
square_reg2(mmc5.S3);
return;
case 0x5003:
square_reg3(mmc5.S3);
return;
case 0x5004:
square_reg0(mmc5.S4);
return;
case 0x5005:
/* lo sweep non e' utilizzato */
return;
case 0x5006:
square_reg2(mmc5.S4);
return;
case 0x5007:
square_reg3(mmc5.S4);
return;
case 0x5010:
mmc5.pcm.enabled = ~value & 0x01;
mmc5.pcm.output = 0;
if (mmc5.pcm.enabled) {
mmc5.pcm.output = mmc5.pcm.amp;
}
mmc5.pcm.clocked = TRUE;
return;
case 0x5011:
mmc5.pcm.amp = value;
mmc5.pcm.output = 0;
if (mmc5.pcm.enabled) {
mmc5.pcm.output = mmc5.pcm.amp;
}
mmc5.pcm.clocked = TRUE;
return;
case 0x5015:
if (!(mmc5.S3.length.enabled = value & 0x01)) {
mmc5.S3.length.value = 0;
}
if (!(mmc5.S4.length.enabled = value & 0x02)) {
mmc5.S4.length.value = 0;
}
return;
case 0x5100:
value &= 0x03;
if (value != mmc5.prg_mode) {
mmc5.prg_mode = value;
prg_swap();
}
return;
case 0x5101:
value &= 0x03;
if (value != mmc5.chr_mode) {
mmc5.chr_mode = value;
if ((r2000.size_spr != 16) || !r2001.visible || r2002.vblank) {
if (mmc5.chr_last == CHR_S) {
use_chr_s();
} else {
use_chr_b();
}
}
}
return;
case 0x5102:
case 0x5103:
mmc5.prg_ram_write[address & 0x0001] = value & 0x03;
if ((mmc5.prg_ram_write[0] == 0x02) && (mmc5.prg_ram_write[1] == 0x01)) {
cpu.prg_ram_wr_active = TRUE;
} else {
cpu.prg_ram_wr_active = FALSE;
}
return;
case 0x5104:
mmc5.ext_mode = value & 0x03;
return;
case 0x5105:
nmt_update(0, 0)
nmt_update(2, 1)
nmt_update(4, 2)
nmt_update(6, 3)
return;
/* --------------------------------- PRG bankswitching ---------------------------------*/
case 0x5106:
mmc5.fill_tile = value;
memset(&mmc5.fill_table[0], mmc5.fill_tile, 0x3C0);
memset(&mmc5.fill_table[0x3C0], filler_attrib[mmc5.fill_attr], 0x40);
return;
case 0x5107:
mmc5.fill_attr = value & 0x03;
memset(&mmc5.fill_table[0x3C0], filler_attrib[mmc5.fill_attr], 0x40);
return;
case 0x5113: {
BYTE bank = prg_ram_access[prg_ram_mode][value & 0x07];
if (bank != INVALID) {
prg.ram_plus_8k = &prg.ram_plus[bank * 0x2000];
}
return;
}
case 0x5114:
case 0x5115:
case 0x5116:
case 0x5117:
address &= 0x0003;
if (mmc5.prg_bank[address] != value) {
mmc5.prg_bank[address] = value;
prg_swap();
}
return;
/* --------------------------------- CHR bankswitching ---------------------------------*/
case 0x5120:
case 0x5121:
case 0x5122:
case 0x5123:
case 0x5124:
case 0x5125:
case 0x5126:
case 0x5127: {
WORD bank = value | (mmc5.chr_high << 2);
address &= 0x0007;
if ((mmc5.chr_last != CHR_S) || (mmc5.chr_s[address] != bank)) {
mmc5.chr_s[address] = bank;
mmc5.chr_last = CHR_S;
if ((r2000.size_spr != 16) || !r2001.visible || r2002.vblank) {
use_chr_s();
}
}
return;
}
case 0x5128:
case 0x5129:
case 0x512A:
case 0x512B: {
WORD bank = value | (mmc5.chr_high << 2);
address &= 0x0003;
if ((mmc5.chr_last != CHR_B) || (mmc5.chr_b[address] != bank)) {
mmc5.chr_b[address] = bank;
mmc5.chr_last = CHR_B;
if ((r2000.size_spr != 16) || !r2001.visible || r2002.vblank) {
use_chr_b();
}
}
return;
}
case 0x5130:
mmc5.chr_high = (value & 0x03) << 6;
return;
case 0x5200:
mmc5.split = value & 0x80;
mmc5.split_side = value & 0x40;
mmc5.split_st_tile = value & 0x1F;
return;
case 0x5201:
if (value >= 240) {
value -= 16;
}
mmc5.split_scrl = value;
return;
case 0x5202:
control_bank(info.chr.rom.max.banks_4k)
mmc5.split_bank = value << 12;
return;
case 0x5203:
irql2f.scanline = value;
return;
case 0x5204:
if (value & 0x80) {
irql2f.enable = TRUE;
return;
}
irql2f.enable = FALSE;
/* disabilito l'IRQ dell'MMC5 */
irq.high &= ~EXT_IRQ;
return;
case 0x5205:
mmc5.factor[0] = value;
mmc5.product = mmc5.factor[0] * mmc5.factor[1];
return;
case 0x5206:
mmc5.factor[1] = value;
mmc5.product = mmc5.factor[0] * mmc5.factor[1];
return;
default:
if ((address >= 0x5C00) && (address < 0x6000)) {
address &= 0x03FF;
if (mmc5.ext_mode < MODE2) {
if (!r2002.vblank && r2001.visible && (ppu.screen_y < SCR_LINES)) {
mmc5.ext_ram[address] = value;
} else {
mmc5.ext_ram[address] = 0;
}
return;
}
if (mmc5.ext_mode == MODE2) {
mmc5.ext_ram[address] = value;
return;
}
return;
}
/*
* posso memorizzare nella PRG rom solo se il banco in cui
* la rom vuole scrivere punta ad un banco di PRG ram.
*/
if (address >= 0x8000) {
BYTE index = ((address >> 13) & 0x03);
if (mmc5.prg_ram_bank[index][0] && cpu.prg_ram_wr_active) {
prg.rom_8k[index][address & 0x1FFF] = value;
}
}
return;
}
