/** * xgene_ahci_do_hardreset - Issue the actual COMRESET * @link: link to reset * @deadline: deadline jiffies for the operation * @online: Return value to indicate if device online * * Due to the limitation of the hardware PHY, a difference set of setting is * required for each supported disk speed - Gen3 (6.0Gbps), Gen2 (3.0Gbps), * and Gen1 (1.5Gbps). Otherwise during long IO stress test, the PHY will * report disparity error and etc. In addition, during COMRESET, there can * be error reported in the register PORT_SCR_ERR. For SERR_DISPARITY and * SERR_10B_8B_ERR, the PHY receiver line must be reseted. The following * algorithm is followed to proper configure the hardware PHY during COMRESET: * * Alg Part 1: * 1. Start the PHY at Gen3 speed (default setting) * 2. Issue the COMRESET * 3. If no link, go to Alg Part 3 * 4. If link up, determine if the negotiated speed matches the PHY * configured speed * 5. If they matched, go to Alg Part 2 * 6. If they do not matched and first time, configure the PHY for the linked * up disk speed and repeat step 2 * 7. Go to Alg Part 2 * * Alg Part 2: * 1. On link up, if there are any SERR_DISPARITY and SERR_10B_8B_ERR error * reported in the register PORT_SCR_ERR, then reset the PHY receiver line * 2. Go to Alg Part 3 * * Alg Part 3: * 1. Clear any pending from register PORT_SCR_ERR. * * NOTE: For the initial version, we will NOT support Gen1/Gen2. In addition * and until the underlying PHY supports an method to reset the receiver * line, on detection of SERR_DISPARITY or SERR_10B_8B_ERR errors, * an warning message will be printed. */ static int xgene_ahci_do_hardreset(struct ata_link *link, unsigned long deadline, bool *online) { const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context); struct ata_port *ap = link->ap; struct ahci_host_priv *hpriv = ap->host->private_data; struct xgene_ahci_context *ctx = hpriv->plat_data; struct ahci_port_priv *pp = ap->private_data; u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG; void __iomem *port_mmio = ahci_port_base(ap); struct ata_taskfile tf; int rc; u32 val; /* clear D2H reception area to properly wait for D2H FIS */ ata_tf_init(link->device, &tf); tf.command = ATA_BUSY; ata_tf_to_fis(&tf, 0, 0, d2h_fis); rc = sata_link_hardreset(link, timing, deadline, online, ahci_check_ready); val = readl(port_mmio + PORT_SCR_ERR); if (val & (SERR_DISPARITY | SERR_10B_8B_ERR)) dev_warn(ctx->dev, "link has error\n"); /* clear all errors if any pending */ val = readl(port_mmio + PORT_SCR_ERR); writel(val, port_mmio + PORT_SCR_ERR); return rc; }
ahci_init_controller(host); } static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class, unsigned long deadline) { struct ata_port *ap = link->ap; bool online; int rc; DPRINTK("ENTER\n"); ahci_stop_engine(ap); rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context), deadline, &online, NULL); ahci_start_engine(ap); DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class); /* vt8251 doesn't clear BSY on signature FIS reception, * request follow-up softreset. */ return online ? -EAGAIN : rc; } static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class, unsigned long deadline) { struct ata_port *ap = link->ap;
* Kernel thread context (may sleep) * * RETURNS: * 0 on success, -errno otherwise. */ int sata_pmp_std_hardreset(struct ata_link *link, unsigned int *class, unsigned long deadline) { const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context); u32 tmp; int rc; DPRINTK("ENTER\n"); /* do hardreset */ rc = sata_link_hardreset(link, timing, deadline); if (rc) { ata_link_printk(link, KERN_ERR, "COMRESET failed (errno=%d)\n", rc); goto out; } /* clear SError bits including .X which blocks the port when set */ rc = sata_scr_write(link, SCR_ERROR, 0xffffffff); if (rc) { ata_link_printk(link, KERN_ERR, "failed to clear SError " "during hardreset (errno=%d)\n", rc); goto out; } /* if device is present, follow up with srst to wait for !BSY */