/* register simulator-specific statistics */
void
sim_reg_stats(struct stat_sdb_t *sdb)
{
stat_reg_counter(sdb, "sim_num_insn",
"total number of instructions executed",
&sim_num_insn, sim_num_insn, NULL);
stat_reg_counter(sdb, "sim_num_refs",
"total number of loads and stores executed",
&sim_num_refs, 0, NULL);
stat_reg_int(sdb, "sim_elapsed_time",
"total simulation time in seconds",
&sim_elapsed_time, 0, NULL);
stat_reg_formula(sdb, "sim_inst_rate",
"simulation speed (in insts/sec)",
"sim_num_insn / sim_elapsed_time", NULL);
stat_reg_counter(sdb, "sim_num_branches",
"total number of branches executed",
&sim_num_branches, /* initial value */0, /* format */NULL);
stat_reg_formula(sdb, "sim_IPB",
"instruction per branch",
"sim_num_insn / sim_num_branches", /* format */NULL);
/* register predictor stats */
if (pred)
bpred_reg_stats(pred, sdb);
}
/* register memory system-specific statistics */
void
mem_reg_stats(struct mem_t *mem, /* memory space to declare */
struct stat_sdb_t *sdb) /* stats data base */
{
char buf[512], buf1[512];
sprintf(buf, "%s.page_count", mem->name);
stat_reg_counter(sdb, buf, "total number of pages allocated",
&mem->page_count, mem->page_count, NULL);
sprintf(buf, "%s.page_mem", mem->name);
sprintf(buf1, "%s.page_count * %d / 1024", mem->name, MD_PAGE_SIZE);
stat_reg_formula(sdb, buf, "total size of memory pages allocated",
buf1, "%11.0fk");
sprintf(buf, "%s.ptab_misses", mem->name);
stat_reg_counter(sdb, buf, "total first level page table misses",
&mem->ptab_misses, mem->ptab_misses, NULL);
sprintf(buf, "%s.ptab_accesses", mem->name);
stat_reg_counter(sdb, buf, "total page table accesses",
&mem->ptab_accesses, mem->ptab_accesses, NULL);
sprintf(buf, "%s.ptab_miss_rate", mem->name);
sprintf(buf1, "%s.ptab_misses / %s.ptab_accesses", mem->name, mem->name);
stat_reg_formula(sdb, buf, "first level page table miss rate", buf1, NULL);
}
/* register simulator-specific statistics */
void
sim_reg_stats(struct stat_sdb_t *sdb)
{
stat_reg_counter(sdb, "sim_num_insn",
"total number of instructions executed",
&sim_num_insn, sim_num_insn, NULL);
stat_reg_uint(sdb, "sim_cycles",
"total number of cycles",
&sim_cycle, 0, NULL);
stat_reg_formula(sdb, "sim_cpi",
"cycles per instruction (CPI)",
"sim_cycles / sim_num_insn", NULL);
stat_reg_counter(sdb, "sim_num_refs",
"total number of loads and stores executed",
&sim_num_refs, 0, NULL);
stat_reg_int(sdb, "sim_elapsed_time",
"total simulation time in seconds",
&sim_elapsed_time, 0, NULL);
stat_reg_formula(sdb, "sim_inst_rate",
"simulation speed (in insts/sec)",
"sim_num_insn / sim_elapsed_time", NULL);
ld_reg_stats(sdb);
mem_reg_stats(mem, sdb);
}
/* register simulator-specific statistics */
void
sim_reg_stats(struct stat_sdb_t *sdb)
{
stat_reg_counter(sdb, "sim_num_insn",
"total number of instructions executed",
&sim_num_insn, sim_num_insn, NULL);
stat_reg_counter(sdb, "sim_num_refs",
"total number of loads and stores executed",
&sim_num_refs, 0, NULL);
stat_reg_int(sdb, "sim_elapsed_time",
"total simulation time in seconds",
&sim_elapsed_time, 0, NULL);
stat_reg_formula(sdb, "sim_inst_rate",
"simulation speed (in insts/sec)",
"sim_num_insn / sim_elapsed_time", NULL);
/* ECE552 Assignment 1 - BEGIN CODE */
stat_reg_counter(sdb, "sim_num_RAW_hazard_q1",
"total number of RAW hazards (q1)",
&sim_num_RAW_hazard_q1, sim_num_RAW_hazard_q1, NULL);
stat_reg_counter(sdb, "sim_num_RAW_hazard_q1_1",
"total number of RAW hazards with 1 cycle stall (q1)",
&sim_num_RAW_hazard_q1_1, sim_num_RAW_hazard_q1_1, NULL);
stat_reg_counter(sdb, "sim_num_RAW_hazard_q1_2",
"total number of RAW hazards with 2 cycle stall (q1)",
&sim_num_RAW_hazard_q1_2, sim_num_RAW_hazard_q1_2, NULL);
stat_reg_counter(sdb, "sim_num_RAW_hazard_q2",
"total number of RAW hazards (q2)",
&sim_num_RAW_hazard_q2, sim_num_RAW_hazard_q2, NULL);
stat_reg_counter(sdb, "sim_num_RAW_hazard_q2_1",
"total number of RAW hazards with 1 cycle stall (q2)",
&sim_num_RAW_hazard_q2_1, sim_num_RAW_hazard_q2_1, NULL);
stat_reg_counter(sdb, "sim_num_RAW_hazard_q2_2",
"total number of RAW hazards with 2 cycle stall (q2)",
&sim_num_RAW_hazard_q2_2, sim_num_RAW_hazard_q2_2, NULL);
stat_reg_formula(sdb, "CPI_from_RAW_hazard_q1",
"CPI from RAW hazard (q1)",
"1*((sim_num_insn-sim_num_RAW_hazard_q1)/sim_num_insn)+2*(sim_num_RAW_hazard_q1_1/sim_num_insn)+3*(sim_num_RAW_hazard_q1_2/sim_num_insn)", NULL);
stat_reg_formula(sdb, "CPI_from_RAW_hazard_q2",
"CPI from RAW hazard (q2)",
"1*((sim_num_insn-sim_num_RAW_hazard_q2)/sim_num_insn)+2*(sim_num_RAW_hazard_q2_1/sim_num_insn)+3*(sim_num_RAW_hazard_q2_2/sim_num_insn)", NULL);
/* ECE552 Assignment 1 - END CODE */
ld_reg_stats(sdb);
mem_reg_stats(mem, sdb);
}
/* register simulator-specific statistics */
void
sim_reg_stats(struct stat_sdb_t *sdb)
{
stat_reg_counter(sdb, "sim_num_insn",
"total number of instructions executed",
&sim_num_insn, sim_num_insn, NULL);
stat_reg_counter(sdb, "sim_num_refs",
"total number of loads and stores executed",
&sim_num_refs, 0, NULL);
stat_reg_int(sdb, "sim_elapsed_time",
"total simulation time in seconds",
&sim_elapsed_time, 0, NULL);
stat_reg_formula(sdb, "sim_inst_rate",
"simulation speed (in insts/sec)",
"sim_num_insn / sim_elapsed_time", NULL);
/* ECE552 Pre-Assignment - BEGIN CODE*/
stat_reg_counter(sdb, "sim_num_loads",
"total number of load instructions",
&sim_num_loads, sim_num_loads, NULL);
stat_reg_formula(sdb, "sim_load_ratio",
"load instruction fraction",
"sim_num_loads / sim_num_insn", NULL);
stat_reg_counter(sdb, "sim_num_lduh",
"total number of load use hazards",
&sim_num_lduh, sim_num_lduh, NULL);
stat_reg_formula(sdb, "sim_load_use_ratio",
"load use fraction",
"sim_num_lduh / sim_num_insn", NULL);
/* ECE552 Pre-Assignment - END CODE*/
/* ECE552 Assignment 1 - BEGIN CODE */
stat_reg_counter(sdb, "sim_num_RAW_hazard_q1",
"total number of RAW hazards (q1)",
&sim_num_RAW_hazard_q1, sim_num_RAW_hazard_q1, NULL);
stat_reg_counter(sdb, "sim_num_RAW_hazard_q2",
"total number of RAW hazards (q2)",
&sim_num_RAW_hazard_q2, sim_num_RAW_hazard_q2, NULL);
stat_reg_formula(sdb, "CPI_from_RAW_hazard_q1",
"CPI from RAW hazard (q1)",
"1" /* ECE552 - MUST ADD YOUR FORMULA */, NULL);
stat_reg_formula(sdb, "CPI_from_RAW_hazard_q2",
"CPI from RAW hazard (q2)",
"1" /* ECE552 - MUST ADD YOUR FORMULA */, NULL);
/* ECE552 Assignment 1 - END CODE */
ld_reg_stats(sdb);
mem_reg_stats(mem, sdb);
}
/* register cache stats */
void
cache_reg_stats(struct cache_t *cp, /* cache instance */
struct stat_sdb_t *sdb) /* stats database */
{
char buf[512], buf1[512], *name;
/* get a name for this cache */
if (!cp->name || !cp->name[0])
name = "<unknown>";
else
name = cp->name;
sprintf(buf, "%s.accesses", name);
sprintf(buf1, "%s.hits + %s.misses", name, name);
stat_reg_formula(sdb, buf, "total number of accesses", buf1, "%12.0f");
sprintf(buf, "%s.hits", name);
stat_reg_counter(sdb, buf, "total number of hits", &cp->hits, 0, NULL);
sprintf(buf, "%s.misses", name);
stat_reg_counter(sdb, buf, "total number of misses", &cp->misses, 0, NULL);
sprintf(buf, "%s.replacements", name);
stat_reg_counter(sdb, buf, "total number of replacements",
&cp->replacements, 0, NULL);
sprintf(buf, "%s.writebacks", name);
stat_reg_counter(sdb, buf, "total number of writebacks",
&cp->writebacks, 0, NULL);
sprintf(buf, "%s.invalidations", name);
stat_reg_counter(sdb, buf, "total number of invalidations",
&cp->invalidations, 0, NULL);
sprintf(buf, "%s.miss_rate", name);
sprintf(buf1, "%s.misses / %s.accesses", name, name);
stat_reg_formula(sdb, buf, "miss rate (i.e., misses/ref)", buf1, NULL);
sprintf(buf, "%s.repl_rate", name);
sprintf(buf1, "%s.replacements / %s.accesses", name, name);
stat_reg_formula(sdb, buf, "replacement rate (i.e., repls/ref)", buf1, NULL);
sprintf(buf, "%s.wb_rate", name);
sprintf(buf1, "%s.writebacks / %s.accesses", name, name);
stat_reg_formula(sdb, buf, "writeback rate (i.e., wrbks/ref)", buf1, NULL);
sprintf(buf, "%s.inv_rate", name);
sprintf(buf1, "%s.invalidations / %s.accesses", name, name);
stat_reg_formula(sdb, buf, "invalidation rate (i.e., invs/ref)", buf1, NULL);
if(cp->num_mshr>0){
sprintf(buf, "%s.mshr_hits", name);
stat_reg_counter(sdb, buf, "%s mshr hits", &cp->mshr_hits, 0, NULL);
sprintf(buf, "%s.mshr_misses", name);
stat_reg_counter(sdb, buf, "%s mshr hits", &cp->mshr_misses, 0, NULL);
sprintf(buf, "%s.mshr_accesses", name);
stat_reg_counter(sdb, buf, "%s mshr accesses", &cp->mshr_accesses, 0, NULL);
}
}
/* power analyzer stats register */
void
panalyzer_reg_stats(
char *name, /* fu name */
fu_pdissipation_t *pdissipation, /* fu pdissipation statistics db ptr */
struct stat_sdb_t *sdb /* stats db ptr */)
{
char buf[512], buf1[512], buf2[512];
/* get a name for this cache */
if (!name || !name[0])
name = "<unknown>";
sprintf(buf, "%s.switching", name);
sprintf(buf1, "%s total in switching power dissipation", name);
stat_reg_double(sdb, buf, buf1, &pdissipation->switching, 0.0, "%12.4f");
sprintf(buf, "%s.avgswitching", name);
sprintf(buf1, "%s.switching / sim_cycle", name);
sprintf(buf2, "%s avg in switching power dissipation", name);
stat_reg_formula(sdb, buf, buf2, buf1, "%12.4f");
sprintf(buf, "%s.internal", name);
sprintf(buf1, "%s total internal power dissipation", name);
stat_reg_double(sdb, buf, buf1, &pdissipation->internal, 0.0, "%12.4f");
sprintf(buf, "%s.avginternal", name);
sprintf(buf1, "%s.internal / sim_cycle", name);
sprintf(buf2, "%s avg internal power dissipation", name);
stat_reg_formula(sdb, buf, buf2, buf1, "%12.4f");
sprintf(buf, "%s.leakage", name);
sprintf(buf1, "%s total leakage power dissipation", name);
stat_reg_double(sdb, buf, buf1, &pdissipation->leakage, 0.0, "%12.4f");
sprintf(buf, "%s.avgleakage", name);
sprintf(buf1, "%s.leakage / sim_cycle", name);
sprintf(buf2, "%s avg leakage power dissipation", name);
stat_reg_formula(sdb, buf, buf2, buf1, "%12.4f");
sprintf(buf, "%s.pdissipation", name);
sprintf(buf1, "%s total power dissipation", name);
stat_reg_double(sdb, buf, buf1, &pdissipation->pdissipation, 0.0, "%12.4f");
sprintf(buf, "%s.avgpdissipation", name);
sprintf(buf1, "%s.pdissipation / sim_cycle", name);
sprintf(buf2, "%s avg power dissipation", name);
stat_reg_formula(sdb, buf, buf2, buf1, "%12.4f");
sprintf(buf, "%s.peak", name);
sprintf(buf1, "%s peak power dissipation", name);
stat_reg_double(sdb, buf, buf1, &pdissipation->peak, 0.0, "%12.4f");
}
/* register default memory-controller stats */
void MC_t::reg_stats(struct stat_sdb_t * sdb)
{
stat_reg_counter(sdb, true, "MC.total_accesses", "total accesses to memory controller",
&total_accesses, /* initial value */0, TRUE, /* format */NULL);
stat_reg_counter(sdb, false, "MC.total_service_cycles", "cumulative request service cycles",
&total_service_cycles, /* initial value */0, TRUE, /* format */NULL);
stat_reg_formula(sdb, true, "MC.service_average","average cycles per MC request",
"MC.total_service_cycles / MC.total_accesses",/* format */NULL);
}
void
core_fetch_STM_t::reg_stats(struct stat_sdb_t * const sdb)
{
char buf[1024];
char buf2[1024];
struct thread_t * arch = core->current_thread;
stat_reg_note(sdb,"\n#### BPRED STATS ####");
bpred->reg_stats(sdb,core);
stat_reg_note(sdb,"\n#### INST CACHE STATS ####");
cache_reg_stats(sdb, core, core->memory.IL1);
cache_reg_stats(sdb, core, core->memory.ITLB);
stat_reg_note(sdb,"\n#### FETCH STATS ####");
sprintf(buf,"c%d.fetch_insn",arch->id);
stat_reg_counter(sdb, true, buf, "total number of instructions fetched", &core->stat.fetch_insn, 0, TRUE, NULL);
sprintf(buf,"c%d.fetch_uops",arch->id);
stat_reg_counter(sdb, true, buf, "total number of uops fetched", &core->stat.fetch_uops, 0, TRUE, NULL);
sprintf(buf,"c%d.fetch_IPC",arch->id);
sprintf(buf2,"c%d.fetch_insn/c%d.sim_cycle",arch->id,arch->id);
stat_reg_formula(sdb, true, buf, "IPC at fetch", buf2, NULL);
sprintf(buf,"c%d.fetch_uPC",arch->id);
sprintf(buf2,"c%d.fetch_uops/c%d.sim_cycle",arch->id,arch->id);
stat_reg_formula(sdb, true, buf, "uPC at fetch", buf2, NULL);
sprintf(buf,"c%d.fetch_stall",core->current_thread->id);
core->stat.fetch_stall = stat_reg_dist(sdb, buf,
"breakdown of stalls in fetch",
/* initial value */0,
/* array size */FSTALL_num,
/* bucket size */1,
/* print format */(PF_COUNT|PF_PDF),
/* format */NULL,
/* index map */fetch_stall_str,
/* scale_me */ TRUE,
/* print fn */NULL);
sprintf(buf,"c%d.byteQ_occupancy",arch->id);
stat_reg_counter(sdb, false, buf, "total byteQ occupancy (in lines/entries)", &core->stat.byteQ_occupancy, 0, TRUE, NULL);
sprintf(buf,"c%d.byteQ_avg",arch->id);
sprintf(buf2,"c%d.byteQ_occupancy/c%d.sim_cycle",arch->id,arch->id);
stat_reg_formula(sdb, true, buf, "average byteQ occupancy (in insts)", buf2, NULL);
}
/* register simulator-specific statistics */
void
sim_reg_stats(struct stat_sdb_t *sdb)
{
stat_reg_counter(sdb, "sim_num_insn",
"total number of instructions executed",
&sim_num_insn, sim_num_insn, NULL);
stat_reg_counter(sdb, "sim_num_cond_branches" /* label for printing */,
"total conditional branches executed" /* description */,
&g_total_cond_branches /* pointer to the counter */,
0 /* initial value for the counter */, NULL);
stat_reg_formula(sdb, "sim_cond_branch_freq",
"relative frequency of conditional branches",
"sim_num_cond_branches / sim_num_insn", NULL);
stat_reg_counter(sdb, "sim_num_uncond_branches",
"total unconditional branches executed",
&g_total_uncond_branches, 0, NULL);
stat_reg_formula(sdb, "sim_uncond_branch_freq",
"relative frequency of unconditional branches",
"sim_num_uncond_branches / sim_num_insn", NULL);
stat_reg_counter(sdb, "sim_num_fp_inst",
"total number of floating-point instructions",
&g_total_fp_inst, 0, NULL);
stat_reg_formula(sdb, "sim_fp_inst_freq",
"relative frequency of fp instructions",
"sim_num_fp_inst / sim_num_insn", NULL);
stat_reg_counter(sdb, "sim_num_store_inst",
"total number of store instructions",
&g_total_store_inst, 0, NULL);
stat_reg_formula(sdb, "sim_store_inst_freq",
"relative frequency of store instructions",
"sim_num_store_inst / sim_num_insn", NULL);
stat_reg_counter(sdb, "sim_num_ld_inst",
"total number of load instructions",
&g_total_ld_inst, 0, NULL);
stat_reg_formula(sdb, "sim_ld_inst_freq",
"relative frequency of load instructions",
"sim_num_ld_inst / sim_num_insn", NULL);
stat_reg_counter(sdb, "sim_num_imm_inst",
"total number of instructions with immediate operands",
&g_total_imm_inst, 0, NULL);
stat_reg_formula(sdb, "sim_imm_inst_freq",
"relative frequency of immediate instructions",
"sim_num_imm_inst / sim_num_insn", NULL);
stat_reg_counter(sdb, "sim_num_refs",
"total number of loads and stores executed",
&sim_num_refs, 0, NULL);
stat_reg_int(sdb, "sim_elapsed_time",
"total simulation time in seconds",
&sim_elapsed_time, 0, NULL);
stat_reg_formula(sdb, "sim_inst_rate",
"simulation speed (in insts/sec)",
"sim_num_insn / sim_elapsed_time", NULL);
ld_reg_stats(sdb);
mem_reg_stats(mem, sdb);
}
/* register simulator-specific statistics */
void
sim_reg_stats(struct stat_sdb_t *sdb)
{
stat_reg_counter(sdb, "sim_num_insn",
"total number of instructions executed",
&sim_num_insn, sim_num_insn, NULL);
stat_reg_counter(sdb, "sim_num_refs",
"total number of loads and stores executed",
&sim_num_refs, 0, NULL);
stat_reg_int(sdb, "sim_elapsed_time",
"total simulation time in seconds",
&sim_elapsed_time, 0, NULL);
stat_reg_formula(sdb, "sim_inst_rate",
"simulation speed (in insts/sec)",
"sim_num_insn / sim_elapsed_time", NULL);
ld_reg_stats(sdb);
mem_reg_stats(mem, sdb);
/* ECE552 Assignment 2 - STATS COUNTERS/FORMULAS - BEGIN */
stat_reg_counter(sdb, "sim_num_br", "total number of conditional branches", &sim_num_br, sim_num_br, NULL);
stat_reg_counter(sdb, "sim_num_mispred_static", "Static preditor: number of mispredicted branches", &sim_num_mispred_static, sim_num_mispred_static, NULL);
stat_reg_formula(sdb, "sim_br_static_ratio", "Static predictor: branch misprediction rate", "sim_num_mispred_static / sim_num_br", NULL);
stat_reg_counter(sdb, "sim_num_mispred_2bitsat", "2-bit sat. counter preditor: number of mispred. branches", &sim_num_mispred_2bitsat, sim_num_mispred_2bitsat, NULL);
stat_reg_formula(sdb, "sim_br_2bitsat_ratio", "2-bit sat. counter predictor: branch misprediction rate", "sim_num_mispred_2bitsat / sim_num_br", NULL);
stat_reg_counter(sdb, "sim_num_mispred_2level", "Two level preditor: number of mispredicted branches", &sim_num_mispred_2level, sim_num_mispred_2level, NULL);
stat_reg_formula(sdb, "sim_br_2level_ratio", "Two level predictor: branch misprediction rate", "sim_num_mispred_2level / sim_num_br", NULL);
stat_reg_counter(sdb, "sim_num_mispred_openend", "Open-ended preditor: number of mispredicted branches", &sim_num_mispred_openend, sim_num_mispred_openend, NULL);
stat_reg_formula(sdb, "sim_br_openend_ratio", "Open-ended predictor: branch misprediction rate", "sim_num_mispred_openend / sim_num_br", NULL);
/* ECE552 Assignment 2 - STATS COUNTERS/FORMULAS - END */
}
void core_commit_NONE_t::reg_stats(struct stat_sdb_t * const sdb)
{
char buf[1024];
char buf2[1024];
struct thread_t * arch = core->current_thread;
stat_reg_note(sdb,"\n#### COMMIT STATS ####");
sprintf(buf,"c%d.sim_cycle",arch->id);
stat_reg_qword(sdb, true, buf, "total number of cycles when last instruction (or uop) committed", (qword_t*) &core->sim_cycle, 0, TRUE, NULL);
sprintf(buf,"c%d.commit_insn",arch->id);
stat_reg_counter(sdb, true, buf, "total number of instructions committed", &core->stat.commit_insn, 0, TRUE, NULL);
sprintf(buf,"c%d.commit_IPC",arch->id);
sprintf(buf2,"c%d.commit_insn/c%d.sim_cycle",arch->id,arch->id);
stat_reg_formula(sdb, true, buf, "IPC at commit", buf2, NULL);
}
/* register simulator-specific statistics */
void
sim_reg_stats(struct stat_sdb_t *sdb)
{
stat_reg_counter(sdb, "sim_num_insn",
"total number of instructions executed",
&sim_num_insn, sim_num_insn, NULL);
stat_reg_counter(sdb, "sim_num_refs",
"total number of loads and stores executed",
&sim_num_refs, 0, NULL);
stat_reg_int(sdb, "sim_elapsed_time",
"total simulation time in seconds",
(int *)&sim_elapsed_time, 0, NULL);
stat_reg_formula(sdb, "sim_inst_rate",
"simulation speed (in insts/sec)",
"sim_num_insn / sim_elapsed_time", NULL);
}
/* register simulator-specific statistics */
void
sim_reg_stats(struct stat_sdb_t *sdb)
{
#ifndef NO_INSN_COUNT
stat_reg_counter(sdb, "sim_num_insn",
"total number of instructions executed",
&sim_num_insn, sim_num_insn, NULL);
#endif /* !NO_INSN_COUNT */
stat_reg_int(sdb, "sim_elapsed_time",
"total simulation time in seconds",
&sim_elapsed_time, 0, NULL);
#ifndef NO_INSN_COUNT
stat_reg_formula(sdb, "sim_inst_rate",
"simulation speed (in insts/sec)",
"sim_num_insn / sim_elapsed_time", NULL);
#endif /* !NO_INSN_COUNT */
ld_reg_stats(sdb);
mem_reg_stats(mem, sdb);
}
/* register simulator-specific statistics */
void
sim_reg_stats(struct stat_sdb_t *sdb)
{
stat_reg_counter(sdb, "sim_num_insn",
"total number of instructions executed",
&sim_num_insn, sim_num_insn, NULL);
stat_reg_counter(sdb, "sim_num_refs",
"total number of loads and stores executed",
&sim_num_refs, 0, NULL);
stat_reg_int(sdb, "sim_elapsed_time",
"total simulation time in seconds",
&sim_elapsed_time, 0, NULL);
stat_reg_formula(sdb, "sim_inst_rate",
"simulation speed (in insts/sec)",
"sim_num_insn / sim_elapsed_time", NULL);
/* this is a*/
stat_reg_counter(sdb, "sim_num_icache_miss", "total number of instruction cache misses", &g_icache_miss, 0, NULL);
stat_reg_formula(sdb, "sim_icache_miss_rate", "instruction cache miss rate (percentage)", "100*(sim_num_icache_miss / sim_num_insn)", NULL);
stat_reg_counter(sdb, "sim_num_icache_miss_aii", "total number of instruction cache misses aii", &g_icache_miss_aii, 0, NULL);
stat_reg_formula(sdb, "sim_icache_miss_rate_aii", "instruction cache miss rate aii (percentage)", "100*(sim_num_icache_miss_aii / sim_num_insn)", NULL);
/*B*/
stat_reg_counter(sdb, "sim_num_load_total", "total number of load", &g_load_total, 0, NULL);
stat_reg_counter(sdb, "sim_num_load_miss", "total number of load miss", &g_load_miss, 0, NULL);
stat_reg_formula(sdb, "sim_load", "load miss rate (percentage)", "100*(sim_num_load_miss / sim_num_load_total)", NULL);
stat_reg_counter(sdb, "sim_num_store_total", "total number of store", &g_store_total, 0, NULL);
stat_reg_counter(sdb, "sim_num_store_miss", "total number of store miss", &g_store_miss, 0, NULL);
stat_reg_formula(sdb, "sim_store", "store miss rate (percentage)", "100*(sim_num_store_miss / sim_num_store_total)", NULL);
stat_reg_counter(sdb, "sim_writeback", "total number of writeback", &g_writeback, 0, NULL);
stat_reg_formula(sdb, "sim_wb_ratio", "writeback to store ratio", "(sim_writeback / sim_num_store_total)", NULL);
// stat_reg_formula(sdb, "sim_icache_miss_rate_aii", "instruction cache miss rate aii (percentage)", "100*(sim_num_icache_miss_aii / sim_num_insn)", NULL);
ld_reg_stats(sdb);
mem_reg_stats(mem, sdb);
}
/* register simulator-specific statistics */
void
sim_reg_stats(struct stat_sdb_t *sdb) /* stats database */
{
int i;
/* register baseline stats */
stat_reg_counter(sdb, "sim_num_insn",
"total number of instructions executed",
&sim_num_insn, sim_num_insn, NULL);
stat_reg_counter(sdb, "sim_num_refs",
"total number of loads and stores executed",
&sim_num_refs, 0, NULL);
stat_reg_int(sdb, "sim_elapsed_time",
"total simulation time in seconds",
&sim_elapsed_time, 0, NULL);
stat_reg_formula(sdb, "sim_inst_rate",
"simulation speed (in insts/sec)",
"sim_num_insn / sim_elapsed_time", NULL);
/* register cache stats */
if (cache_il1
&& (cache_il1 != cache_dl1 && cache_il1 != cache_dl2))
cache_reg_stats(cache_il1, sdb);
if (cache_il2
&& (cache_il2 != cache_dl1 && cache_il2 != cache_dl2))
cache_reg_stats(cache_il2, sdb);
if (cache_dl1)
cache_reg_stats(cache_dl1, sdb);
if (cache_dl2)
cache_reg_stats(cache_dl2, sdb);
if (itlb)
cache_reg_stats(itlb, sdb);
if (dtlb)
cache_reg_stats(dtlb, sdb);
for (i=0; i<pcstat_nelt; i++)
{
char buf[512], buf1[512];
struct stat_stat_t *stat;
/* track the named statistical variable by text address */
/* find it... */
stat = stat_find_stat(sdb, pcstat_vars[i]);
if (!stat)
fatal("cannot locate any statistic named `%s'", pcstat_vars[i]);
/* stat must be an integral type */
if (stat->sc != sc_int && stat->sc != sc_uint && stat->sc != sc_counter)
fatal("`-pcstat' statistical variable `%s' is not an integral type",
stat->name);
/* register this stat */
pcstat_stats[i] = stat;
pcstat_lastvals[i] = STATVAL(stat);
/* declare the sparce text distribution */
sprintf(buf, "%s_by_pc", stat->name);
sprintf(buf1, "%s (by text address)", stat->desc);
pcstat_sdists[i] = stat_reg_sdist(sdb, buf, buf1,
/* initial value */0,
/* print fmt */(PF_COUNT|PF_PDF),
/* format */"0x%p %u %.2f",
/* print fn */NULL);
}
ld_reg_stats(sdb);
mem_reg_stats(mem, sdb);
}
/* register cache stats */
void
cache_reg_stats(struct cache_t *cp, /* cache instance */
struct stat_sdb_t *sdb) /* stats database */
{
char buf[512], buf1[512], *name;
/* get a name for this cache */
if (!cp->name || !cp->name[0])
name = "<unknown>";
else
name = cp->name;
sprintf(buf, "%s.accesses", name);
sprintf(buf1, "%s.hits + %s.misses", name, name);
stat_reg_formula(sdb, buf, "total number of accesses", buf1, "%12.0f");
sprintf(buf, "%s.hits", name);
stat_reg_counter(sdb, buf, "total number of hits", &cp->hits, 0, NULL);
sprintf(buf, "%s.misses", name);
stat_reg_counter(sdb, buf, "total number of misses", &cp->misses, 0, NULL);
sprintf(buf, "%s.replacements", name);
stat_reg_counter(sdb, buf, "total number of replacements",
&cp->replacements, 0, NULL);
sprintf(buf, "%s.writebacks", name);
stat_reg_counter(sdb, buf, "total number of writebacks",
&cp->writebacks, 0, NULL);
sprintf(buf, "%s.invalidations", name);
stat_reg_counter(sdb, buf, "total number of invalidations",
&cp->invalidations, 0, NULL);
sprintf(buf, "%s.miss_rate", name);
sprintf(buf1, "%s.misses / %s.accesses", name, name);
stat_reg_formula(sdb, buf, "miss rate (i.e., misses/ref)", buf1, NULL);
sprintf(buf, "%s.repl_rate", name);
sprintf(buf1, "%s.replacements / %s.accesses", name, name);
stat_reg_formula(sdb, buf, "replacement rate (i.e., repls/ref)", buf1, NULL);
sprintf(buf, "%s.wb_rate", name);
sprintf(buf1, "%s.writebacks / %s.accesses", name, name);
stat_reg_formula(sdb, buf, "writeback rate (i.e., wrbks/ref)", buf1, NULL);
sprintf(buf, "%s.inv_rate", name);
sprintf(buf1, "%s.invalidations / %s.accesses", name, name);
stat_reg_formula(sdb, buf, "invalidation rate (i.e., invs/ref)", buf1, NULL);
sprintf(buf, "%s.read_accesses", name);
sprintf(buf1, "%s.read_hits + %s.read_misses", name, name);
stat_reg_formula(sdb, buf, "total number of read accesses", buf1, "%12.0f");
sprintf(buf, "%s.read_hits", name);
stat_reg_counter(sdb, buf, "total number of read hits", &cp->read_hits, 0, NULL);
sprintf(buf, "%s.read_misses", name);
stat_reg_counter(sdb, buf, "total number of read misses", &cp->read_misses, 0, NULL);
sprintf(buf, "%s.read_miss_rate", name);
sprintf(buf1, "%s.read_misses / %s.read_accesses", name, name);
stat_reg_formula(sdb, buf, "read miss rate", buf1, NULL);
/* ECE552 Assignment 4 - BEGIN CODE */
sprintf(buf, "%s.prefetch_accuracy", name);
sprintf(buf1, "%s.prefetch_useful_cnt / %s.prefetch_cnt", name, name);
stat_reg_formula(sdb, buf, "accuracy of prefetch accesses", buf1, "%12.0f");
sprintf(buf, "%s.prefetch_cnt", name);
stat_reg_counter(sdb, buf, "total number of prefetches", &cp->prefetch_cnt, 0, NULL);
sprintf(buf, "%s.prefetch_useful_cnt", name);
stat_reg_counter(sdb, buf, "total number of useful prefetches", &cp->prefetch_useful_cnt, 0, NULL);
sprintf(buf, "%s.prefetch_misses", name);
stat_reg_counter(sdb, buf, "total number of misses caused by prefetch evictions", &cp->prefetch_misses, 0, NULL);
/* ECE552 Assignment 4 - END CODE */
}
/* register simulator-specific statistics */
void
sim_reg_stats(struct stat_sdb_t *sdb)
{
stat_reg_counter(sdb, "sim_num_insn",
"total number of instructions executed",
&sim_num_insn, sim_num_insn, NULL);
stat_reg_counter(sdb, "sim_num_refs",
"total number of loads and stores executed",
&sim_num_refs, 0, NULL);
stat_reg_int(sdb, "sim_elapsed_time",
"total simulation time in seconds",
&sim_elapsed_time, 0, NULL);
stat_reg_formula(sdb, "sim_inst_rate",
"simulation speed (in insts/sec)",
"sim_num_insn / sim_elapsed_time", NULL);
/* ECE552 Assignment 1 - BEGIN CODE */
stat_reg_counter(sdb, "sim_num_RAW_hazard_q1",
"total number of RAW hazards (q1)",
&sim_num_RAW_hazard_q1, sim_num_RAW_hazard_q1, NULL);
stat_reg_counter(sdb, "sim_num_one_cycle_hazard_q1",
"total one cycle hazard q1",
&sim_num_one_cycle_hazard_q1, sim_num_one_cycle_hazard_q1, NULL);
stat_reg_counter(sdb, "sim_num_two_cycle_hazard_q1",
"total two cycle hazard q1",
&sim_num_two_cycle_hazard_q1, sim_num_two_cycle_hazard_q1, NULL);
stat_reg_counter(sdb, "sim_num_one_cycle_hazard_q2",
"total one cycle hazard q2",
&sim_num_one_cycle_hazard_q2, sim_num_one_cycle_hazard_q2, NULL);
stat_reg_counter(sdb, "sim_num_two_cycle_hazard_q2",
"total two cycle hazard q2",
&sim_num_two_cycle_hazard_q2, sim_num_two_cycle_hazard_q2, NULL);
stat_reg_counter(sdb, "sim_num_one_cycle_hazard_q3",
"total one cycle hazard q3",
&sim_num_one_cycle_hazard_q3, sim_num_one_cycle_hazard_q3, NULL);
stat_reg_counter(sdb, "sim_num_two_cycle_hazard_q3",
"total two cycle hazard q3",
&sim_num_two_cycle_hazard_q3, sim_num_two_cycle_hazard_q3, NULL);
stat_reg_counter(sdb, "sim_num_RAW_hazard_q2",
"total number of RAW hazards (q2)",
&sim_num_RAW_hazard_q2, sim_num_RAW_hazard_q2, NULL);
stat_reg_counter(sdb, "sim_num_WAW_hazard_q3",
"total number of WAW hazards (q3)",
&sim_num_WAW_hazard_q3, sim_num_WAW_hazard_q3, NULL);
/* These are structural hazards occuring when two instructions **without** a WAW dependence
try to do the WriteBack in the same cycle. The latest instruction should stall.
*/
stat_reg_counter(sdb, "sim_num_structural_hazard_q3",
"total number of structural hazards (q3)",
&sim_num_structural_hazard_q3, sim_num_structural_hazard_q3, NULL);
stat_reg_formula(sdb, "CPI_from_RAW_hazard_q1",
"CPI from RAW hazard (q1)",
"1 + (sim_num_one_cycle_hazard_q1/sim_num_insn)+ ((sim_num_two_cycle_hazard_q1/sim_num_insn)*2)", NULL);
stat_reg_formula(sdb, "CPI_from_RAW_hazard_q2",
"CPI from RAW hazard (q2)",
"1 + (sim_num_one_cycle_hazard_q2/sim_num_insn) + ((sim_num_two_cycle_hazard_q2/sim_num_insn)*2)", NULL);
/* Include both WAW and structural hazards in your CPI computation */
stat_reg_formula(sdb, "CPI_from_WAW_and_Structural_hazard_q3",
"CPI from WAW and structural hazards (q3)",
"1 + ((sim_num_one_cycle_hazard_q3 + sim_num_structural_hazard_q3)/sim_num_insn) + ((sim_num_two_cycle_hazard_q3/sim_num_insn)*2)", NULL);
/* ECE552 Assignment 1 - END CODE */
ld_reg_stats(sdb);
mem_reg_stats(mem, sdb);
}
void
main(void)
{
struct stat_sdb_t *sdb;
struct stat_stat_t *stat, *stat1, *stat2, *stat3, *stat4, *stat5;
int an_int;
unsigned int a_uint;
float a_float;
double a_double;
static char *my_imap[8] = {
"foo", "bar", "uxxe", "blah", "gaga", "dada", "mama", "googoo"
};
/* make stats database */
sdb = stat_new();
/* register stat variables */
stat_reg_int(sdb, "stat.an_int", "An integer stat variable.",
&an_int, 1, NULL);
stat_reg_uint(sdb, "stat.a_uint", "An unsigned integer stat variable.",
&a_uint, 2, "%u (unsigned)");
stat_reg_float(sdb, "stat.a_float", "A float stat variable.",
&a_float, 3, NULL);
stat_reg_double(sdb, "stat.a_double", "A double stat variable.",
&a_double, 4, NULL);
stat_reg_formula(sdb, "stat.a_formula", "A double stat formula.",
"stat.a_float / stat.a_uint", NULL);
stat_reg_formula(sdb, "stat.a_formula1", "A double stat formula #1.",
"2 * (stat.a_formula / (1.5 * stat.an_int))", NULL);
stat_reg_formula(sdb, "stat.a_bad_formula", "A double stat formula w/error.",
"stat.a_float / (stat.a_uint - 2)", NULL);
stat = stat_reg_dist(sdb, "stat.a_dist", "An array distribution.",
0, 8, 1, PF_ALL, NULL, NULL, NULL);
stat1 = stat_reg_dist(sdb, "stat.a_dist1", "An array distribution #1.",
0, 8, 4, PF_ALL, NULL, NULL, NULL);
stat2 = stat_reg_dist(sdb, "stat.a_dist2", "An array distribution #2.",
0, 8, 1, (PF_PDF|PF_CDF), NULL, NULL, NULL);
stat3 = stat_reg_dist(sdb, "stat.a_dist3", "An array distribution #3.",
0, 8, 1, PF_ALL, NULL, my_imap, NULL);
stat4 = stat_reg_sdist(sdb, "stat.a_sdist", "A sparse array distribution.",
0, PF_ALL, NULL, NULL);
stat5 = stat_reg_sdist(sdb, "stat.a_sdist1",
"A sparse array distribution #1.",
0, PF_ALL, "0x%08lx %10lu %6.2f %6.2f",
NULL);
/* print initial stats */
fprintf(stdout, "** Initial stats...\n");
stat_print_stats(sdb, stdout);
/* adjust stats */
an_int++;
a_uint++;
a_float *= 2;
a_double *= 4;
stat_add_sample(stat, 8);
stat_add_sample(stat, 8);
stat_add_sample(stat, 1);
stat_add_sample(stat, 3);
stat_add_sample(stat, 4);
stat_add_sample(stat, 4);
stat_add_sample(stat, 7);
stat_add_sample(stat1, 32);
stat_add_sample(stat1, 32);
stat_add_sample(stat1, 1);
stat_add_sample(stat1, 12);
stat_add_sample(stat1, 17);
stat_add_sample(stat1, 18);
stat_add_sample(stat1, 30);
stat_add_sample(stat2, 8);
stat_add_sample(stat2, 8);
stat_add_sample(stat2, 1);
stat_add_sample(stat2, 3);
stat_add_sample(stat2, 4);
stat_add_sample(stat2, 4);
stat_add_sample(stat2, 7);
stat_add_sample(stat3, 8);
stat_add_sample(stat3, 8);
stat_add_sample(stat3, 1);
stat_add_sample(stat3, 3);
stat_add_sample(stat3, 4);
stat_add_sample(stat3, 4);
stat_add_sample(stat3, 7);
stat_add_sample(stat4, 800);
stat_add_sample(stat4, 800);
stat_add_sample(stat4, 1123);
stat_add_sample(stat4, 3332);
stat_add_sample(stat4, 4000);
stat_add_samples(stat4, 4001, 18);
stat_add_sample(stat4, 7);
stat_add_sample(stat5, 800);
stat_add_sample(stat5, 800);
stat_add_sample(stat5, 1123);
stat_add_sample(stat5, 3332);
stat_add_sample(stat5, 4000);
stat_add_samples(stat5, 4001, 18);
stat_add_sample(stat5, 7);
/* print final stats */
fprintf(stdout, "** Final stats...\n");
stat_print_stats(sdb, stdout);
/* all done */
stat_delete(sdb);
exit(0);
}
/* *************************** OPTICAL_STATISTICS.C ****************************/
void optical_reg_stats (struct opt_odb_t *sdb)
{
int i = 0;
stat_reg_counter (sdb, "meta_conflict_pro", "total meta conflict event", &meta_conflict_pro, 0, NULL);
stat_reg_counter (sdb, "data_conflict_pro", "total data conflict event", &data_conflict_pro, 0, NULL);
stat_reg_counter (sdb, "large_retry", "retry using even probability", &large_retry, 0, NULL);
stat_reg_counter (sdb, "small_retry", "retry using uneven probability", &small_retry, 0, NULL);
stat_reg_counter (sdb, "extra_input_buffer_overflow", "total number of extra overflow in inputbuffer", &input_extra_overflow, 0, NULL);
stat_reg_counter (sdb, "total_req_msg", "total request messages in network", &meta_packets, 0, NULL);
stat_reg_counter (sdb, "total_data_msg", "total data messages in network", &data_packets, 0, NULL);
stat_reg_counter (sdb, "total_req_msg_sending", "total request messages sending in network", &meta_packet_transfer, 0, NULL);
stat_reg_counter (sdb, "total_data_msg_sending", "total data messages sending in network", &data_packet_transfer, 0, NULL);
stat_reg_counter (sdb, "total_conf_ack_msg", "total acknowledgement in confirmation bits messages in network", &conf_ack_packets, 0, NULL);
stat_reg_counter (sdb, "total_conf_ack_read_msg", "total acknowledgement in confirmation bits messages in network", &conf_ack_packets_read, 0, NULL);
stat_reg_counter (sdb, "total_conf_upgrades_msg", "total upgrades messages in confirmation bits including final ack and ack_dir_upgrades", &conf_upgrades, 0, NULL);
stat_reg_counter (sdb, "total_conf_readupgrades_msg", "total read upgrades messages in confirmation bits including final ack and ack_dir_upgrades", &conf_readupgrades, 0, NULL);
stat_reg_counter (sdb, "total_conf_sync_lock", "total sync locks messages in confirmation bits", &conf_sync_lock, 0, NULL);
stat_reg_counter (sdb, "total_acknowledge_msg", "total acknowledgement not in confirmation bits messages in network", &acknowledge_packets, 0, NULL);
/* wb split statistics */
stat_reg_counter (sdb, "total_wb_conflict_event", "total wb conflicts event in network", &wb_split_conf_event, 0, NULL);
stat_reg_counter (sdb, "total_wb_conf", "total wb conflicts event in network", &WbSplitConf, 0, NULL);
stat_reg_counter (sdb, "total_wb_failconf", "total wb conflicts event in network", &WbSplitFailConf, 0, NULL);
stat_reg_counter (sdb, "total_wb_msg", "total write back messages", &total_wb_msg, 0, NULL);
stat_reg_counter (sdb, "total_wbhead_msg", "total write back head messages", &total_wbhead_msg, 0, NULL);
stat_reg_counter (sdb, "total_wb_head_success", "total wb header messages", &total_wb_head_success, 0, NULL);
stat_reg_counter (sdb, "total_wb_head_fail", "total wb header conflict", &total_wb_head_fail, 0, NULL);
stat_reg_counter (sdb, "total_wbreq_confirmation", "total wb invitation using confirmation", &total_wbreq_confirmation, 0, NULL);
stat_reg_counter (sdb, "total_wbreq_convention", "total wb invitation using conventional packets", &total_wbreq_convention, 0, NULL);
stat_reg_counter (sdb, "total_wb_req_convention_success", "total wb invitation using conventional packets successfully", &total_wb_req_convention_success, 0, NULL);
stat_reg_counter (sdb, "total_wb_req_convention_fail_event", "total wb invitation conflict event", &total_wb_req_convention_fail_event, 0, NULL);
stat_reg_counter (sdb, "total_wb_req_convention_fail_time", "total wb invitation conflict time", &total_wb_req_convention_fail_time, 0, NULL);
stat_reg_counter (sdb, "bit_overflow", "wb split using confirmation bits overflow", &bit_overflow, 0, NULL);
stat_reg_counter (sdb, "bit_used", "wb split using confirmation bits overflow", &bit_used, 0, NULL);
stat_reg_counter (sdb, "wb_close", "wb split invitation is close to other meta packet", &wb_close, 0, NULL);
/* mem split statistics */
stat_reg_counter (sdb, "total_mem_conflict_event", "total mem conflicts event in network", &mem_split_conf_event, 0, NULL);
stat_reg_counter (sdb, "total_mem_conf", "total mem conflicts event in network", &MemSplitConf, 0, NULL);
stat_reg_counter (sdb, "total_mem_failconf", "total mem conflicts event in network", &MemSplitFailConf, 0, NULL);
stat_reg_counter (sdb, "total_mem_msg", "total memory messages", &total_mem_msg, 0, NULL);
stat_reg_counter (sdb, "total_memhead_msg", "total memory head messages", &total_memhead_msg, 0, NULL);
stat_reg_counter (sdb, "total_mem_head_success", "total mem header messages", &total_mem_head_success, 0, NULL);
stat_reg_counter (sdb, "total_mem_head_fail", "total mem header conflict", &total_mem_head_fail, 0, NULL);
stat_reg_counter (sdb, "total_memreq_confirmation", "total mem invitation using confirmation", &total_memreq_confirmation, 0, NULL);
stat_reg_counter (sdb, "total_memreq_convention", "total mem invitation using conventional packets", &total_memreq_convention, 0, NULL);
stat_reg_counter (sdb, "total_mem_req_convention_success", "total mem invitation using conventional packets successfully", &total_mem_req_convention_success, 0, NULL);
stat_reg_counter (sdb, "total_mem_req_convention_fail_event", "total mem invitation conflict event", &total_mem_req_convention_fail_event, 0, NULL);
stat_reg_counter (sdb, "total_mem_req_convention_fail_time", "total mem invitation conflict time", &total_mem_req_convention_fail_time, 0, NULL);
/* power statistics */
stat_reg_counter (sdb, "laser_power_switch_off", "total numbers of laser power is switch off", &laser_power_switchoff_counter, 0, NULL);
stat_reg_counter (sdb, "laser_power_on_cycle", "total cycles of laser power on", &total_cycle_laser_power_on, 0, NULL);
stat_reg_counter (sdb, "laser_power_switch_on", "total numbers of laser power is switch on", &laser_power_switchon_counter, 0, NULL);
stat_reg_counter (sdb, "laser_conf_power_switch_off", "total numbers of laser power is switch off", &conf_laser_power_switchoff_counter, 0, NULL);
stat_reg_counter (sdb, "laser_conf_power_on_cycle", "total cycles of laser power on", &total_cycle_conf_laser_power_on, 0, NULL);
stat_reg_counter (sdb, "laser_conf_power_switch_on", "total numbers of laser power is switch on", &conf_laser_power_switchon_counter, 0, NULL);
stat_reg_counter (sdb, "laser_direction_switch", "total times of laser steering is required", &laser_direction_switch_counter, 0, NULL);
stat_reg_counter (sdb, "flits_transmit", "total numbers of flits transmittion", &flits_transmit_counter, 0, NULL);
stat_reg_counter (sdb, "flits_receiving", "total numbers of flits are receiving", &flits_receiving_counter, 0, NULL);
#ifdef CONF_PREDICTOR
stat_reg_counter (sdb, "wb_retry_conf", "", &wb_retry_conf, 0, NULL);
stat_reg_counter (sdb, "MaxReqPending", "", &MaxReqPending, 0, NULL);
stat_reg_counter (sdb, "predict_correct", "", &predict_correct, 0, NULL);
stat_reg_counter (sdb, "predict_fail", "", &predict_fail, 0, NULL);
stat_reg_counter (sdb, "hint_received_wrong", "", &hint_received_wrong, 0, NULL);
stat_reg_counter (sdb, "hint_receive", "", &hint_received, 0, NULL);
stat_reg_counter (sdb, "packet_conf_hint_conf", "", &packet_conf_hint_conf, 0, NULL);
stat_reg_counter (sdb, "packet_conf_hint_suc", "", &packet_conf_hint_suc, 0, NULL);
stat_reg_counter (sdb, "MultiPendingError", "", &MultiPendingError, 0, NULL);
stat_reg_counter (sdb, "WbPendingError", "", &WbPendingError, 0, NULL);
stat_reg_counter (sdb, "ReqPendingError", "", &ReqPendingError, 0, NULL);
stat_reg_counter (sdb, "ReqPendingError2", "", &ReqPendingError2, 0, NULL);
stat_reg_formula (sdb, "PredErrorRate", "", "predict_correct / (predict_fail + predict_correct)", /* format */ NULL);
stat_reg_formula (sdb, "WbErrorRate", "", "WbPendingError / predict_fail", /* format */ NULL);
stat_reg_formula (sdb, "MultiPendingErrorRate", "", "MultiPendingError / predict_fail", /* format */ NULL);
stat_reg_counter (sdb, "tencase", "", &tencase, 0, NULL);
#endif
/* network delay statistics */
#ifdef CONF_RES_ACK
stat_reg_counter (sdb, "data_conflict_packet_num", "total numbers of data packet in confliction", &data_conflict_packet_num, 0, NULL);
stat_reg_counter (sdb, "meta_conflict_packet_num", "total numbers of meta packet in confliction", &meta_conflict_packet_num, 0, NULL);
stat_reg_counter (sdb, "mem_data_conflict", "total numbers of mem refill data packet in confliction", &mem_data_conflict, 0, NULL);
stat_reg_counter (sdb, "mem_req_conflict", "total numbers of mem refill req packet in confliction", &mem_req_conflict, 0, NULL);
stat_reg_counter (sdb, "data_retry_packet_num", "total times of data packet retry", &data_retry_packet_num, 0, NULL);
stat_reg_counter (sdb, "meta_retry_packet_num", "total times of meta packet retry", &meta_retry_packet_num, 0, NULL);
stat_reg_counter (sdb, "mem_data_retry", "total numbers of mem refill data packet in confliction", &mem_data_retry, 0, NULL);
stat_reg_counter (sdb, "mem_req_retry", "total numbers of mem refill req packet in confliction", &mem_req_retry, 0, NULL);
stat_reg_counter (sdb, "pending_packet_num", "total numbers of pending packet", &pending_packet_num, 0, NULL);
stat_reg_counter (sdb, "conflict_delay", "total delay of confliction", &confliction_delay, 0, NULL);
stat_reg_counter (sdb, "data_confliction_delay", "total delay of data confliction", &data_confliction_delay, 0, NULL);
stat_reg_counter (sdb, "meta_confliction_delay", "total delay of meta confliction", &meta_confliction_delay, 0, NULL);
stat_reg_counter (sdb, "pending_delay", "total delay of pending packet", &pending_delay, 0, NULL);
#endif
/* conflict reason */
stat_reg_counter (sdb, "MemPckConfEvent", "Conflict event due to memory packets", &MemPckConfEvent, 0, NULL);
stat_reg_counter (sdb, "MemSecPckConfEvent", "Conflict event due to memory packets", &MemSecPckConfEvent, 0, NULL);
stat_reg_counter (sdb, "WriteBackConfEvent", "Conflict event due to Write back packets", &WriteBackConfEvent, 0, NULL);
stat_reg_counter (sdb, "RetransmissionConfEvent", "Conflict event due to Retransmission packets", &RetransmissionConfEvent, 0, NULL);
stat_reg_counter (sdb, "ReplyConfEvent", "Conflict event due to reply packets", &ReplyConfEvent, 0, NULL);
stat_reg_counter (sdb, "retry conflict", "conflict with retry packets", &retry_conflict, 0, NULL);
stat_reg_counter (sdb, "L2_miss_conflict", "conflict due to L2 miss", &L2_miss_conflict, 0, NULL);
stat_reg_counter (sdb, "all_L2miss_conflict", "conflict due to L2 miss (all the packets involved in a conflict", &all_L2_miss_conflict, 0, NULL);
stat_reg_counter (sdb, "L2_dirty_conflict", "conflict due to L2 dirty", &L2_dirty_conflict, 0, NULL);
stat_reg_counter (sdb, "queue_delay_conflict", "conflict due to queue delay (overall)", &queue_delay_conflict, 0, NULL);
stat_reg_counter (sdb, "L1_L2_conflict", "conflict due to L1 and L2 (L1 and L2 data reply conflict)", &L1_L2_conflict, 0, NULL);
stat_reg_counter (sdb, "l2_fifo_conflict", "conflict due to L2 fifo conflict", &l2_fifo_conflict, 0, NULL);
stat_reg_counter (sdb, "request_close_conflict", "conflict due to request close to each other", &request_close_conflict, 0, NULL);
stat_reg_counter (sdb, "wrong_conflict", "wrong conflict (should be request closed)", &wrong_conflict, 0, NULL);
stat_reg_counter (sdb, "queue_conflict", "conflict due to queue delay", &queue_conflict, 0, NULL);
stat_reg_counter (sdb, "steering_queue_conflict", "conflict due to steering delay", &steering_queue_conflict, 0, NULL);
stat_reg_counter (sdb, "fifo_queue_steering_conflict", "conflict due to all the factors", &fifo_queue_steering_conflict, 0, NULL);
stat_reg_counter (sdb, "laser_switch_on_delay", "total delay of laser warmup", &laser_switch_on_delay, 0, NULL);
stat_reg_counter (sdb, "network_delay_in_fiber", "total network delay in fiber", &network_delay_in_fiber, 0, NULL);
stat_reg_counter (sdb, "steering_delay", "total delay of laser steering", &steering_delay, 0, NULL);
stat_reg_counter (sdb, "net_work_queue_delay", "total delay due to the queue effect", &network_queue_delay, 0, NULL);
stat_reg_counter (sdb, "output_queue_delay", "total delay due to the queue effect", &output_queue_delay, 0, NULL);
stat_reg_counter (sdb, "no_queue_delay", "total number of data packets without queue delay", &no_queue_delay, 0, NULL);
stat_reg_counter (sdb, "data_network_queue_delay", "total data delay due to the queue effect", &data_network_queue_delay, 0, NULL);
stat_reg_counter (sdb, "meta_network_queue_delay", "total meta delay due to the queue effect", &meta_network_queue_delay, 0, NULL);
stat_reg_counter (sdb, "timeslot_wait_delay", "total delay due to data channel time slot", ×lot_wait_time, 0, NULL);
stat_reg_counter (sdb, "meta_wait_delay", "total delay due to meta channel time slot", &meta_timeslot_wait_time, 0, NULL);
stat_reg_counter (sdb, "wbreq_wait_delay", "total delay due to wb req time slot", &wbreq_timeslot_wait_time, 0, NULL);
stat_reg_counter (sdb, "reply_data_packets", "total data packets which are reply", &reply_data_packets, 0, NULL);
stat_reg_counter (sdb, "original_replydata_packets", "total data packets which are reply", &original_reply_data_packets, 0, NULL);
stat_reg_counter (sdb, "write_back_packets", "total data packets which are write back", &write_back_packets, 0, NULL);
stat_reg_counter (sdb, "no_write_back", "total data packets which are write back", &no_write_back, 0, NULL);
stat_reg_counter (sdb, "all_write_back", "total data packets which are write back", &all_write_back, 0, NULL);
stat_reg_counter (sdb, "partial_write_back", "total data packets which are write back", &partial_write_back, 0, NULL);
stat_reg_counter (sdb, "no_solution_pwb", "total data packets which are write back", &no_solution_pwb, 0, NULL);
stat_reg_counter (sdb, "original_writeback_packets", "total data packets which are write back", &original_write_back_packets, 0, NULL);
stat_reg_counter (sdb, "data_retry_queue", "total retried data packets queued", &retry_data_queue, 0, NULL);
stat_reg_counter (sdb, "meta_retry_queue", "total retried meta packets queued", &retry_meta_queue, 0, NULL);
stat_reg_counter (sdb, "max_conflict_involves", "maximum packets involves in one conflict", &max_conf, 0, NULL);
stat_reg_counter (sdb, "max_packet_retry", "maximum number packets retry", &max_packet_retry, 0, NULL);
stat_reg_counter (sdb, "max_packets_inbuffer", "maximum number packets in the input buffer", &max_packets_inbuffer, 0, NULL);
stat_reg_counter (sdb, "max_flits_inbuffer", "maximum number flits in the input buffer", &max_flits_inbuffer, 0, NULL);
stat_reg_counter (sdb, "meta_delay_packets", "number of meta packets delay", &meta_delay_packets, 0, NULL);
stat_reg_counter (sdb, "wbreq_delay_packets", "number of meta packets delay", &wbreq_delay_packets, 0, NULL);
stat_reg_counter (sdb, "meta_l1_delay_packets", "number of meta packets delay", &meta_l1_delay_packets, 0, NULL);
stat_reg_counter (sdb, "meta_packets_forward", "number of meta packets forward", &meta_packets_forward, 0, NULL);
stat_reg_counter (sdb, "data_packets_forward", "number of data packets forward", &data_packets_forward, 0, NULL);
stat_reg_counter (sdb, "RTCC", "data_conflict due to Request Time Close to each other Counter", &RTCC, 0, NULL);
stat_reg_counter (sdb, "RTC_C_miss", "data_conflict due to Request Time Close to each other Counter", &RTCC_miss, 0, NULL);
stat_reg_counter (sdb, "RTC_C_half", "data_conflict due to Request Time Close to half Counter", &RTCC_half, 0, NULL);
stat_reg_counter (sdb, "RTC_C_fail", "data_conflict due to Request Time Close failed counter", &RTCC_fail, 0, NULL);
stat_reg_counter (sdb, "RTC_counter_reduced", "data_conflict due to Request Time Close to each other Counter", &RTCC_reduced, 0, NULL);
stat_reg_counter (sdb, "meta_reduced_packets", "Request Time Close to each other Counter", &meta_reduced_packets, 0, NULL);
stat_reg_counter (sdb, "meta_close_packets", "Request Time Close to each other Counter", &meta_close_packets, 0, NULL);
stat_reg_counter (sdb, "data_packets_delay", "data packets are actually delayed to avoid conflict", &data_packets_delay, 0, NULL);
stat_reg_counter (sdb, "data_packets_no_delay", "data packets are not delayed to avoid conflict", &data_packets_no_delay, 0, NULL);
stat_reg_counter (sdb, "data_delay", "data packets delay time", &data_delay, 0, NULL);
stat_reg_counter (sdb, "data_packet_generate_max", "data packets generation max per 100 cycles", &data_packet_generate_max, 0, NULL);
/* conflicts statistics */
stat_reg_counter (sdb, "data_sync_conf_event", "", &sync_conf_event, 0, NULL);
stat_reg_counter (sdb, "data_sync_conf_packets", "", &sync_conf_packets, 0, NULL);
stat_reg_counter (sdb, "meta_sync_conf_event,", "", &meta_sync_conf_event, 0, NULL);
stat_reg_counter (sdb, "meta_sync_conf_packets", "", &meta_sync_conf_packets, 0, NULL);
stat_reg_counter (sdb, "meta_ldl_conf_event,", "", &meta_ldl_conf_event, 0, NULL);
stat_reg_counter (sdb, "meta_ldl_conf_packets", "", &meta_ldl_conf_packets, 0, NULL);
stat_reg_counter (sdb, "max_queue_delay", "maximum queue delay", &max_queue_delay, 0, NULL);
stat_reg_counter (sdb, "more_than_Two_conflict", "", &more_than_two_conflict, 0, NULL);
stat_reg_counter (sdb, "meta_more_than_Two_conflict", "", &meta_more_than_two_conflict, 0, NULL);
stat_reg_counter (sdb, "meta_ldl_more_than_Two_conflict", "", &meta_ldl_more_than_two_conflict, 0, NULL);
int j = 0, m = 0;
/* for(i=0; i<(mesh_size+2)*(mesh_size+2)*2; i++)
{
for(j=0; j<(mesh_size+2)*(mesh_size+2); j++)
{
for(m=0; m<(mesh_size+2)*(mesh_size+2); m++)
{
char ch2[32];
sprintf(ch2, "data_queue_%d_%d_%d", i, j, m);
stat_reg_counter(sdb, ch2, "", &conflict_table[i][j][m], 0, NULL);
}
}
}
for(i=0; i<(mesh_size+2)*(mesh_size+2)*2; i++)
{
for(j=0; j<(mesh_size+2)*(mesh_size+2); j++)
{
for(m=0; m<(mesh_size+2)*(mesh_size+2); m++)
{
char ch3[32];
sprintf(ch3, "meta_queue_%d_%d_%d", i, j, m);
stat_reg_counter(sdb, ch3, "", &meta_conflict_table[i][j][m], 0, NULL);
char ch4[32];
sprintf(ch4, "meta_ldl_queue_%d_%d_%d", i, j, m);
stat_reg_counter(sdb, ch4, "", &meta_ldl_conflict_table[i][j][m], 0, NULL);
}
}
}*/
//
for(i=0; i<PROCESSOR; i++)
{
char ch2[32];
sprintf(ch2, "NetQueueDelay_%d", i);
stat_reg_counter(sdb, ch2, "", &network_queue_Delay[i], 0, /* format */NULL);
}
for(i=0; i<PROCESSOR; i++)
{
char ch2[32];
sprintf(ch2, "OutQueueDelay_%d", i);
stat_reg_counter(sdb, ch2, "", &output_queue_Delay[i], 0, /* format */NULL);
}
for(i=0; i<PROCESSOR; i++)
{
char ch2[32];
sprintf(ch2, "DataQueueDelay_%d", i);
stat_reg_counter(sdb, ch2, "", &data_network_queue_Delay[i], 0, /* format */NULL);
}
for(i=0; i<PROCESSOR; i++)
{
char ch2[32];
sprintf(ch2, "MetaQueueDelay_%d", i);
stat_reg_counter(sdb, ch2, "", &meta_network_queue_Delay[i], 0, /* format */NULL);
}
for(i=0; i<PROCESSOR; i++)
{
char ch2[32];
sprintf(ch2, "PendDelay_%d", i);
stat_reg_counter(sdb, ch2, "", &pending_Delay[i], 0, /* format */NULL);
}
for(i=0; i<PROCESSOR; i++)
{
char ch2[32];
sprintf(ch2, "SteerDelay_%d", i);
stat_reg_counter(sdb, ch2, "", &steering_Delay[i], 0, /* format */NULL);
}
for(i=0; i<PROCESSOR; i++)
{
char ch2[32];
sprintf(ch2, "DataColDelay_%d", i);
stat_reg_counter(sdb, ch2, "", &data_confliction_Delay[i], 0, /* format */NULL);
}
for(i=0; i<PROCESSOR; i++)
{
char ch2[32];
sprintf(ch2, "MetaColDelay_%d", i);
stat_reg_counter(sdb, ch2, "", &meta_confliction_Delay[i], 0, /* format */NULL);
}
for(i=0; i<PROCESSOR; i++)
{
char ch2[32];
sprintf(ch2, "LaserSDelay_%d", i);
stat_reg_counter(sdb, ch2, "", &laser_switch_on_Delay[i], 0, /* format */NULL);
}
for(i=0; i<PROCESSOR; i++)
{
char ch2[32];
sprintf(ch2, "TSDelay_%d", i);
stat_reg_counter(sdb, ch2, "", ×lot_wait_Delay[i], 0, /* format */NULL);
}
for(i=0; i<PROCESSOR; i++)
{
char ch2[32];
sprintf(ch2, "MetaTSlDelay_%d", i);
stat_reg_counter(sdb, ch2, "", &meta_timeslot_wait_Delay[i], 0, /* format */NULL);
}
for(i=0; i<24; i++)
{
char ch2[32];
sprintf(ch2, "queue_%d", i);
stat_reg_counter(sdb, ch2, "queue delay distribution", &queue_distr[i], 0, /* format */NULL);
}
for(i=0; i<20; i++)
{
char ch2[32];
sprintf(ch2, "distance_%d.bincount", i);
stat_reg_counter(sdb, ch2, "bincount for distance of sending two packets", &dist_bin[i], 0, /* format */NULL);
}
for(i=0; i<7; i++)
{
char ch2[32];
sprintf(ch2, "meta_%d_way_conf", i);
stat_reg_counter(sdb, ch2, "", &meta_way_conf[i], 0, /* format */NULL);
}
for(i=0; i<7; i++)
{
char ch2[32];
sprintf(ch2, "data_%d_way_conf", i);
stat_reg_counter(sdb, ch2, "", &data_way_conf[i], 0, /* format */NULL);
}
for(i=0; i<7; i++)
{
char ch2[32];
sprintf(ch2, "data_conf_inv%d.bincount", i);
stat_reg_counter(sdb, ch2, "bincount for packets involved in a conflict", &data_conf_inv_bincount[i], 0, /* format */NULL);
}
for(i=0; i<3; i++)
{
char ch2[32];
sprintf(ch2, "wb_conf_inv%d.bincount", i);
stat_reg_counter(sdb, ch2, "bincount for wb packets involves in a conflict", &write_back_inv_bincount[i], 0, /* format */NULL);
}
for(i=0; i<4; i++)
{
char ch2[32];
sprintf(ch2, "request_%d.conflict", i);
stat_reg_counter(sdb, ch2, "request conflict on destination per event", &req_conf[i], /* intital value */0, /* format */NULL);
}
for(i=0; i<4; i++)
{
char ch2[32];
sprintf(ch2, "data_%d.conflict", i);
stat_reg_counter(sdb, ch2, "data conflict on destination per event", &data_conf[i], /* intital value */0, /* format */NULL);
}
}
void
core_commit_IO_DPM_t::reg_stats(struct stat_sdb_t * const sdb)
{
char buf[1024];
char buf2[1024];
struct thread_t * arch = core->current_thread;
stat_reg_note(sdb,"\n#### COMMIT STATS ####");
sprintf(buf,"c%d.commit_bytes",arch->id);
stat_reg_counter(sdb, true, buf, "total number of bytes committed", &core->stat.commit_bytes, 0, TRUE, NULL);
sprintf(buf,"c%d.commit_insn",arch->id);
stat_reg_counter(sdb, true, buf, "total number of instructions committed", &core->stat.commit_insn, 0, TRUE, NULL);
sprintf(buf,"c%d.commit_uops",arch->id);
stat_reg_counter(sdb, true, buf, "total number of uops committed", &core->stat.commit_uops, 0, TRUE, NULL);
sprintf(buf,"c%d.commit_eff_uops",arch->id);
stat_reg_counter(sdb, true, buf, "total number of effective uops committed", &core->stat.commit_eff_uops, 0, TRUE, NULL);
sprintf(buf,"c%d.commit_BPC",arch->id);
sprintf(buf2,"c%d.commit_bytes/c%d.sim_cycle",arch->id,arch->id);
stat_reg_formula(sdb, true, buf, "BPC (bytes per cycle) at commit", buf2, NULL);
sprintf(buf,"c%d.commit_IPC",arch->id);
sprintf(buf2,"c%d.commit_insn/c%d.sim_cycle",arch->id,arch->id);
stat_reg_formula(sdb, true, buf, "IPC at commit", buf2, NULL);
sprintf(buf,"c%d.commit_uPC",arch->id);
sprintf(buf2,"c%d.commit_uops/c%d.sim_cycle",arch->id,arch->id);
stat_reg_formula(sdb, true, buf, "uPC at commit", buf2, NULL);
sprintf(buf,"c%d.commit_euPC",arch->id);
sprintf(buf2,"c%d.commit_eff_uops/c%d.sim_cycle",arch->id,arch->id);
stat_reg_formula(sdb, true, buf, "effective uPC at commit", buf2, NULL);
sprintf(buf,"c%d.commit_byte_per_inst",arch->id);
sprintf(buf2,"c%d.commit_bytes/c%d.commit_insn",arch->id,arch->id);
stat_reg_formula(sdb, true, buf, "average bytes per instruction", buf2, NULL);
sprintf(buf,"c%d.commit_byte_per_uop",arch->id);
sprintf(buf2,"c%d.commit_bytes/c%d.commit_uops",arch->id,arch->id);
stat_reg_formula(sdb, true, buf, "average bytes per uop", buf2, NULL);
sprintf(buf,"c%d.commit_byte_per_eff_uop",arch->id);
sprintf(buf2,"c%d.commit_bytes/c%d.commit_eff_uops",arch->id,arch->id);
stat_reg_formula(sdb, true, buf, "average bytes per effective uop", buf2, NULL);
sprintf(buf,"c%d.avg_commit_flowlen",arch->id);
sprintf(buf2,"c%d.commit_uops/c%d.commit_insn",arch->id,arch->id);
stat_reg_formula(sdb, true, buf, "uops per instruction at commit", buf2, NULL);
sprintf(buf,"c%d.avg_commit_eff_flowlen",arch->id);
sprintf(buf2,"c%d.commit_eff_uops/c%d.commit_insn",arch->id,arch->id);
stat_reg_formula(sdb, true, buf, "effective uops per instruction at commit", buf2, NULL);
sprintf(buf,"c%d.commit_fusions",arch->id);
stat_reg_counter(sdb, true, buf, "total number of fused uops committed", &core->stat.commit_fusions, 0, TRUE, NULL);
sprintf(buf,"c%d.commit_fusion_uops",arch->id);
sprintf(buf2,"(c%d.commit_eff_uops - c%d.commit_uops) + c%d.commit_fusions",arch->id,arch->id,arch->id);
stat_reg_formula(sdb, true, buf, "fused uops at commit", buf2, "%12.0f");
sprintf(buf,"c%d.commit_frac_fusion_uops",arch->id);
sprintf(buf2,"c%d.commit_fusion_uops / c%d.commit_eff_uops",arch->id,arch->id);
stat_reg_formula(sdb, true, buf, "fraction of effective uops fused at commit", buf2, NULL);
sprintf(buf,"c%d.commit_fusion_compression",arch->id);
sprintf(buf2,"(c%d.commit_eff_uops - c%d.commit_uops) / c%d.commit_eff_uops",arch->id,arch->id,arch->id);
stat_reg_formula(sdb, true, buf, "fraction of effective uops compressed via fusion at commit", buf2, NULL);
sprintf(buf,"c%d.commit_fusion_expansion",arch->id);
sprintf(buf2,"c%d.commit_eff_uops / c%d.commit_uops",arch->id,arch->id);
stat_reg_formula(sdb, true, buf, "average number of effective uops per uop (fused or standalone) commit", buf2, NULL);
sprintf(buf,"c%d.commit_dead_lock_flushes",arch->id);
stat_reg_counter(sdb, true, buf, "total number of pipe-flushes due to dead-locked pipeline", &core->stat.commit_deadlock_flushes, 0, FALSE, NULL);
sprintf(buf,"c%d.ROB_empty",arch->id);
sprintf(buf,"c%d.ROB_occupancy",arch->id);
stat_reg_counter(sdb, false, buf, "total ROB occupancy", &core->stat.ROB_occupancy, 0, TRUE, NULL);
sprintf(buf,"c%d.ROB_eff_occupancy",arch->id);
stat_reg_counter(sdb, false, buf, "total ROB effective_occupancy", &core->stat.ROB_eff_occupancy, 0, TRUE, NULL);
sprintf(buf,"c%d.ROB_empty",arch->id);
stat_reg_counter(sdb, false, buf, "total cycles ROB was empty", &core->stat.ROB_empty_cycles, 0, TRUE, NULL);
sprintf(buf,"c%d.ROB_full",arch->id);
stat_reg_counter(sdb, false, buf, "total cycles ROB was full", &core->stat.ROB_full_cycles, 0, TRUE, NULL);
sprintf(buf,"c%d.ROB_avg",arch->id);
sprintf(buf2,"c%d.ROB_occupancy/c%d.sim_cycle",arch->id,arch->id);
stat_reg_formula(sdb, true, buf, "average ROB occupancy", buf2, NULL);
sprintf(buf,"c%d.ROB_eff_avg",arch->id);
sprintf(buf2,"c%d.ROB_eff_occupancy/c%d.sim_cycle",arch->id,arch->id);
stat_reg_formula(sdb, true, buf, "average ROB effective occupancy", buf2, NULL);
sprintf(buf,"c%d.ROB_frac_empty",arch->id);
sprintf(buf2,"c%d.ROB_empty/c%d.sim_cycle",arch->id,arch->id);
stat_reg_formula(sdb, true, buf, "fraction of cycles ROB was empty", buf2, NULL);
sprintf(buf,"c%d.ROB_frac_full",arch->id);
sprintf(buf2,"c%d.ROB_full/c%d.sim_cycle",arch->id,arch->id);
stat_reg_formula(sdb, true, buf, "fraction of cycles ROB was full", buf2, NULL);
sprintf(buf,"c%d.DL1_store_split_accesses",arch->id);
stat_reg_counter(sdb, true, buf, "number of stores requiring split accesses", &core->stat.DL1_store_split_accesses, 0, TRUE, NULL);
sprintf(buf,"c%d.DL1_store_split_frac",arch->id);
sprintf(buf2,"c%d.DL1_store_split_accesses/(c%d.DL1.store_lookups-c%d.DL1_store_split_accesses)",arch->id,arch->id,arch->id); /* need to subtract since each split access generated two store accesses */
stat_reg_formula(sdb, true, buf, "fraction of stores requiring split accesses", buf2, NULL);
sprintf(buf,"c%d.commit_stall",core->current_thread->id);
core->stat.commit_stall = stat_reg_dist(sdb, buf,
"breakdown of stalls at commit",
/* initial value */0,
/* array size */CSTALL_num,
/* bucket size */1,
/* print format */(PF_COUNT|PF_PDF),
/* format */NULL,
/* index map */commit_stall_str,
/* scale_me */TRUE,
/* print fn */NULL);
stat_reg_note(sdb,"#### TIMING STATS ####");
sprintf(buf,"c%d.sim_cycle",arch->id);
stat_reg_qword(sdb, true, buf, "total number of cycles when last instruction (or uop) committed", (qword_t*) &core->stat.final_sim_cycle, 0, TRUE, NULL);
/* cumulative slip cycles (not printed) */
sprintf(buf,"c%d.Mop_fetch_Tslip",core->current_thread->id);
stat_reg_qword(sdb, false, buf, "total Mop fetch slip cycles", (qword_t*) &core->stat.Mop_fetch_slip, 0, TRUE, NULL);
sprintf(buf,"c%d.Mop_f2d_Tslip",core->current_thread->id);
stat_reg_qword(sdb, false, buf, "total Mop fetch-to-decode slip cycles", (qword_t*) &core->stat.Mop_fetch2decode_slip, 0, TRUE, NULL);
sprintf(buf,"c%d.Mop_decode_Tslip",core->current_thread->id);
stat_reg_qword(sdb, false, buf, "total Mop decode slip cycles", (qword_t*) &core->stat.Mop_decode_slip, 0, TRUE, NULL);
sprintf(buf,"c%d.uop_d2a_Tslip",core->current_thread->id);
stat_reg_qword(sdb, false, buf, "total uop decode-to-alloc slip cycles", (qword_t*) &core->stat.uop_decode2alloc_slip, 0, TRUE, NULL);
sprintf(buf,"c%d.uop_a2r_Tslip",core->current_thread->id);
stat_reg_qword(sdb, false, buf, "total uop alloc-to-ready slip cycles", (qword_t*) &core->stat.uop_alloc2ready_slip, 0, TRUE, NULL);
sprintf(buf,"c%d.uop_r2i_Tslip",core->current_thread->id);
stat_reg_qword(sdb, false, buf, "total uop ready-to-issue slip cycles", (qword_t*) &core->stat.uop_ready2issue_slip, 0, TRUE, NULL);
sprintf(buf,"c%d.uop_i2e_Tslip",core->current_thread->id);
stat_reg_qword(sdb, false, buf, "total uop issue-to-exec slip cycles", (qword_t*) &core->stat.uop_issue2exec_slip, 0, TRUE, NULL);
sprintf(buf,"c%d.uop_e2w_Tslip",core->current_thread->id);
stat_reg_qword(sdb, false, buf, "total uop exec-to-WB slip cycles", (qword_t*) &core->stat.uop_exec2complete_slip, 0, TRUE, NULL);
sprintf(buf,"c%d.uop_w2c_Tslip",core->current_thread->id);
stat_reg_qword(sdb, false, buf, "total uop WB-to-commit slip cycles", (qword_t*) &core->stat.uop_complete2commit_slip, 0, TRUE, NULL);
sprintf(buf,"c%d.Mop_d2c_Tslip",core->current_thread->id);
stat_reg_qword(sdb, false, buf, "total Mop decode-to-commit slip cycles", (qword_t*) &core->stat.Mop_decode2commit_slip, 0, TRUE, NULL);
sprintf(buf,"c%d.Mop_commit_Tslip",core->current_thread->id);
stat_reg_qword(sdb, false, buf, "total Mop commit slip cycles", (qword_t*) &core->stat.Mop_commit_slip, 0, TRUE, NULL);
/* average slip cycles */
sprintf(buf,"c%d.Mop_fetch_avg_slip",arch->id);
sprintf(buf2,"c%d.Mop_fetch_Tslip / (c%d.commit_insn - c%d.num_traps)",arch->id,arch->id,arch->id);
stat_reg_formula(sdb, true, buf, "Mop fetch average delay", buf2, NULL);
sprintf(buf,"c%d.Mop_f2d_avg_slip",arch->id);
sprintf(buf2,"c%d.Mop_f2d_Tslip / (c%d.commit_insn - c%d.num_traps)",arch->id,arch->id,arch->id);
stat_reg_formula(sdb, true, buf, "Mop fetch-to-decode average delay", buf2, NULL);
sprintf(buf,"c%d.Mop_decode_avg_slip",arch->id);
sprintf(buf2,"c%d.Mop_decode_Tslip / (c%d.commit_insn - c%d.num_traps)",arch->id,arch->id,arch->id);
stat_reg_formula(sdb, true, buf, "Mop decode average delay", buf2, NULL);
sprintf(buf,"c%d.uop_d2a_avg_slip",arch->id);
sprintf(buf2,"c%d.uop_d2a_Tslip / c%d.commit_uops",arch->id,arch->id);
stat_reg_formula(sdb, true, buf, "uop decode-to-alloc average delay", buf2, NULL);
sprintf(buf,"c%d.uop_a2r_avg_slip",arch->id);
sprintf(buf2,"c%d.uop_a2r_Tslip / c%d.commit_uops",arch->id,arch->id);
stat_reg_formula(sdb, true, buf, "uop alloc-to-ready average delay", buf2, NULL);
sprintf(buf,"c%d.uop_r2i_avg_slip",arch->id);
sprintf(buf2,"c%d.uop_r2i_Tslip / c%d.commit_uops",arch->id,arch->id);
stat_reg_formula(sdb, true, buf, "uop ready-to-issue average delay", buf2, NULL);
sprintf(buf,"c%d.uop_i2e_avg_slip",arch->id);
sprintf(buf2,"c%d.uop_i2e_Tslip / c%d.commit_uops",arch->id,arch->id);
stat_reg_formula(sdb, true, buf, "uop issue-to-exec average delay", buf2, NULL);
sprintf(buf,"c%d.uop_e2w_avg_slip",arch->id);
sprintf(buf2,"c%d.uop_e2w_Tslip / c%d.commit_uops",arch->id,arch->id);
stat_reg_formula(sdb, true, buf, "uop exec-to-WB average delay", buf2, NULL);
sprintf(buf,"c%d.uop_w2c_avg_slip",arch->id);
sprintf(buf2,"c%d.uop_w2c_Tslip / c%d.commit_uops",arch->id,arch->id);
stat_reg_formula(sdb, true, buf, "uop WB-to-commit average delay", buf2, NULL);
sprintf(buf,"c%d.Mop_d2c_avg_slip",arch->id);
sprintf(buf2,"c%d.Mop_d2c_Tslip / (c%d.commit_insn - c%d.num_traps)",arch->id,arch->id,arch->id);
stat_reg_formula(sdb, true, buf, "Mop decode-to-commit average delay", buf2, NULL);
sprintf(buf,"c%d.Mop_commit_avg_slip",arch->id);
sprintf(buf2,"c%d.Mop_commit_Tslip / (c%d.commit_insn - c%d.num_traps)",arch->id,arch->id,arch->id);
stat_reg_formula(sdb, true, buf, "Mop commit average delay", buf2, NULL);
sprintf(buf,"c%d.Mop_avg_end_to_end",arch->id);
sprintf(buf2,"c%d.Mop_fetch_avg_slip + c%d.Mop_f2d_avg_slip + c%d.Mop_d2c_avg_slip + c%d.Mop_commit_avg_slip",arch->id,arch->id,arch->id,arch->id);
stat_reg_formula(sdb, true, buf, "Mop average end-to-end pipeline delay", buf2, NULL);
/* instruction distribution stats */
stat_reg_note(sdb,"\n#### INSTRUCTION STATS (no wrong-path) ####");
sprintf(buf,"c%d.num_insn",arch->id);
sprintf(buf2,"c%d.commit_insn",arch->id);
stat_reg_formula(sdb, true, buf, "total number of instructions committed", buf2, NULL);
sprintf(buf,"c%d.num_refs",arch->id);
stat_reg_counter(sdb, true, buf, "total number of loads and stores committed", &core->stat.commit_refs, 0, TRUE, NULL);
sprintf(buf,"c%d.num_loads",arch->id);
stat_reg_counter(sdb, true, buf, "total number of loads committed", &core->stat.commit_loads, 0, TRUE, NULL);
sprintf(buf2,"c%d.num_refs - c%d.num_loads",arch->id,arch->id);
sprintf(buf,"c%d.num_stores",arch->id);
stat_reg_formula(sdb, true, buf, "total number of stores committed", buf2, "%12.0f");
sprintf(buf,"c%d.num_branches",arch->id);
stat_reg_counter(sdb, true, buf, "total number of branches committed", &core->stat.commit_branches, 0, TRUE, NULL);
sprintf(buf,"c%d.num_traps",arch->id);
stat_reg_counter(sdb, true, buf, "total number of traps committed", &core->stat.commit_traps, 0, TRUE, NULL);
sprintf(buf,"c%d.num_rep_insn",arch->id);
stat_reg_counter(sdb, true, buf, "total number of REP insts committed", &core->stat.commit_rep_insn, 0, TRUE, NULL);
sprintf(buf,"c%d.num_rep_iter",arch->id);
stat_reg_counter(sdb, true, buf, "total number of REP iterations committed", &core->stat.commit_rep_iterations, 0, TRUE, NULL);
sprintf(buf,"c%d.num_rep_uops",arch->id);
stat_reg_counter(sdb, true, buf, "total number of uops in REP insts committed", &core->stat.commit_rep_uops, 0, TRUE, NULL);
sprintf(buf,"c%d.num_avg_reps",arch->id);
sprintf(buf2,"c%d.num_rep_iter/c%d.num_rep_insn",arch->id,arch->id);
stat_reg_formula(sdb, true, buf, "average iterations per REP inst", buf2, "%12.2f");
sprintf(buf,"c%d.num_avg_rep_uops",arch->id);
sprintf(buf2,"c%d.num_rep_uops/c%d.num_rep_insn",arch->id,arch->id);
stat_reg_formula(sdb, true, buf, "average uops per REP inst", buf2, "%12.2f");
sprintf(buf,"c%d.num_UROM_insn",arch->id);
stat_reg_counter(sdb, true, buf, "total number of insn using the UROM committed", &core->stat.commit_UROM_insn, 0, TRUE, NULL);
sprintf(buf,"c%d.num_UROM_uops",arch->id);
stat_reg_counter(sdb, true, buf, "total number of uops using the UROM committed", &core->stat.commit_UROM_uops, 0, TRUE, NULL);
sprintf(buf,"c%d.num_UROM_eff_uops",arch->id);
stat_reg_counter(sdb, true, buf, "total number of effective uops using the UROM committed", &core->stat.commit_UROM_eff_uops, 0, TRUE, NULL);
sprintf(buf,"c%d.num_avg_UROM_uops",arch->id);
sprintf(buf2,"c%d.num_UROM_uops/c%d.num_UROM_insn",arch->id,arch->id);
stat_reg_formula(sdb, true, buf, "average uops per UROM inst", buf2, "%12.2f");
sprintf(buf,"c%d.avg_flowlen",arch->id);
sprintf(buf2,"c%d.commit_uops/c%d.commit_insn",arch->id,arch->id);
stat_reg_formula(sdb, true, buf, "average uops per instruction", buf2, NULL);
sprintf(buf,"c%d.avg_eff_flowlen",arch->id);
sprintf(buf2,"c%d.commit_eff_uops/c%d.commit_insn",arch->id,arch->id);
stat_reg_formula(sdb, true, buf, "average effective uops per instruction", buf2, NULL);
sprintf(buf,"c%d.regfile_writes",arch->id);
stat_reg_counter(sdb, true, buf, "number of register file writes", &core->stat.regfile_writes, 0, TRUE, NULL);
sprintf(buf,"c%d.fp_regfile_writes",arch->id);
stat_reg_counter(sdb, true, buf, "number of fp refister file writes", &core->stat.fp_regfile_writes, 0, TRUE, NULL);
sprintf(buf,"c%d.flow_lengths",core->current_thread->id);
core->stat.flow_histo = stat_reg_dist(sdb, buf,
"histogram of uop flow lengths",
/* initial value */0,
/* array size */FLOW_HISTO_SIZE,
/* bucket size */1,
/* print format */(PF_COUNT|PF_PDF),
/* format */NULL,
/* index map */NULL,
/* scale_me */TRUE,
/* print fn */NULL);
sprintf(buf,"c%d.eff_flow_lengths",core->current_thread->id);
core->stat.eff_flow_histo = stat_reg_dist(sdb, buf,
"histogram of effective uop flow lengths",
/* initial value */0,
/* array size */FLOW_HISTO_SIZE,
/* bucket size */1,
/* print format */(PF_COUNT|PF_PDF),
/* format */NULL,
/* index map */NULL,
/* scale_me */TRUE,
/* print fn */NULL);
}
/* register simulator-specific statistics */
void
sim_reg_stats(struct stat_sdb_t *sdb)
{
int i;
stat_reg_counter(sdb, "sim_num_insn",
"total number of instructions executed",
&sim_num_insn, sim_num_insn, NULL);
stat_reg_counter(sdb, "sim_num_refs",
"total number of loads and stores executed",
&sim_num_refs, 0, NULL);
stat_reg_int(sdb, "sim_elapsed_time",
"total simulation time in seconds",
&sim_elapsed_time, 0, NULL);
stat_reg_formula(sdb, "sim_inst_rate",
"simulation speed (in insts/sec)",
"sim_num_insn / sim_elapsed_time", NULL);
if (prof_ic)
{
/* instruction class profile */
ic_prof = stat_reg_dist(sdb, "sim_inst_class_prof",
"instruction class profile",
/* initial value */0,
/* array size */ic_NUM,
/* bucket size */1,
/* print format */(PF_COUNT|PF_PDF),
/* format */NULL,
/* index map */inst_class_str,
/* print fn */NULL);
}
if (prof_inst)
{
int i;
char buf[512];
/* conjure up appropriate instruction description strings */
for (i=0; i < /* skip NA */OP_MAX-1; i++)
{
sprintf(buf, "%-8s %-6s", md_op2name[i+1], md_op2format[i+1]);
inst_str[i] = mystrdup(buf);
}
/* instruction profile */
inst_prof = stat_reg_dist(sdb, "sim_inst_prof",
"instruction profile",
/* initial value */0,
/* array size */ /* skip NA */OP_MAX-1,
/* bucket size */1,
/* print format */(PF_COUNT|PF_PDF),
/* format */NULL,
/* index map */inst_str,
/* print fn */NULL);
}
if (prof_bc)
{
/* instruction branch profile */
bc_prof = stat_reg_dist(sdb, "sim_branch_prof",
"branch instruction profile",
/* initial value */0,
/* array size */bc_NUM,
/* bucket size */1,
/* print format */(PF_COUNT|PF_PDF),
/* format */NULL,
/* index map */branch_class_str,
/* print fn */NULL);
}
if (prof_am)
{
/* instruction branch profile */
am_prof = stat_reg_dist(sdb, "sim_addr_mode_prof",
"addressing mode profile",
/* initial value */0,
/* array size */md_amode_NUM,
/* bucket size */1,
/* print format */(PF_COUNT|PF_PDF),
/* format */NULL,
/* index map */md_amode_str,
/* print fn */NULL);
}
if (prof_seg)
{
/* instruction branch profile */
seg_prof = stat_reg_dist(sdb, "sim_addr_seg_prof",
"load/store address segment profile",
/* initial value */0,
/* array size */seg_NUM,
/* bucket size */1,
/* print format */(PF_COUNT|PF_PDF),
/* format */NULL,
/* index map */addr_seg_str,
/* print fn */NULL);
}
if (prof_tsyms && sym_ntextsyms != 0)
{
int i;
/* load program symbols */
sym_loadsyms(ld_prog_fname, load_locals);
/* conjure up appropriate instruction description strings */
tsym_names = (char **)calloc(sym_ntextsyms, sizeof(char *));
for (i=0; i < sym_ntextsyms; i++)
tsym_names[i] = sym_textsyms[i]->name;
/* text symbol profile */
tsym_prof = stat_reg_dist(sdb, "sim_text_sym_prof",
"text symbol profile",
/* initial value */0,
/* array size */sym_ntextsyms,
/* bucket size */1,
/* print format */(PF_COUNT|PF_PDF),
/* format */NULL,
/* index map */tsym_names,
/* print fn */NULL);
}
if (prof_dsyms && sym_ndatasyms != 0)
{
int i;
/* load program symbols */
sym_loadsyms(ld_prog_fname, load_locals);
/* conjure up appropriate instruction description strings */
dsym_names = (char **)calloc(sym_ndatasyms, sizeof(char *));
for (i=0; i < sym_ndatasyms; i++)
dsym_names[i] = sym_datasyms[i]->name;
/* data symbol profile */
dsym_prof = stat_reg_dist(sdb, "sim_data_sym_prof",
"data symbol profile",
/* initial value */0,
/* array size */sym_ndatasyms,
/* bucket size */1,
/* print format */(PF_COUNT|PF_PDF),
/* format */NULL,
/* index map */dsym_names,
/* print fn */NULL);
}
if (prof_taddr)
{
/* text address profile (sparse profile), NOTE: a dense print format
is used, its more difficult to read, but the profiles are *much*
smaller, I've assumed that the profiles are read by programs, at
least for your sake I hope this is the case!! */
taddr_prof = stat_reg_sdist(sdb, "sim_text_addr_prof",
"text address profile",
/* initial value */0,
/* print format */(PF_COUNT|PF_PDF),
/* format */"0x%p %u %.2f",
/* print fn */NULL);
}
for (i=0; i<pcstat_nelt; i++)
{
char buf[512], buf1[512];
struct stat_stat_t *stat;
/* track the named statistical variable by text address */
/* find it... */
stat = stat_find_stat(sdb, pcstat_vars[i]);
if (!stat)
fatal("cannot locate any statistic named `%s'", pcstat_vars[i]);
/* stat must be an integral type */
if (stat->sc != sc_int && stat->sc != sc_uint && stat->sc != sc_counter)
fatal("`-pcstat' statistical variable `%s' is not an integral type",
stat->name);
/* register this stat */
pcstat_stats[i] = stat;
pcstat_lastvals[i] = STATVAL(stat);
/* declare the sparce text distribution */
sprintf(buf, "%s_by_pc", stat->name);
sprintf(buf1, "%s (by text address)", stat->desc);
pcstat_sdists[i] = stat_reg_sdist(sdb, buf, buf1,
/* initial value */0,
/* print format */(PF_COUNT|PF_PDF),
/* format */"0x%p %u %.2f",
/* print fn */NULL);
}
ld_reg_stats(sdb);
mem_reg_stats(mem, sdb);
}
