static bool do_hardware_msaa_resolve(struct pipe_context *ctx, const struct pipe_blit_info *info) { struct si_context *sctx = (struct si_context*)ctx; struct r600_texture *src = (struct r600_texture*)info->src.resource; struct r600_texture *dst = (struct r600_texture*)info->dst.resource; unsigned dst_width = u_minify(info->dst.resource->width0, info->dst.level); unsigned dst_height = u_minify(info->dst.resource->height0, info->dst.level); enum pipe_format format = info->src.format; unsigned sample_mask = ~0; struct pipe_resource *tmp, templ; struct pipe_blit_info blit; /* Check basic requirements for hw resolve. */ if (!(info->src.resource->nr_samples > 1 && info->dst.resource->nr_samples <= 1 && !util_format_is_pure_integer(format) && !util_format_is_depth_or_stencil(format) && util_max_layer(info->src.resource, 0) == 0)) return false; /* Hardware MSAA resolve doesn't work if SPI format = NORM16_ABGR and * the format is R16G16. Use R16A16, which does work. */ if (format == PIPE_FORMAT_R16G16_UNORM) format = PIPE_FORMAT_R16A16_UNORM; if (format == PIPE_FORMAT_R16G16_SNORM) format = PIPE_FORMAT_R16A16_SNORM; /* Check the remaining requirements for hw resolve. */ if (util_max_layer(info->dst.resource, info->dst.level) == 0 && !info->scissor_enable && (info->mask & PIPE_MASK_RGBA) == PIPE_MASK_RGBA && util_is_format_compatible(util_format_description(info->src.format), util_format_description(info->dst.format)) && dst_width == info->src.resource->width0 && dst_height == info->src.resource->height0 && info->dst.box.x == 0 && info->dst.box.y == 0 && info->dst.box.width == dst_width && info->dst.box.height == dst_height && info->dst.box.depth == 1 && info->src.box.x == 0 && info->src.box.y == 0 && info->src.box.width == dst_width && info->src.box.height == dst_height && info->src.box.depth == 1 && dst->surface.level[info->dst.level].mode >= RADEON_SURF_MODE_1D && (!dst->cmask.size || !dst->dirty_level_mask)) { /* dst cannot be fast-cleared */ /* Check the last constraint. */ if (src->surface.micro_tile_mode != dst->surface.micro_tile_mode) { /* The next fast clear will switch to this mode to * get direct hw resolve next time if the mode is * different now. */ src->last_msaa_resolve_target_micro_mode = dst->surface.micro_tile_mode; goto resolve_to_temp; } /* Resolving into a surface with DCC is unsupported. Since * it's being overwritten anyway, clear it to uncompressed. * This is still the fastest codepath even with this clear. */ if (dst->dcc_offset && dst->surface.level[info->dst.level].dcc_enabled) { vi_dcc_clear_level(&sctx->b, dst, info->dst.level, 0xFFFFFFFF); dst->dirty_level_mask &= ~(1 << info->dst.level); } /* Resolve directly from src to dst. */ si_blitter_begin(ctx, SI_COLOR_RESOLVE | (info->render_condition_enable ? 0 : SI_DISABLE_RENDER_COND)); util_blitter_custom_resolve_color(sctx->blitter, info->dst.resource, info->dst.level, info->dst.box.z, info->src.resource, info->src.box.z, sample_mask, sctx->custom_blend_resolve, format); si_blitter_end(ctx); return true; } resolve_to_temp: /* Shader-based resolve is VERY SLOW. Instead, resolve into * a temporary texture and blit. */ memset(&templ, 0, sizeof(templ)); templ.target = PIPE_TEXTURE_2D; templ.format = info->src.resource->format; templ.width0 = info->src.resource->width0; templ.height0 = info->src.resource->height0; templ.depth0 = 1; templ.array_size = 1; templ.usage = PIPE_USAGE_DEFAULT; templ.flags = R600_RESOURCE_FLAG_FORCE_TILING | R600_RESOURCE_FLAG_DISABLE_DCC; /* The src and dst microtile modes must be the same. */ if (src->surface.micro_tile_mode == V_009910_ADDR_SURF_DISPLAY_MICRO_TILING) templ.bind = PIPE_BIND_SCANOUT; else templ.bind = 0; tmp = ctx->screen->resource_create(ctx->screen, &templ); if (!tmp) return false; assert(src->surface.micro_tile_mode == ((struct r600_texture*)tmp)->surface.micro_tile_mode); /* resolve */ si_blitter_begin(ctx, SI_COLOR_RESOLVE | (info->render_condition_enable ? 0 : SI_DISABLE_RENDER_COND)); util_blitter_custom_resolve_color(sctx->blitter, tmp, 0, 0, info->src.resource, info->src.box.z, sample_mask, sctx->custom_blend_resolve, format); si_blitter_end(ctx); /* blit */ blit = *info; blit.src.resource = tmp; blit.src.box.z = 0; si_blitter_begin(ctx, SI_BLIT | (info->render_condition_enable ? 0 : SI_DISABLE_RENDER_COND)); util_blitter_blit(sctx->blitter, &blit); si_blitter_end(ctx); pipe_resource_reference(&tmp, NULL); return true; }
static void si_do_fast_color_clear(struct si_context *sctx, unsigned *buffers, const union pipe_color_union *color) { struct pipe_framebuffer_state *fb = &sctx->framebuffer.state; int i; /* This function is broken in BE, so just disable this path for now */ #ifdef PIPE_ARCH_BIG_ENDIAN return; #endif if (sctx->render_cond) return; for (i = 0; i < fb->nr_cbufs; i++) { struct si_texture *tex; unsigned clear_bit = PIPE_CLEAR_COLOR0 << i; if (!fb->cbufs[i]) continue; /* if this colorbuffer is not being cleared */ if (!(*buffers & clear_bit)) continue; unsigned level = fb->cbufs[i]->u.tex.level; if (level > 0) continue; tex = (struct si_texture *)fb->cbufs[i]->texture; /* TODO: GFX9: Implement DCC fast clear for level 0 of * mipmapped textures. Mipmapped DCC has to clear a rectangular * area of DCC for level 0 (because the whole miptree is * organized in a 2D plane). */ if (sctx->chip_class >= GFX9 && tex->buffer.b.b.last_level > 0) continue; /* the clear is allowed if all layers are bound */ if (fb->cbufs[i]->u.tex.first_layer != 0 || fb->cbufs[i]->u.tex.last_layer != util_max_layer(&tex->buffer.b.b, 0)) { continue; } /* only supported on tiled surfaces */ if (tex->surface.is_linear) { continue; } /* shared textures can't use fast clear without an explicit flush, * because there is no way to communicate the clear color among * all clients */ if (tex->buffer.b.is_shared && !(tex->buffer.external_usage & PIPE_HANDLE_USAGE_EXPLICIT_FLUSH)) continue; if (sctx->chip_class <= GFX8 && tex->surface.u.legacy.level[0].mode == RADEON_SURF_MODE_1D && !sctx->screen->info.htile_cmask_support_1d_tiling) continue; /* Use a slow clear for small surfaces where the cost of * the eliminate pass can be higher than the benefit of fast * clear. The closed driver does this, but the numbers may differ. * * This helps on both dGPUs and APUs, even small APUs like Mullins. */ bool too_small = tex->buffer.b.b.nr_samples <= 1 && tex->buffer.b.b.width0 * tex->buffer.b.b.height0 <= 512 * 512; bool eliminate_needed = false; bool fmask_decompress_needed = false; /* Fast clear is the most appropriate place to enable DCC for * displayable surfaces. */ if (sctx->family == CHIP_STONEY && !too_small) { vi_separate_dcc_try_enable(sctx, tex); /* RB+ isn't supported with a CMASK clear only on Stoney, * so all clears are considered to be hypothetically slow * clears, which is weighed when determining whether to * enable separate DCC. */ if (tex->dcc_gather_statistics) /* only for Stoney */ tex->num_slow_clears++; } /* Try to clear DCC first, otherwise try CMASK. */ if (vi_dcc_enabled(tex, 0)) { uint32_t reset_value; if (sctx->screen->debug_flags & DBG(NO_DCC_CLEAR)) continue; /* This can happen with mipmapping or MSAA. */ if (sctx->chip_class == GFX8 && !tex->surface.u.legacy.level[level].dcc_fast_clear_size) continue; if (!vi_get_fast_clear_parameters(tex->buffer.b.b.format, fb->cbufs[i]->format, color, &reset_value, &eliminate_needed)) continue; if (eliminate_needed && too_small) continue; /* DCC fast clear with MSAA should clear CMASK to 0xC. */ if (tex->buffer.b.b.nr_samples >= 2 && tex->cmask_buffer) { /* TODO: This doesn't work with MSAA. */ if (eliminate_needed) continue; uint32_t clear_value = 0xCCCCCCCC; si_clear_buffer(sctx, &tex->cmask_buffer->b.b, tex->cmask_offset, tex->surface.cmask_size, &clear_value, 4, SI_COHERENCY_CB_META, false); fmask_decompress_needed = true; } vi_dcc_clear_level(sctx, tex, 0, reset_value); tex->separate_dcc_dirty = true; } else { if (too_small) continue; /* 128-bit formats are unusupported */ if (tex->surface.bpe > 8) { continue; } /* RB+ doesn't work with CMASK fast clear on Stoney. */ if (sctx->family == CHIP_STONEY) continue; /* ensure CMASK is enabled */ si_alloc_separate_cmask(sctx->screen, tex); if (!tex->cmask_buffer) continue; /* Do the fast clear. */ uint32_t clear_value = 0; si_clear_buffer(sctx, &tex->cmask_buffer->b.b, tex->cmask_offset, tex->surface.cmask_size, &clear_value, 4, SI_COHERENCY_CB_META, false); eliminate_needed = true; } if ((eliminate_needed || fmask_decompress_needed) && !(tex->dirty_level_mask & (1 << level))) { tex->dirty_level_mask |= 1 << level; p_atomic_inc(&sctx->screen->compressed_colortex_counter); } /* We can change the micro tile mode before a full clear. */ si_set_optimal_micro_tile_mode(sctx->screen, tex); *buffers &= ~clear_bit; /* Chips with DCC constant encoding don't need to set the clear * color registers for DCC clear values 0 and 1. */ if (sctx->screen->has_dcc_constant_encode && !eliminate_needed) continue; if (si_set_clear_color(tex, fb->cbufs[i]->format, color)) { sctx->framebuffer.dirty_cbufs |= 1 << i; si_mark_atom_dirty(sctx, &sctx->atoms.s.framebuffer); } } }