void HexagonHazardRecognizer::EmitInstruction(SUnit *SU) { MachineInstr *MI = SU->getInstr(); if (!MI) return; // Keep the set of definitions for each packet, which is used to determine // if a .new can be used. for (const MachineOperand &MO : MI->operands()) if (MO.isReg() && MO.isDef() && !MO.isImplicit()) RegDefs.insert(MO.getReg()); if (TII->isZeroCost(MI->getOpcode())) return; if (!Resources->canReserveResources(*MI)) { // It must be a .new store since other instructions must be able to be // reserved at this point. assert(TII->mayBeNewStore(*MI) && "Expecting .new store"); MachineFunction *MF = MI->getParent()->getParent(); MachineInstr *NewMI = MF->CreateMachineInstr(TII->get(TII->getDotNewOp(*MI)), MI->getDebugLoc()); assert(Resources->canReserveResources(*NewMI)); Resources->reserveResources(*NewMI); MF->DeleteMachineInstr(NewMI); } else Resources->reserveResources(*MI); LLVM_DEBUG(dbgs() << " Add instruction " << *MI); // When scheduling a dot cur instruction, check if there is an instruction // that can use the dot cur in the same packet. If so, we'll attempt to // schedule it before other instructions. We only do this if the load has a // single zero-latency use. if (TII->mayBeCurLoad(*MI)) for (auto &S : SU->Succs) if (S.isAssignedRegDep() && S.getLatency() == 0 && S.getSUnit()->NumPredsLeft == 1) { UsesDotCur = S.getSUnit(); DotCurPNum = PacketNum; break; } if (SU == UsesDotCur) { UsesDotCur = nullptr; DotCurPNum = -1; } UsesLoad = MI->mayLoad(); if (TII->isHVXVec(*MI) && !MI->mayLoad() && !MI->mayStore()) for (auto &S : SU->Succs) if (S.isAssignedRegDep() && S.getLatency() == 0 && TII->mayBeNewStore(*S.getSUnit()->getInstr()) && Resources->canReserveResources(*S.getSUnit()->getInstr())) { PrefVectorStoreNew = S.getSUnit(); break; } }
ScheduleHazardRecognizer::HazardType HexagonHazardRecognizer::getHazardType(SUnit *SU, int stalls) { MachineInstr *MI = SU->getInstr(); if (!MI || TII->isZeroCost(MI->getOpcode())) return NoHazard; if (!Resources->canReserveResources(*MI)) { LLVM_DEBUG(dbgs() << "*** Hazard in cycle " << PacketNum << ", " << *MI); HazardType RetVal = Hazard; if (TII->mayBeNewStore(*MI)) { // Make sure the register to be stored is defined by an instruction in the // packet. MachineOperand &MO = MI->getOperand(MI->getNumOperands() - 1); if (!MO.isReg() || RegDefs.count(MO.getReg()) == 0) return Hazard; // The .new store version uses different resources so check if it // causes a hazard. MachineFunction *MF = MI->getParent()->getParent(); MachineInstr *NewMI = MF->CreateMachineInstr(TII->get(TII->getDotNewOp(*MI)), MI->getDebugLoc()); if (Resources->canReserveResources(*NewMI)) RetVal = NoHazard; LLVM_DEBUG(dbgs() << "*** Try .new version? " << (RetVal == NoHazard) << "\n"); MF->DeleteMachineInstr(NewMI); } return RetVal; } if (SU == UsesDotCur && DotCurPNum != (int)PacketNum) { LLVM_DEBUG(dbgs() << "*** .cur Hazard in cycle " << PacketNum << ", " << *MI); return Hazard; } return NoHazard; }