uint_32 _e300_decrementer_timer_init
(
/* [IN] the tick rate wanted */
uint_32 frequency,
/* [IN] External clock speed */
uint_32 ext_clock,
/* [OUT] DEC value loaded */
uint_32_ptr preload_ptr
)
{
MPC5125_SYSTEM_CONFIGURATION_STRUCT_PTR sc_ptr = MPC5125_SC_ADDR();
uint_32 dec_freq,preload,hid0;
dec_freq = _mpc5125_get_ppc_clock(ext_clock);
preload = (dec_freq/frequency + 1 ) >> 3;
_PSP_SPR_SET(E300CORE_DEC,preload);
_PSP_SPR_GET(hid0,E300CORE_HID0);
hid0 |= (1<<6);
_PSP_SPR_SET(E300CORE_HID0,hid0);
*preload_ptr = preload;
sc_ptr->SPCR |= MPC5125_SC_SPCR_TBEN;
return MQX_OK;
}
static uint_32 _e200_decrementer_timer_init
(
/* [IN] the tick rate wanted */
uint_32 tickfreq,
/* [IN] Input clock frequency */
uint_32 clk
)
{
uint_32 period;
uint_32 tmp;
_PSP_SPR_SET(E200CORE_DEC, 0);
period = (uint_32)( ((clk << 1)/tickfreq + 1) >> 1 );
_PSP_SPR_GET(tmp, E200CORE_TCR);
tmp |= E200CORE_TCR_DIE | E200CORE_TCR_ARE; /* interrupt + Auto-reload enable */
_PSP_SPR_SET(E200CORE_TCR, tmp);
/* preload value is one less than period */
_PSP_SPR_SET(E200CORE_DEC, period-1);
_PSP_SPR_SET(E200CORE_DECAR, period-1); /* decrementer auto-reload */
/* enable clocks for TimeBase - this applies also to decrementer */
_PSP_SPR_GET(tmp, E200CORE_HID0);
tmp |= E200CORE_HID0_TBEN;
_PSP_SPR_SET(E200CORE_HID0, tmp);
return period;
}
uint_32 _e300_decrementer_timer_init
(
/* [IN] the tick rate wanted */
uint_32 frequency,
/* [IN] External clock speed */
uint_32 ext_clock,
/* [OUT] DEC value loaded */
uint_32_ptr preload_ptr
)
{
MPC83xx_SYSCON_STRUCT_PTR syscon_ptr;
uint_32 dec_freq,preload,hid0;
uint_32 immr;
immr = (uint_32)BSP_IMMR_BASE;
syscon_ptr = (MPC83xx_SYSCON_STRUCT_PTR)(immr + MPC83xx_SYSCON_BASE);
dec_freq = _mpc83xx_get_core_clock(BSP_CLKIN);
preload = (dec_freq/frequency + 1 ) >> 2;
_PSP_SPR_SET(E300CORE_DEC,preload);
_PSP_SPR_GET(hid0,E300CORE_HID0);
hid0 |= (1<<6);
_PSP_SPR_SET(E300CORE_HID0,hid0);
*preload_ptr = preload;
syscon_ptr->SPCR |= MPC83XX_SYSCON_TBEN;
return MQX_OK;
}
static void _e200_decrementer_kernel_isr(pointer dummy)
{
_PSP_SPR_SET(E200CORE_TSR, E200CORE_TSR_DIS);
_time_notify_kernel();
}
static void _e200_decrementer_null_isr(pointer dummy)
{
_PSP_SPR_SET(E200CORE_TSR, E200CORE_TSR_DIS);
}
void _icache_disable
(
void
)
{ /* Body */
#if defined(PSP_PPC403) || defined(PSP_PPC401) || defined(PSP_IOP480) || \
defined(PSP_PPC405)
_icache_invalidate();
_PSP_ISYNC();
_PSP_SPR_SET(1019, 0); // ICCR <= 0
#elif defined(PSP_PPC603) || defined(PSP_PPC740) || defined(PSP_PPC750) || \
defined(PSP_MPC8240) || defined(PSP_G2_CORE) || defined(PSP_PPC7400) || \
defined(PSP_E300_CORE)
_icache_invalidate();
asm(" mfspr r3,1008");
asm(" rlwinm r3,r3,0,17,15");
_PSP_ISYNC();
asm(" mtspr 1008,r3");
_PSP_ISYNC();
#elif defined(PSP_E500_CORE) || (defined(PSP_E200_CORE) && defined (PSP_E200_CORE_Z7))
register uint_32 val;
_dcache_flush();
_PSP_SPR_GET(val,1011); /* L1CSR1 */
val &= ~0x01;
#ifdef PSP_BOOKE
asm ("msync");
#else
_PSP_SYNC();
#endif
_PSP_ISYNC();
_PSP_SPR_SET(1011,val);
_PSP_ISYNC();
#elif defined(PSP_MPC555) || defined(PSP_MPC566)
/* Has no cache */
#elif defined(PSP_MPC505) || defined(PSP_MPC821) || defined(PSP_MPC823) || \
defined(PSP_MPC850) || defined(PSP_MPC855) || defined(PSP_MPC860) || \
defined(PSP_MPC866) || defined(PSP_MPC875)
_icache_invalidate();
asm(" mfspr r3,560");
asm(" oris r3,r3,0x0400");
asm(" mtspr 560,r3");
_PSP_ISYNC();
#elif defined(PSP_PPC440)
// Cache cannot be easily disabled. You must modify the appropriate
// TLB entries....
#elif defined(PSP_E200_CORE)
/* catch ERROR : undefined cpu type " */
#else
#error "CPU NOT DEFINED"
#endif
} /* Endbody */
void _icache_enable
(
/* [IN] icache enable parameter */
uint_32 parameter
)
{ /* Body */
#if defined(PSP_PPC403) || defined(PSP_PPC401) || defined(PSP_IOP480) || \
defined(PSP_PPC405)
_PSP_SYNC();
_PSP_ISYNC();
_PSP_SPR_SET(1019, parameter); // mtspr iccr,param
_PSP_SYNC();
_PSP_ISYNC();
#elif defined(PSP_PPC603) || defined(PSP_MPC8240) || defined(PSP_G2_CORE) || \
defined(PSP_E300_CORE)
asm(" mfspr r3,1008");
asm(" ori r4,r3,0xA800");
asm(" xori r3,r4,0x2800");
asm(" xori r4,r4,0x2000");
_PSP_ISYNC();
asm(" mtspr 1008,r4");
asm(" mtspr 1008,r3");
_PSP_SYNC();
#elif defined(PSP_E500_CORE)
register uint_32 i,e;
_PSP_SPR_GET(i,1011); /* L1CSR1 */
i |= 0x03;
e = i ^ 0x02;
_PSP_SYNC();
_PSP_ISYNC();
_PSP_SPR_SET(1011,i);
_PSP_SPR_SET(1011,e);
_PSP_ISYNC();
#elif defined(PSP_E200_CORE)
#if defined (PSP_E200_CORE_Z7)
register uint_32 i;
/* Cache must be invalidated first and then enabled */
_icache_invalidate();
_PSP_SPR_GET(i,E200CORE_L1CSR1); /* L1CSR1 */
/* enable instruction cache */
i |= E200CORE_L1CSR1_ICE;
asm ("msync");
_PSP_ISYNC();
_PSP_SPR_SET(E200CORE_L1CSR1,i); /* instruction enable cache */
_PSP_ISYNC();
asm ("isync");
#endif
#elif defined(PSP_PPC740) || defined(PSP_PPC750) || defined(PSP_PPC7400)
asm(" mfspr r3,1008");
asm(" ori r4,r3,0xA808");
asm(" xori r3,r4,0x2800");
asm(" xori r4,r4,0x2000");
_PSP_ISYNC();
asm(" mtspr 1008,r4");
asm(" mtspr 1008,r3");
_PSP_SYNC();
#elif defined(PSP_MPC555) || defined(PSP_MPC566)
/* Has no cache */
#elif defined(PSP_MPC505) || defined(PSP_MPC821) || defined(PSP_MPC823) || \
defined(PSP_MPC850) || defined(PSP_MPC855) || defined(PSP_MPC860) || \
defined(PSP_MPC866) || defined(PSP_MPC875)
asm(" mfspr r3,560");
asm(" oris r3,r3,0x0200");
asm(" mtspr 560,r3");
_PSP_ISYNC();
#elif defined(PSP_PPC440)
// Cache control registers have to be set up during boot process.
/* catch ERROR : undefined cpu type " */
#else
#error "CPU NOT DEFINED"
#endif
} /* Endbody */
void _dcache_enable
(
/* [IN] mask that defines cachable areas on 403,401 */
/* [IN] dummy input variable on other PPCs*/
uint_32 dcache_en_mask
)
{ /* Body */
#if defined(PSP_PPC403) || defined(PSP_PPC401) || defined(PSP_IOP480) || \
defined(PSP_PPC405)
_PSP_SYNC();
_PSP_ISYNC();
_PSP_SPR_SET(1018, dcache_en_mask); // mtspr dccr,dcache_en_mask
_PSP_SYNC();
_PSP_ISYNC();
#elif defined(PSP_PPC603) || defined(PSP_MPC8240) || defined(PSP_G2_CORE) || \
defined(PSP_E300_CORE)
register uint_32 val,i,e;
_PSP_SPR_GET(val,1008);
i = val | 0x5400;
e = i ^ 0x1400;
i = i ^ 0x1000;
_PSP_SYNC();
_PSP_SPR_SET(1008,i);
_PSP_SPR_SET(1008,e);
_PSP_SYNC();
#elif defined(PSP_E500_CORE)
register uint_32 i,e;
/* Enable address boardcast enable for L1 & L2 caches */
_PSP_SPR_GET(i,E500CORE_HID1);
i |= E500CORE_HID1_ABE;
_PSP_SPR_SET(E500CORE_HID1,i);
_PSP_SPR_GET(i,1010); /* L1CSR0 */
i |= 0x03;
e = i ^ 0x02;
_PSP_SYNC();
_PSP_ISYNC();
_PSP_SPR_SET(1010,i);
_PSP_SPR_SET(1010,e);
_PSP_ISYNC();
#elif defined(PSP_E200_CORE)
register uint_32 i;
/* Cahce must be invalidated first and then enabled */
_dcache_invalidate();
_PSP_SPR_GET(i,E200CORE_L1CSR0); /* L1CSR0 */
/* enable copy-back mode,
push buffer disabled, error injection disabled on 5674,
enable cache */
i |= E200CORE_L1CSR0_CE | E200CORE_L1CSR0_CWM | E200CORE_L1CSR0_DPB;
asm ("msync");
_PSP_ISYNC();
_PSP_SPR_SET(E200CORE_L1CSR0,i); /* enable cache */
_PSP_ISYNC();
asm ("isync");
#elif defined(PSP_PPC740) || defined(PSP_PPC750) || defined(PSP_PPC7400)
register uint_32 val,i,e;
_PSP_SPR_GET(val,1008);
i = val | 0x5480;
e = i ^ 0x1400;
i = i ^ 0x1000;
_PSP_SYNC();
_PSP_SPR_SET(1008,i);
_PSP_SPR_SET(1008,e);
_PSP_SYNC();
#elif defined(PSP_MPC555) || defined(PSP_MPC566)
/* Has no cache */
#elif defined(PSP_MPC821) || defined(PSP_MPC823) || defined(PSP_MPC850) || \
defined(PSP_MPC855) || defined(PSP_MPC860) || defined(PSP_MPC866) || \
defined(PSP_MPC875)
register uint_32 val;
_PSP_SPR_GET(val,568);
val |= 0x02000000;
_PSP_SYNC();
_PSP_SPR_SET(568,val);
_PSP_SYNC();
#elif defined(PSP_PPC440)
// Cache control registers have to be set up during boot process.
// marks@6/25/03 The ibevb440 BSP has not yet done this since it relies
// on the IBM OS/Open rom monitor to initialize the board.
/* catch ERROR : undefined cpu type " */
#else
#error "CPU NOT DEFINED"
#endif
} /* Endbody */
void _dcache_flush
(
void
)
{ /* Body */
#if defined(PSP_PPC403) || defined(PSP_PPC401) || defined(PSP_IOP480)
/* hardcoded branches are used, insert lines with care */
asm(" li r5, 0"); /* line 0 */
asm(" mtcrf 0xFF, r5"); /* Set whole CR to zero */
asm(" mfcdbcr r3"); /* CDBCR -> R3*/
asm(" clrrwi r4, r3, 1"); /* set Way A */
asm("_dcache_flush_next_way:");
asm(" ori r4, r4, 0x10"); /* set CIS to tag */
asm(" mtcdbcr r4"); /* R4 -> CDBCR */
asm("_dcache_flush_next_line:");
asm(" dcread r4, 0, r5"); /* read cache TAG info*/
asm(" andi. r6, r4,0x10"); /* check the valid bit */
asm(" beq CR0, _dcache_flush_invalid"); /* skip line if invalid */
asm(" clrrwi r4, r4, 9"); /* form EA that is flushed*/
asm(" dcbf r4, r5"); /* flush line */
asm("_dcache_flush_invalid:");
asm(" addi r5, r5, 16"); /* set r5 for next line*/
asm(" andi. r6, r5, 0xFE00"); /* last flushed ?*/
asm(" beq CR0, _dcache_flush_next_line"); /* next line */
asm(" bgt CR1, _dcache_flush_end_flush"); /* end ? */
asm(" mcrf CR1, CR0"); /* set CR1[gt] */
asm(" li r5, 0"); /* line 0 */
asm(" ori r4, r3, 1"); /* set Way B*/
asm(" b _dcache_flush_next_way"); /* next line */
asm("_dcache_flush_end_flush:");
asm(" mtcdbcr r3"); /* restore CDBCR */
_PSP_SYNC();
#elif defined(PSP_MPC555) || defined(PSP_MPC566)
/* Has no cache */
#elif defined(PSP_PPC603) || defined(PSP_MPC8240) || defined(PSP_G2_CORE) || \
defined(PSP_E300_CORE) || defined(PSP_E500_CORE)
volatile uint_32 _PTR_ tmp_ptr;
volatile uint_32 tmp;
uint_32 i;
/*
** We just stored our link register %LR on the top of the stack.
** When debugging with the cache enabled we want to force it to
** memory now. Problems were found on the MPC8266 where the LR
** value restored was not the value written.
*/
_PSP_SYNC();
_PSP_ISYNC();
asm(" dcbf r0, r1"); /* Flush top of stack + 0x00 */
asm(" li r0, 32");
asm(" dcbf r1, r0"); /* Flush top of stack + 0x20 */
asm(" li r0, 64");
asm(" dcbf r1, r0"); /* Flush top of stack + 0x40 */
asm(" li r0, 96");
asm(" dcbf r1, r0"); /* Flush top of stack + 0x60 */
_PSP_SYNC();
/* In order to "Flush" the entire data cache, fake reads
** need to be executed for a select number of memory locations,
** then those locations need to be "flushed"
** there are 128 sets of 4 blocks each.
** the sets are addressed by bits A20 to A26
*/
tmp_ptr = 0;
i = PSP_DCACHE_SIZE / PSP_CACHE_LINE_SIZE + 1;
while (--i) {
tmp = *tmp_ptr;
tmp_ptr = (pointer)((uchar_ptr)tmp_ptr + PSP_CACHE_LINE_SIZE);
} /* Endwhile */
tmp_ptr = 0;
i = PSP_DCACHE_SIZE / PSP_CACHE_LINE_SIZE;
while (--i) {
_PSP_FLUSH_LINE((pointer)tmp_ptr);
tmp_ptr = (pointer)((uchar_ptr)tmp_ptr + PSP_CACHE_LINE_SIZE);
} /* Endwhile */
_dcache_flush_line((pointer)tmp_ptr);
#elif defined(PSP_E200_CORE)
register uint_32 i;
uint_32 j;
volatile uint_32 _PTR_ tmp_ptr;
/* In order to "Flush" the entire data cache, we need to flush
** either by the way or by the set (line).
*/
tmp_ptr = 0;
asm ("msync");
_PSP_ISYNC();
_PSP_SPR_GET(i,E200CORE_L1FINV0); /* L1FINV0 */
for (j = 0; j < PSP_DCACHE_NUM_LINES; j++)
{
i = j << 5; /* Specify the cache set to be selected */
i |= 0x00000001; /* Flush and valid without invalidation */
_PSP_FLUSH_LINE((pointer)tmp_ptr);
tmp_ptr = (pointer)((uchar_ptr)tmp_ptr + PSP_CACHE_LINE_SIZE);
_PSP_SPR_SET(E200CORE_L1FINV0,i);
} /* Endfor */
_dcache_flush_line((pointer)tmp_ptr);
#elif defined(PSP_PPC740) || defined(PSP_PPC750)
volatile uint_32 _PTR_ tmp_ptr;
volatile uint_32 tmp;
uint_32 i;
uint_32 l2_cache;
uint_32 init;
/* In order to "Flush" the entire data cache, fake reads
** need to be executed for a select number of memory locations,
** then those locations need to be "flushed"
** there are 128 sets of 8 blocks each.
** the sets are addressed by bits A20 to A26
** However if the L2 cached is enabled, then it can be of
** size 128K, 512K or 1024K.
*/
tmp_ptr = 0;
_PSP_SPR_GET(l2_cache, PPC750_L2CR);
if (l2_cache & PPC750_L2_CACHE_L2E) {
if ((l2_cache & PPC750_L2_CACHE_L2SIZ_MASK) ==
PPC750_L2_CACHE_L2SIZ_256K)
{
init = 8193;
} else if ((l2_cache & PPC750_L2_CACHE_L2SIZ_MASK) ==
PPC750_L2_CACHE_L2SIZ_512K)
{
init = 16385;
} else {
init = 32769;
}/* Endif */
} else {
init = 1025;
}/* Endif */
i = init;
while (--i) {
tmp = *tmp_ptr;
tmp_ptr = (pointer)((uchar_ptr)tmp_ptr + 0x20);
} /* Endwhile */
tmp_ptr = 0;
i = init - 1;
while (--i) {
_PSP_FLUSH_LINE((pointer)tmp_ptr);
tmp_ptr = (pointer)((uchar_ptr)tmp_ptr + 0x20);
} /* Endwhile */
_dcache_flush_line((pointer)tmp_ptr);
#elif defined(PSP_PPC7400)
/* Flush L1 and L2 cache */
_ppc7400_flushL1();
_ppc7400_flushL2();
#elif defined(PSP_MPC821) || defined(PSP_MPC823) || defined(PSP_MPC850) || \
defined(PSP_MPC855) || defined(PSP_MPC860) || defined(PSP_MPC866) || \
defined(PSP_MPC875)
uint_32 i,way0 = 0x0000, way1 = 0x1000, cmd;
_PSP_SPR_GET(cmd,568);
cmd |= 0x0E000000;
for (i = 0; i < 256; i++) {
_PSP_SPR_SET(569,way0);
_PSP_SPR_SET(568,cmd);
_PSP_SPR_SET(569,way1);
_PSP_SPR_SET(568,cmd);
way0 += 16;
way1 += 16;
} /* Endfor */
_PSP_SYNC();
#elif defined(PSP_PPC405)
register uchar_ptr p;
uint_32 i;
// I'm assuming KERNEL_DATA is a large enough block of memory
// and that it can be aligned to the beginning of a 4 * dcache
// sized memory block.
_GET_KERNEL_DATA(p);
p = (uchar_ptr)(((uint_32)p) & ~((PSP_DCACHE_SIZE*4)-1));
_int_disable();
for (i = 0; i < PSP_DCACHE_NUM_LINES*4; i++) {
register uint_32 zero = 0;
(void) *(volatile _mqx_int _PTR_)p; // Load from the address
__dcbf((pointer)p, zero); // Data cache block flush
asm {
iccci p, zero
}
p += PSP_CACHE_LINE_SIZE;
} /* Endfor */
_PSP_SYNC();
_PSP_ISYNC();
_int_enable();
#elif defined(PSP_PPC440)
uchar_ptr p;
_mqx_int i, old_msr = _MFMSR();
// I'm assuming KERNEL_DATA is a large enough block of memory
// and that it can be aligned to the beginning of a dcache
// sized memory block.
_GET_KERNEL_DATA(p);
p = (uchar_ptr)(((uint_32)p) & ~(PSP_DCACHE_SIZE-1));
// Must be atomic
_MTMSR(old_msr & ~(PPC440_MSR_EE|PPC440_MSR_CE|PPC440_MSR_ME));
// Finish all data writes
_PSP_SYNC();
// There are 1024 lines in the dcache.
// Twice as much data must be read in.
for (i = 0; i < PPC440_DCACHE_NUM_LINES2X; i++) {
(void) *(volatile _mqx_int _PTR_)p; // Load from the address
_DCBF((pointer)p,0); // Data cache block flush
_ICBI((pointer)p,0); // Instruction cache block invalidate
p += PPC440_DCACHE_LINE_SIZE;
} /* Endfor */
_PSP_SYNC();
_MTMSR(old_msr);
/* catch ERROR : undefined cpu type " */
#else
#error "CPU NOT DEFINED"
#endif
} /* Endbody */
void _dcache_disable
(
void
)
{ /* Body */
#if defined(PSP_PPC403) || defined(PSP_PPC401) || defined(PSP_IOP480) || \
defined(PSP_PPC405)
_dcache_flush();
_PSP_SPR_SET(1018,0); // mtspr dccr,0
_PSP_SYNC();
#elif defined(PSP_PPC603) || defined(PSP_PPC740) || defined(PSP_PPC750) || \
defined(PSP_MPC8240) || defined(PSP_G2_CORE) || defined(PSP_PPC7400) || \
defined(PSP_E300_CORE)
register uint_32 val;
_dcache_flush();
_PSP_SPR_GET(val,1008);
val &= ~0x4000;
_PSP_SYNC();
_PSP_SPR_SET(1008,val);
_PSP_SYNC();
#elif defined(PSP_E500_CORE) || defined(PSP_E200_CORE)
register uint_32 val;
_dcache_flush();
_PSP_SPR_GET(val,1010); /* L1CSR0 */
val &= ~0x01;
#ifdef PSP_BOOKE
asm ("msync");
#else
_PSP_SYNC();
#endif
_PSP_ISYNC();
_PSP_SPR_SET(1010,val);
_PSP_ISYNC();
#elif defined(PSP_MPC555) || defined(PSP_MPC566)
/* Has no cache */
/* define PSP_MPC823 in macro */
#elif defined(PSP_MPC821) || defined(PSP_MPC823) || defined(PSP_MPC850) || \
defined(PSP_MPC855) || defined(PSP_MPC860) || defined(PSP_MPC866) || \
defined(PSP_MPC875)
register uint_32 val;
_dcache_flush();
_PSP_SPR_GET(val,568);
val |= 0x04000000;
_PSP_SYNC();
_PSP_SPR_SET(568,val);
#elif defined(PSP_PPC440)
// Cache cannot be easily disabled. You must modify the appropriate
// TLB entries that allow cache to disallow it. I'm not sure that's
// a good idea.
/* catch ERROR : undefined cpu type " */
#else
#error "CPU NOT DEFINED"
#endif
} /* Endbody */
