void gpio_can_active(int id)
{
	int pad;

	switch (id) {
	case 0:
		pad = PAD_CTL_HYS_SCHMITZ | PAD_CTL_PKE_ENABLE | \
		    PAD_CTL_PUE_PUD | PAD_CTL_100K_PU | PAD_CTL_DRV_HIGH;
		mxc_request_iomux(MX35_PIN_I2C2_CLK, MUX_CONFIG_ALT1);
		mxc_request_iomux(MX35_PIN_I2C2_DAT, MUX_CONFIG_ALT1);
		mxc_iomux_set_pad(MX35_PIN_I2C2_CLK, pad);
		mxc_iomux_set_pad(MX35_PIN_I2C2_DAT, pad);
		mxc_iomux_set_input(MUX_IN_CAN1_CANRX, INPUT_CTL_PATH0);
		break;
	case 1:
		pad = PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_PUD | PAD_CTL_100K_PU;
		mxc_request_iomux(MX35_PIN_FEC_MDC, MUX_CONFIG_ALT1);
		mxc_request_iomux(MX35_PIN_FEC_MDIO, MUX_CONFIG_ALT1);
		mxc_iomux_set_pad(MX35_PIN_FEC_MDC, pad);
		mxc_iomux_set_pad(MX35_PIN_FEC_MDIO, pad);
		mxc_iomux_set_input(MUX_IN_CAN2_CANRX, INPUT_CTL_PATH2);
		break;
	default:
		printk(KERN_ERR "NO such device\n");
	}
}
/*!
 * Setup GPIO for an I2C device to be active
 *
 * @param  i2c_num         an I2C device
 */
void gpio_i2c_active(int i2c_num)
{
	iomux_pad_config_t regval = 0;

	switch (i2c_num) {
	case 0:
		/* fuel gauge and rtc */
		mxc_request_iomux(MX37_PIN_I2C1_CLK, IOMUX_CONFIG_ALT4);
		mxc_set_gpio_direction(MX37_PIN_I2C1_CLK, 0);
		mxc_set_gpio_dataout(MX37_PIN_I2C1_CLK, 0);
		mxc_request_iomux(MX37_PIN_I2C1_DAT, IOMUX_CONFIG_ALT4);
		mxc_set_gpio_direction(MX37_PIN_I2C1_DAT, 0);
		mxc_set_gpio_dataout(MX37_PIN_I2C1_DAT, 0);

		/* select I2C1_SCK as daisy chain input */
		mxc_request_iomux(MX37_PIN_I2C1_CLK, IOMUX_CONFIG_ALT0);
		mxc_iomux_set_input(MUX_IN_I2C1_SCL, INPUT_CTL_PATH1);
		/* OpenDrain enabled, 100k PU enabled */
		regval =
		    PAD_CTL_ODE_OPENDRAIN_ENABLE | PAD_CTL_100K_PU |
		    PAD_CTL_PKE_ENABLE;
		mxc_iomux_set_pad(MX37_PIN_I2C1_CLK, regval);

		/*select I2C1_SDA as daisy chain input */
		mxc_request_iomux(MX37_PIN_I2C1_DAT, IOMUX_CONFIG_ALT0);
		mxc_iomux_set_input(MUX_IN_I2C1_SDA, INPUT_CTL_PATH1);
		mxc_iomux_set_pad(MX37_PIN_I2C1_DAT, regval);
		mxc_iomux_set_pad(MX37_PIN_GRP_H3, PAD_CTL_HYS_ENABLE);
		break;
	case 1:
		mxc_request_iomux(MX37_PIN_GPIO1_0, IOMUX_CONFIG_ALT0);
		mxc_set_gpio_direction(MX37_PIN_GPIO1_0, 0);
		mxc_set_gpio_dataout(MX37_PIN_GPIO1_0, 0);
		mxc_request_iomux(MX37_PIN_GPIO1_1, IOMUX_CONFIG_ALT0);
		mxc_set_gpio_direction(MX37_PIN_GPIO1_1, 0);
		mxc_set_gpio_dataout(MX37_PIN_GPIO1_1, 0);

		/*select I2C2_SCL as daisy chain input */
		mxc_iomux_set_input(MUX_IN_I2C2_SCL, INPUT_CTL_PATH1);
		regval = PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE |
		    PAD_CTL_PUE_PULL | PAD_CTL_100K_PU |
		    PAD_CTL_ODE_OPENDRAIN_ENABLE | PAD_CTL_DRV_HIGH;
		mxc_iomux_set_pad(MX37_PIN_GPIO1_0, regval);
		mxc_request_iomux(MX37_PIN_GPIO1_0,
				  (IOMUX_CONFIG_SION | IOMUX_CONFIG_ALT2));

		/*select I2C2_SDA as daisy chain input */
		mxc_iomux_set_input(MUX_IN_I2C2_SDA, INPUT_CTL_PATH1);
		mxc_iomux_set_pad(MX37_PIN_GPIO1_1, regval);
		mxc_request_iomux(MX37_PIN_GPIO1_1,
				  (IOMUX_CONFIG_SION | IOMUX_CONFIG_ALT2));
		break;
	case 2:
		break;
	default:
		break;
	}
}
예제 #3
0
/*!
 * Setup GPIO for a UART port to be active
 *
 * @param  port         a UART port
 * @param  no_irda      indicates if the port is used for SIR
 */
void gpio_uart_active(int port, int no_irda)
{
	/*
	 * Configure the IOMUX control registers for the UART signals
	 */
	switch (port) {
		/* UART 1 IOMUX Configs */
	case 0:
		mxc_request_iomux(MX35_PIN_RXD1, MUX_CONFIG_FUNC);
		mxc_request_iomux(MX35_PIN_TXD1, MUX_CONFIG_FUNC);
		mxc_request_iomux(MX35_PIN_RTS1, MUX_CONFIG_FUNC);
		mxc_request_iomux(MX35_PIN_CTS1, MUX_CONFIG_FUNC);

		mxc_iomux_set_pad(MX35_PIN_RXD1,
				  PAD_CTL_HYS_SCHMITZ | PAD_CTL_PKE_ENABLE |
				  PAD_CTL_PUE_PUD | PAD_CTL_100K_PU);
		mxc_iomux_set_pad(MX35_PIN_TXD1,
				  PAD_CTL_PUE_PUD | PAD_CTL_100K_PD);
		mxc_iomux_set_pad(MX35_PIN_RTS1,
				  PAD_CTL_HYS_SCHMITZ | PAD_CTL_PKE_ENABLE |
				  PAD_CTL_PUE_PUD | PAD_CTL_100K_PU);
		mxc_iomux_set_pad(MX35_PIN_CTS1,
				  PAD_CTL_PUE_PUD | PAD_CTL_100K_PD);

		break;
		/* UART 2 IOMUX Configs */
	case 1:
		mxc_request_iomux(MX35_PIN_TXD2, MUX_CONFIG_FUNC);
		mxc_request_iomux(MX35_PIN_RXD2, MUX_CONFIG_FUNC);
		mxc_request_iomux(MX35_PIN_RTS2, MUX_CONFIG_FUNC);
		mxc_request_iomux(MX35_PIN_CTS2, MUX_CONFIG_FUNC);
		mxc_iomux_set_pad(MX35_PIN_RXD2,
				  PAD_CTL_HYS_SCHMITZ | PAD_CTL_PKE_ENABLE |
				  PAD_CTL_PUE_PUD | PAD_CTL_100K_PU);
		mxc_iomux_set_pad(MX35_PIN_TXD2,
				  PAD_CTL_PUE_PUD | PAD_CTL_100K_PD);
		mxc_iomux_set_pad(MX35_PIN_RTS2,
				  PAD_CTL_HYS_SCHMITZ | PAD_CTL_PKE_ENABLE |
				  PAD_CTL_PUE_PUD | PAD_CTL_100K_PU);
		mxc_iomux_set_pad(MX35_PIN_CTS2,
				  PAD_CTL_PUE_PUD | PAD_CTL_100K_PD);
		break;
		/* UART 3 IOMUX Configs */
	case 2:
		mxc_request_iomux(MX35_PIN_FEC_TX_CLK, MUX_CONFIG_ALT2);
		mxc_request_iomux(MX35_PIN_FEC_RX_CLK, MUX_CONFIG_ALT2);
		mxc_request_iomux(MX35_PIN_FEC_COL, MUX_CONFIG_ALT2);
		mxc_request_iomux(MX35_PIN_FEC_RX_DV, MUX_CONFIG_ALT2);

		mxc_iomux_set_input(MUX_IN_UART3_UART_RTS_B, INPUT_CTL_PATH2);
		mxc_iomux_set_input(MUX_IN_UART3_UART_RXD_MUX, INPUT_CTL_PATH3);
		break;
	default:
		break;
	}

}
예제 #4
0
/* workaround for ecspi chipselect pin may not keep correct level when idle */
void mx53_evk_gpio_spi_chipselect_active(int cspi_mode, int status,
					     int chipselect)
{
	switch (cspi_mode) {
	case 1:
		switch (chipselect) {
		case 0x1:
			/* de-select SS1 of instance: ecspi1. */
			mxc_request_iomux(MX53_PIN_EIM_D19, IOMUX_CONFIG_ALT1);
			mxc_iomux_set_pad(MX53_PIN_EIM_D19,
					  PAD_CTL_HYS_ENABLE |
					  PAD_CTL_PKE_ENABLE |
					  PAD_CTL_PUE_PULL |
					  PAD_CTL_100K_PU |
					  PAD_CTL_DRV_HIGH);

			/* mux mode: ALT4 mux port: SS0 of instance: ecspi1. */
			mxc_request_iomux(MX53_PIN_EIM_EB2, IOMUX_CONFIG_ALT4);
			mxc_iomux_set_pad(MX53_PIN_EIM_EB2,
					  PAD_CTL_HYS_ENABLE |
					  PAD_CTL_DRV_HIGH);
			mxc_iomux_set_input(
				MUX_IN_ECSPI1_IPP_IND_SS_B_1_SELECT_INPUT,
					  INPUT_CTL_PATH3);
			break;
		case 0x2:
			/* de-select SS0 of instance: ecspi1. */
			mxc_request_iomux(MX53_PIN_EIM_EB2, IOMUX_CONFIG_ALT1);
			mxc_iomux_set_pad(MX53_PIN_EIM_EB2,
					  PAD_CTL_HYS_ENABLE |
					  PAD_CTL_PKE_ENABLE |
					  PAD_CTL_PUE_PULL |
					  PAD_CTL_100K_PU |
					  PAD_CTL_DRV_HIGH);
			mxc_request_iomux(MX53_PIN_EIM_D19, IOMUX_CONFIG_ALT4);
			mxc_iomux_set_pad(MX53_PIN_EIM_D19,
					  PAD_CTL_HYS_ENABLE |
					  PAD_CTL_DRV_HIGH);
			mxc_iomux_set_input(
				MUX_IN_ECSPI1_IPP_IND_SS_B_1_SELECT_INPUT,
					  INPUT_CTL_PATH3);

			break;
		default:
			break;
		}
		break;
	case 2:
		break;
	case 3:
		break;
	default:
		break;
	}
}
예제 #5
0
static void setup_i2c(unsigned int port_number)
{
	switch (port_number) {
	case 0:
		/* i2c1 SDA */
		mxc_request_iomux(MX53_PIN_CSI0_D8,
				IOMUX_CONFIG_ALT5 | IOMUX_CONFIG_SION);
		mxc_iomux_set_input(MX53_I2C1_IPP_SDA_IN_SELECT_INPUT,
				INPUT_CTL_PATH0);
		mxc_iomux_set_pad(MX53_PIN_CSI0_D8,
				PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH |
				PAD_CTL_100K_PU | PAD_CTL_HYS_ENABLE |
				PAD_CTL_ODE_OPENDRAIN_ENABLE);
		/* i2c1 SCL */
		mxc_request_iomux(MX53_PIN_CSI0_D9,
				IOMUX_CONFIG_ALT5 | IOMUX_CONFIG_SION);
		mxc_iomux_set_input(MX53_I2C1_IPP_SCL_IN_SELECT_INPUT,
				INPUT_CTL_PATH0);
		mxc_iomux_set_pad(MX53_PIN_CSI0_D9,
				PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH |
				PAD_CTL_100K_PU | PAD_CTL_HYS_ENABLE |
				PAD_CTL_ODE_OPENDRAIN_ENABLE);
		break;
	case 1:
		/* i2c2 SDA */
		mxc_request_iomux(MX53_PIN_KEY_ROW3,
				IOMUX_CONFIG_ALT4 | IOMUX_CONFIG_SION);
		mxc_iomux_set_input(MX53_I2C2_IPP_SDA_IN_SELECT_INPUT,
				INPUT_CTL_PATH0);
		mxc_iomux_set_pad(MX53_PIN_KEY_ROW3,
				PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH |
				PAD_CTL_100K_PU | PAD_CTL_HYS_ENABLE |
				PAD_CTL_ODE_OPENDRAIN_ENABLE);

		/* i2c2 SCL */
		mxc_request_iomux(MX53_PIN_KEY_COL3,
				IOMUX_CONFIG_ALT4 | IOMUX_CONFIG_SION);
		mxc_iomux_set_input(MX53_I2C2_IPP_SCL_IN_SELECT_INPUT,
				INPUT_CTL_PATH0);
		mxc_iomux_set_pad(MX53_PIN_KEY_COL3,
				PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH |
				PAD_CTL_100K_PU | PAD_CTL_HYS_ENABLE |
				PAD_CTL_ODE_OPENDRAIN_ENABLE);
		break;
	default:
		printf("Warning: Wrong I2C port number\n");
		break;
	}
}
void gpio_can_inactive(int id)
{
	switch (id) {
	case 0:
		mxc_free_iomux(MX35_PIN_I2C2_CLK, MUX_CONFIG_ALT1);
		mxc_free_iomux(MX35_PIN_I2C2_DAT, MUX_CONFIG_ALT1);
		mxc_iomux_set_input(MUX_IN_CAN1_CANRX, INPUT_CTL_PATH0);
		break;
	case 1:
		mxc_free_iomux(MX35_PIN_FEC_MDC, MUX_CONFIG_ALT1);
		mxc_free_iomux(MX35_PIN_FEC_MDIO, MUX_CONFIG_ALT1);
		mxc_iomux_set_input(MUX_IN_CAN2_CANRX, INPUT_CTL_PATH0);
		break;
	default:
		printk(KERN_ERR "NO such device\n");
	}
}
/*!
 * Setup GPIO for a UART port to be inactive
 *
 * @param  port         a UART port
 * @param  no_irda      indicates if the port is used for SIR
 */
void gpio_uart_inactive(int port, int no_irda)
{
	switch (port) {
	case 0:
		mxc_request_gpio(MX35_PIN_RXD1);
		mxc_request_gpio(MX35_PIN_TXD1);
		mxc_request_gpio(MX35_PIN_RTS1);
		mxc_request_gpio(MX35_PIN_CTS1);

		mxc_free_iomux(MX35_PIN_RXD1, MUX_CONFIG_GPIO);
		mxc_free_iomux(MX35_PIN_TXD1, MUX_CONFIG_GPIO);
		mxc_free_iomux(MX35_PIN_RTS1, MUX_CONFIG_GPIO);
		mxc_free_iomux(MX35_PIN_CTS1, MUX_CONFIG_GPIO);
		break;
	case 1:
		mxc_request_gpio(MX35_PIN_RXD2);
		mxc_request_gpio(MX35_PIN_TXD2);
		mxc_request_gpio(MX35_PIN_RTS2);
		mxc_request_gpio(MX35_PIN_CTS2);

		mxc_free_iomux(MX35_PIN_RXD2, MUX_CONFIG_GPIO);
		mxc_free_iomux(MX35_PIN_TXD2, MUX_CONFIG_GPIO);
		mxc_free_iomux(MX35_PIN_RTS2, MUX_CONFIG_GPIO);
		mxc_free_iomux(MX35_PIN_CTS2, MUX_CONFIG_GPIO);
		break;
	case 2:
		mxc_request_gpio(MX35_PIN_FEC_TX_CLK);
		mxc_request_gpio(MX35_PIN_FEC_RX_CLK);
		mxc_request_gpio(MX35_PIN_FEC_COL);
		mxc_request_gpio(MX35_PIN_FEC_RX_DV);

		mxc_free_iomux(MX35_PIN_FEC_TX_CLK, MUX_CONFIG_GPIO);
		mxc_free_iomux(MX35_PIN_FEC_RX_CLK, MUX_CONFIG_GPIO);
		mxc_free_iomux(MX35_PIN_FEC_COL, MUX_CONFIG_GPIO);
		mxc_free_iomux(MX35_PIN_FEC_RX_DV, MUX_CONFIG_GPIO);

		mxc_iomux_set_input(MUX_IN_UART3_UART_RTS_B, INPUT_CTL_PATH0);
		mxc_iomux_set_input(MUX_IN_UART3_UART_RXD_MUX, INPUT_CTL_PATH0);
		break;
	default:
		break;
	}
}
예제 #8
0
/*
 *  USB Host2
 */
int gpio_usbh2_active(void)
{
	mxc_request_iomux(MX35_PIN_I2C2_CLK, MUX_CONFIG_ALT2);
	mxc_iomux_set_pad(MX35_PIN_I2C2_CLK, 0x0040);

	mxc_request_iomux(MX35_PIN_I2C2_DAT, MUX_CONFIG_ALT2);
	mxc_iomux_set_input(MUX_IN_USB_UH2_USB_OC, INPUT_CTL_PATH0);
	mxc_iomux_set_pad(MX35_PIN_I2C2_DAT, 0x01c0);

	return 0;
}
예제 #9
0
static void setup_iomux_fec(void)
{
	/*FEC_MDIO*/
	mxc_request_iomux(MX53_PIN_FEC_MDIO, IOMUX_CONFIG_ALT0);
	mxc_iomux_set_pad(MX53_PIN_FEC_MDIO,
				PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
				PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
				PAD_CTL_22K_PU | PAD_CTL_ODE_OPENDRAIN_ENABLE);
	mxc_iomux_set_input(MX53_FEC_FEC_MDI_SELECT_INPUT, 0x1);

	/*FEC_MDC*/
	mxc_request_iomux(MX53_PIN_FEC_MDC, IOMUX_CONFIG_ALT0);
	mxc_iomux_set_pad(MX53_PIN_FEC_MDC, PAD_CTL_DRV_HIGH);

	/* FEC RXD1 */
	mxc_request_iomux(MX53_PIN_FEC_RXD1, IOMUX_CONFIG_ALT0);
	mxc_iomux_set_pad(MX53_PIN_FEC_RXD1,
			PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);

	/* FEC RXD0 */
	mxc_request_iomux(MX53_PIN_FEC_RXD0, IOMUX_CONFIG_ALT0);
	mxc_iomux_set_pad(MX53_PIN_FEC_RXD0,
			PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);

	 /* FEC TXD1 */
	mxc_request_iomux(MX53_PIN_FEC_TXD1, IOMUX_CONFIG_ALT0);
	mxc_iomux_set_pad(MX53_PIN_FEC_TXD1, PAD_CTL_DRV_HIGH);

	/* FEC TXD0 */
	mxc_request_iomux(MX53_PIN_FEC_TXD0, IOMUX_CONFIG_ALT0);
	mxc_iomux_set_pad(MX53_PIN_FEC_TXD0, PAD_CTL_DRV_HIGH);

	/* FEC TX_EN */
	mxc_request_iomux(MX53_PIN_FEC_TX_EN, IOMUX_CONFIG_ALT0);
	mxc_iomux_set_pad(MX53_PIN_FEC_TX_EN, PAD_CTL_DRV_HIGH);

	/* FEC TX_CLK */
	mxc_request_iomux(MX53_PIN_FEC_REF_CLK, IOMUX_CONFIG_ALT0);
	mxc_iomux_set_pad(MX53_PIN_FEC_REF_CLK,
			PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);

	/* FEC RX_ER */
	mxc_request_iomux(MX53_PIN_FEC_RX_ER, IOMUX_CONFIG_ALT0);
	mxc_iomux_set_pad(MX53_PIN_FEC_RX_ER,
			PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);

	/* FEC CRS */
	mxc_request_iomux(MX53_PIN_FEC_CRS_DV, IOMUX_CONFIG_ALT0);
	mxc_iomux_set_pad(MX53_PIN_FEC_CRS_DV,
			PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
}
예제 #10
0
static void setup_iomux_i2c(void)
{
	/* I2C1 SDA */
	mxc_request_iomux(MX53_PIN_CSI0_D8,
		IOMUX_CONFIG_ALT5 | IOMUX_CONFIG_SION);
	mxc_iomux_set_input(MX53_I2C1_IPP_SDA_IN_SELECT_INPUT,
		INPUT_CTL_PATH0);
	mxc_iomux_set_pad(MX53_PIN_CSI0_D8,
		PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH |
		PAD_CTL_100K_PU | PAD_CTL_PKE_ENABLE |
		PAD_CTL_PUE_PULL |
		PAD_CTL_ODE_OPENDRAIN_ENABLE);
	/* I2C1 SCL */
	mxc_request_iomux(MX53_PIN_CSI0_D9,
		IOMUX_CONFIG_ALT5 | IOMUX_CONFIG_SION);
	mxc_iomux_set_input(MX53_I2C1_IPP_SCL_IN_SELECT_INPUT,
		INPUT_CTL_PATH0);
	mxc_iomux_set_pad(MX53_PIN_CSI0_D9,
		PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH |
		PAD_CTL_100K_PU | PAD_CTL_PKE_ENABLE |
		PAD_CTL_PUE_PULL |
		PAD_CTL_ODE_OPENDRAIN_ENABLE);
}
/*
 *  USB Host2
 */
int gpio_usbh2_active(void)
{
	if (board_is_mx35(BOARD_REV_2)) {
		/* MUX3_CTR to be low for USB Host2 DP&DM */
		pmic_gpio_set_bit_val(MCU_GPIO_REG_GPIO_CONTROL_2, 6, 0);
		/* CAN_PWDN to be high for USB Host2 Power&OC */
		pmic_gpio_set_bit_val(MCU_GPIO_REG_GPIO_CONTROL_2, 1, 1);
	}

	mxc_request_iomux(MX35_PIN_I2C2_CLK, MUX_CONFIG_ALT2);
	mxc_iomux_set_pad(MX35_PIN_I2C2_CLK, 0x0040);

	mxc_request_iomux(MX35_PIN_I2C2_DAT, MUX_CONFIG_ALT2);
	mxc_iomux_set_input(MUX_IN_USB_UH2_USB_OC, INPUT_CTL_PATH0);
	mxc_iomux_set_pad(MX35_PIN_I2C2_DAT, 0x01c0);

	return 0;
}
예제 #12
0
static void setup_iomux_uart(void)
{
	/* UART1 RXD */
	mxc_request_iomux(MX53_PIN_ATA_DMACK, IOMUX_CONFIG_ALT3);
	mxc_iomux_set_pad(MX53_PIN_ATA_DMACK,
				PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
				PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
				PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU |
				PAD_CTL_ODE_OPENDRAIN_ENABLE);
	mxc_iomux_set_input(MX53_UART1_IPP_UART_RXD_MUX_SELECT_INPUT, 0x3);

	/* UART1 TXD */
	mxc_request_iomux(MX53_PIN_ATA_DIOW, IOMUX_CONFIG_ALT3);
	mxc_iomux_set_pad(MX53_PIN_ATA_DIOW,
				PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
				PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
				PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU |
				PAD_CTL_ODE_OPENDRAIN_ENABLE);
}
예제 #13
0
void lcd_iomux(void)
{
	/* DI2_PIN15 */
	mxc_request_iomux(MX51_PIN_DI_GP4, IOMUX_CONFIG_ALT4);

	/* Pad settings for MX51_PIN_DI2_DISP_CLK */
	mxc_iomux_set_pad(MX51_PIN_DI2_DISP_CLK, PAD_CTL_HYS_NONE |
			  PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
			  PAD_CTL_DRV_MAX | PAD_CTL_SRE_SLOW);

	/* Turn on 3.3V voltage for LCD */
	mxc_request_iomux(MX51_PIN_CSI2_D12, IOMUX_CONFIG_ALT3);
	gpio_direction_output(MX51EVK_LCD_3V3, 1);

	/* Turn on 5V voltage for LCD */
	mxc_request_iomux(MX51_PIN_CSI2_D13, IOMUX_CONFIG_ALT3);
	gpio_direction_output(MX51EVK_LCD_5V, 1);

	/* Turn on GPIO backlight */
	mxc_request_iomux(MX51_PIN_DI1_D1_CS, IOMUX_CONFIG_ALT4);
	mxc_iomux_set_input(MX51_GPIO3_IPP_IND_G_IN_4_SELECT_INPUT,
							INPUT_CTL_PATH1);
	gpio_direction_output(MX51EVK_LCD_BACKLIGHT, 1);
}
예제 #14
0
void __init mx50_yoshi_io_init(void)
{
	int i;

	for (i = 0; i < ARRAY_SIZE(mxc_iomux_pins); i++) {
		mxc_request_iomux(mxc_iomux_pins[i].pin,
		                  mxc_iomux_pins[i].mux_mode);
		if (mxc_iomux_pins[i].pad_cfg)
		        mxc_iomux_set_pad(mxc_iomux_pins[i].pin,
		                          mxc_iomux_pins[i].pad_cfg);
		if (mxc_iomux_pins[i].in_select)
		        mxc_iomux_set_input(mxc_iomux_pins[i].in_select,
		                            mxc_iomux_pins[i].in_mode);
	}

	/* SD4 CD */
	gpio_request(IOMUX_TO_GPIO(MX50_PIN_DISP_D15), "sd4_cd");
	gpio_direction_input(IOMUX_TO_GPIO(MX50_PIN_DISP_D15));

	/* SD4 WP */
	gpio_request(IOMUX_TO_GPIO(MX50_PIN_DISP_D14), "sd4_wp");
	gpio_direction_input(IOMUX_TO_GPIO(MX50_PIN_DISP_D14));

	/* PMIC Interrupt */
	gpio_request(IOMUX_TO_GPIO(MX50_PIN_UART1_CTS), "pmic_int");
	gpio_direction_input(IOMUX_TO_GPIO(MX50_PIN_UART1_CTS));

	/* WiFi Power */
	gpio_request(IOMUX_TO_GPIO(MX50_PIN_SD3_WP), "sd3_wp");
	gpio_direction_output(IOMUX_TO_GPIO(MX50_PIN_SD3_WP), 0);
	gpio_set_value(IOMUX_TO_GPIO(MX50_PIN_SD3_WP), 1);	

	/* WiFi spec, add delay */
	mdelay(40);

	gpio_request(IOMUX_TO_GPIO(MX50_PIN_SSI_RXC), "gp5_6");
	gpio_direction_output(IOMUX_TO_GPIO(MX50_PIN_SSI_RXC), 0);
	gpio_set_value(IOMUX_TO_GPIO(MX50_PIN_SSI_RXC), 1);

	gpio_request(IOMUX_TO_GPIO(MX50_PIN_EPDC_VCOM0), "epdc_vcom");
	gpio_direction_output(IOMUX_TO_GPIO(MX50_PIN_EPDC_VCOM0), 0);

	gpio_request(IOMUX_TO_GPIO(MX50_PIN_EPDC_PWRSTAT), "epdc_pwrstat");
	gpio_direction_input(IOMUX_TO_GPIO(MX50_PIN_EPDC_PWRSTAT));

	gpio_request(IOMUX_TO_GPIO(MX50_PIN_EPDC_PWRCOM), "epdc_pwrcom");
	gpio_direction_output(IOMUX_TO_GPIO(MX50_PIN_EPDC_PWRCOM), 0);

	gpio_request(IOMUX_TO_GPIO(MX50_PIN_EPDC_PWRCTRL0), "epdc_pwrctrl0");
	gpio_direction_output(IOMUX_TO_GPIO(MX50_PIN_EPDC_PWRCTRL0), 0);
	gpio_set_value(IOMUX_TO_GPIO(MX50_PIN_EPDC_PWRCTRL0), 1);

	gpio_request(IOMUX_TO_GPIO(MX50_PIN_EPDC_PWRCTRL1), "epdc_pwrctrl1");
	gpio_direction_input(IOMUX_TO_GPIO(MX50_PIN_EPDC_PWRCTRL1));

	gpio_request(IOMUX_TO_GPIO(MX50_PIN_EIM_DA4), "eim_da4");
	gpio_direction_input(IOMUX_TO_GPIO(MX50_PIN_EIM_DA4));

	gpio_request(IOMUX_TO_GPIO(MX50_PIN_OWIRE), "owire");
	gpio_direction_input(IOMUX_TO_GPIO(MX50_PIN_OWIRE));

	gpio_direction_output(IOMUX_TO_GPIO(MX50_PIN_DISP_CS), 0);
	gpio_set_value(IOMUX_TO_GPIO(MX50_PIN_DISP_CS), 0);
	mdelay(10);
	gpio_set_value(IOMUX_TO_GPIO(MX50_PIN_DISP_CS), 1);

	/* EIM_DA10 and EIM_DA11 */
	gpio_direction_output(IOMUX_TO_GPIO(MX50_PIN_EIM_DA11), 0);
	gpio_set_value(IOMUX_TO_GPIO(MX50_PIN_EIM_DA11), 0);

	gpio_direction_output(IOMUX_TO_GPIO(MX50_PIN_EIM_DA12), 0);
	gpio_set_value(IOMUX_TO_GPIO(MX50_PIN_EIM_DA12), 0);

	gpio_request(IOMUX_TO_GPIO(MX50_PIN_SD1_D2), "sd1_d2");
	gpio_direction_input(IOMUX_TO_GPIO(MX50_PIN_SD1_D2));
	gpio_request(IOMUX_TO_GPIO(MX50_PIN_SD1_CLK), "sd1_clk");
	gpio_direction_input(IOMUX_TO_GPIO(MX50_PIN_SD1_CLK));
	
	/* EPDC */
	gpio_request(IOMUX_TO_GPIO(MX50_PIN_EPDC_SDCE0), "epdc_sdce0");	
	gpio_direction_output(IOMUX_TO_GPIO(MX50_PIN_EPDC_SDCE0), 0);

	gpio_request(IOMUX_TO_GPIO(MX50_PIN_EPDC_GDSP), "epdc_gdsp");
	gpio_direction_output(IOMUX_TO_GPIO(MX50_PIN_EPDC_GDSP), 0);

	/* Accessory power good */
	gpio_direction_input(IOMUX_TO_GPIO(MX50_PIN_EIM_DA13));

	/* Accessory charging */
	gpio_direction_input(IOMUX_TO_GPIO(MX50_PIN_EIM_DA14));

	
	mxc_free_iomux(MX50_PIN_UART4_TXD, IOMUX_CONFIG_ALT0);
	mxc_request_iomux(MX50_PIN_UART4_TXD, IOMUX_CONFIG_ALT1);
	gpio_request(IOMUX_TO_GPIO(MX50_PIN_UART4_TXD), "uart4_txd");
	gpio_direction_output(IOMUX_TO_GPIO(MX50_PIN_UART4_TXD), 0);
	gpio_set_value(IOMUX_TO_GPIO(MX50_PIN_UART4_TXD), 0);
	

	/* NAND family - 1.8V */
	__raw_writel(0x2000, IO_ADDRESS(IOMUXC_BASE_ADDR) + 0x06c0);

	__raw_writel(0x2000, IO_ADDRESS(IOMUXC_BASE_ADDR) + 0x069c);
}
예제 #15
0
void __init mx51_3stack_io_init(void)
{
	int i, num;
	struct mxc_iomux_pin_cfg *pin_ptr;

	for (i = 0; i < ARRAY_SIZE(mxc_iomux_pins); i++) {
		mxc_request_iomux(mxc_iomux_pins[i].pin,
				  mxc_iomux_pins[i].mux_mode);
		if (mxc_iomux_pins[i].pad_cfg)
			mxc_iomux_set_pad(mxc_iomux_pins[i].pin,
					  mxc_iomux_pins[i].pad_cfg);
		if (mxc_iomux_pins[i].in_select)
			mxc_iomux_set_input(mxc_iomux_pins[i].in_select,
					  mxc_iomux_pins[i].in_mode);
	}

	if (enable_ata) {
		pin_ptr = ata_iomux_pins;
		num = ARRAY_SIZE(ata_iomux_pins);
	} else if (enable_sim) {
		pin_ptr = sim_iomux_pins;
		num = ARRAY_SIZE(sim_iomux_pins);
	} else {
		pin_ptr = nand_iomux_pins;
		num = ARRAY_SIZE(nand_iomux_pins);
	}

	for (i = 0; i < num; i++) {
		mxc_request_iomux(pin_ptr[i].pin, pin_ptr[i].mux_mode);
		if (pin_ptr[i].pad_cfg)
			mxc_iomux_set_pad(pin_ptr[i].pin, pin_ptr[i].pad_cfg);
		if (pin_ptr[i].in_select)
			mxc_iomux_set_input(pin_ptr[i].in_select,
					pin_ptr[i].in_mode);
	}

	/* TO3 doesn't need pad to drive CSI_DATA_EN[0] high */
	if (cpu_is_mx51_rev(CHIP_REV_3_0) > 0)
		mxc_request_iomux(MX51_PIN_EIM_A26, IOMUX_CONFIG_ALT0);

	/* Camera low power */
	gpio_request(IOMUX_TO_GPIO(MX51_PIN_CSI1_D8), "csi1_d8");
	gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_CSI1_D8), 0);
	gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_CSI1_D8), 0);
	gpio_request(IOMUX_TO_GPIO(MX51_PIN_EIM_EB2), "eim_eb2");
	gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_EIM_EB2), 0);    /* TO1 */
	gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_EIM_EB2), 0);      /* TO1 */

	/* Camera reset */
	gpio_request(IOMUX_TO_GPIO(MX51_PIN_CSI1_D9), "csi1_d9");
	gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_CSI1_D9), 0);
	gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_CSI1_D9), 1);
	gpio_request(IOMUX_TO_GPIO(MX51_PIN_DI1_D1_CS), "di1_d1_cs");
	gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_DI1_D1_CS), 0);
	gpio_request(IOMUX_TO_GPIO(MX51_PIN_GPIO1_0), "gpio1_0");
	gpio_direction_input(IOMUX_TO_GPIO(MX51_PIN_GPIO1_0));	/* SD1 CD */
	gpio_request(IOMUX_TO_GPIO(MX51_PIN_GPIO1_1), "gpio1_1");
	gpio_direction_input(IOMUX_TO_GPIO(MX51_PIN_GPIO1_1));	/* SD1 WP */

	/* EIM_D16 */
	/* osc_en is shared by SPDIF */
	gpio_request(IOMUX_TO_GPIO(MX51_PIN_EIM_D16), "eim_d16");
	gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_EIM_D16), 0);
	gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_EIM_D16), 1);

	/* LCD related gpio */
	gpio_request(IOMUX_TO_GPIO(MX51_PIN_DI1_D1_CS), "di1_d1_cs");
	gpio_request(IOMUX_TO_GPIO(MX51_PIN_DISPB2_SER_DIO), "dispb2_ser_di0");
	gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_DI1_D1_CS), 0);
	gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_DISPB2_SER_DIO), 0);
	gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_DISPB2_SER_DIO), 0);

	/* GPS related gpio */
	gpio_request(IOMUX_TO_GPIO(MX51_PIN_EIM_CS2), "eim_cs2");
	gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_EIM_CS2), 0);
	gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_EIM_CS2), 0);
	gpio_request(IOMUX_TO_GPIO(MX51_PIN_EIM_CRE), "eim_cre");
	gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_EIM_CRE), 0);
	gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_EIM_CRE), 0);
	gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_EIM_CRE), 1);
}
예제 #16
0
void __init mx51_efikamx_io_init(void)
{
	int i, num;
	struct mxc_iomux_pin_cfg *pin_ptr;

	for (i = 0; i < ARRAY_SIZE(mxc_iomux_pins); i++) {
		mxc_request_iomux(mxc_iomux_pins[i].pin,
				  mxc_iomux_pins[i].mux_mode);
		if (mxc_iomux_pins[i].pad_cfg)
			mxc_iomux_set_pad(mxc_iomux_pins[i].pin,
					  mxc_iomux_pins[i].pad_cfg);
		if (mxc_iomux_pins[i].in_select)
			mxc_iomux_set_input(mxc_iomux_pins[i].in_select,
					    mxc_iomux_pins[i].in_mode);
	}

	// enable PATA
	pin_ptr = ata_iomux_pins;
	num = ARRAY_SIZE(ata_iomux_pins);

	for (i = 0; i < num; i++) {
		mxc_request_iomux(pin_ptr[i].pin,
				  pin_ptr[i].mux_mode);
		if (pin_ptr[i].pad_cfg)
			mxc_iomux_set_pad(pin_ptr[i].pin,
					  pin_ptr[i].pad_cfg);
		if (pin_ptr[i].in_select)
			mxc_iomux_set_input(pin_ptr[i].in_select,
					    pin_ptr[i].in_mode);
	}

	// WiFi LED
	/* mxc_request_iomux(MX51_PIN_CSI1_D9, IOMUX_CONFIG_ALT3); */
	gpio_request(IOMUX_TO_GPIO(WLAN_LED_PIN), "wlan_led");
	gpio_direction_output(IOMUX_TO_GPIO(WLAN_LED_PIN)/* MX51_PIN_CSI1_D9 */, 0);
	gpio_free(IOMUX_TO_GPIO(WLAN_LED_PIN));

	// Power On LED
	/* mxc_request_iomux(MX51_PIN_CSI1_VSYNC, IOMUX_CONFIG_ALT3); */
	gpio_request(IOMUX_TO_GPIO(POWER_LED_PIN), "power_led");
	gpio_direction_output(IOMUX_TO_GPIO(POWER_LED_PIN)/* MX51_PIN_CSI1_VSYNC */, 1);
	gpio_free(IOMUX_TO_GPIO(POWER_LED_PIN));

	// Sleep LED
	/* mxc_request_iomux(MX51_PIN_CSI1_HSYNC, IOMUX_CONFIG_ALT3); */
	gpio_request(IOMUX_TO_GPIO(SLEEP_LED_PIN), "sleep_led");	
	gpio_direction_output(IOMUX_TO_GPIO(SLEEP_LED_PIN)/* MX51_PIN_CSI1_HSYNC */, 0);
	gpio_free(IOMUX_TO_GPIO(SLEEP_LED_PIN));

	// register platform device for LEDs now we fiddled them
	(void)platform_device_register(&mx51_efikamx_leds_device);

	//ron: USB Hub Reset
	mxc_request_iomux(MX51_PIN_GPIO1_5, IOMUX_CONFIG_ALT0);
	mxc_iomux_set_pad(MX51_PIN_GPIO1_5, PAD_CTL_DRV_HIGH |
			  PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
	gpio_request(IOMUX_TO_GPIO(MX51_PIN_GPIO1_5), "usb_hub_reset");
	gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_GPIO1_5), 1);
	msleep(1);
	gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_GPIO1_5), 0);
	msleep(1);
	gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_GPIO1_5), 1);

	//ron: change PMIC interrupt from GPIO1_8 to GPIO1_6
	
	gpio_request(IOMUX_TO_GPIO(MX51_PIN_GPIO1_6), "pmic_intr");
	gpio_direction_input(IOMUX_TO_GPIO(MX51_PIN_GPIO1_6));
	
	gpio_request(IOMUX_TO_GPIO(MX51_PIN_GPIO1_0), "sdhc1_cd");
	gpio_direction_input(IOMUX_TO_GPIO(MX51_PIN_GPIO1_0));		/* SD1 CD */
	gpio_request(IOMUX_TO_GPIO(MX51_PIN_GPIO1_8), "sdhc2_cd");
	gpio_direction_input(IOMUX_TO_GPIO(MX51_PIN_GPIO1_8));		/*ron: SDHC2 CD*/
	
	gpio_request(IOMUX_TO_GPIO(MX51_PIN_GPIO1_1), "sdhc1_wp");
	gpio_direction_input(IOMUX_TO_GPIO(MX51_PIN_GPIO1_1));		/* SD1 WP */
	gpio_request(IOMUX_TO_GPIO(MX51_PIN_GPIO1_7), "sdhc2_wp");
	gpio_direction_input(IOMUX_TO_GPIO(MX51_PIN_GPIO1_7));		/*ron: SDHC2 WP*/

	/* enable BlueTooth */
	gpio_request(IOMUX_TO_GPIO(MX51_PIN_EIM_A17), "bluetooth_enable");
	gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_EIM_A17), 0);
	msleep(10);
	gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_EIM_A17), 1);

	/* pull low wlan_on# */
	gpio_request(IOMUX_TO_GPIO(MX51_PIN_EIM_A22), "wlan_on");
    gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_EIM_A22), 0);
	msleep(10);

	/* pull low-high pulse wlan_rst# */
	gpio_request(IOMUX_TO_GPIO(MX51_PIN_EIM_A16), "wlan_rst");
    gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_EIM_A16), 0);
	msleep(10);
	gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_EIM_A16), 1);

	mxc_free_iomux(MX51_PIN_EIM_A24, IOMUX_CONFIG_ALT2);
	mxc_free_iomux(MX51_PIN_EIM_A25, IOMUX_CONFIG_ALT2);
	mxc_free_iomux(MX51_PIN_EIM_D18, IOMUX_CONFIG_ALT2);
	mxc_free_iomux(MX51_PIN_EIM_D20, IOMUX_CONFIG_ALT2);
	mxc_free_iomux(MX51_PIN_EIM_D21, IOMUX_CONFIG_ALT2);
	mxc_free_iomux(MX51_PIN_EIM_D23, IOMUX_CONFIG_ALT2);
	mxc_free_iomux(MX51_PIN_EIM_D16, IOMUX_CONFIG_ALT2);
	mxc_free_iomux(MX51_PIN_EIM_D17, IOMUX_CONFIG_ALT2);
	mxc_free_iomux(MX51_PIN_EIM_D19, IOMUX_CONFIG_ALT2);
	mxc_free_iomux(MX51_PIN_GPIO1_2, IOMUX_CONFIG_ALT2);
	mxc_free_iomux(MX51_PIN_GPIO1_3, IOMUX_CONFIG_ALT2);
	mxc_free_iomux(MX51_PIN_EIM_LBA, IOMUX_CONFIG_GPIO);

	/* i2c2 SDA */
	mxc_request_iomux(MX51_PIN_KEY_COL5,
			  IOMUX_CONFIG_ALT3 | IOMUX_CONFIG_SION);
	mxc_iomux_set_input(MUX_IN_I2C2_IPP_SDA_IN_SELECT_INPUT,
			    INPUT_CTL_PATH1);
	mxc_iomux_set_pad(MX51_PIN_KEY_COL5,
			  PAD_CTL_SRE_FAST |
			  PAD_CTL_ODE_OPENDRAIN_ENABLE |
			  PAD_CTL_DRV_HIGH | PAD_CTL_100K_PU |
			  PAD_CTL_HYS_ENABLE);

	/* i2c2 SCL */
	mxc_request_iomux(MX51_PIN_KEY_COL4,
			  IOMUX_CONFIG_ALT3 | IOMUX_CONFIG_SION);
	mxc_iomux_set_input(MUX_IN_I2C2_IPP_SCL_IN_SELECT_INPUT,
			    INPUT_CTL_PATH1);
	mxc_iomux_set_pad(MX51_PIN_KEY_COL4,
			  PAD_CTL_SRE_FAST |
			  PAD_CTL_ODE_OPENDRAIN_ENABLE |
			  PAD_CTL_DRV_HIGH | PAD_CTL_100K_PU |
			  PAD_CTL_HYS_ENABLE);

	/* MX51_PIN_EIM_D27 - De-assert USB PHY RESETB */
	mxc_request_iomux(MX51_PIN_EIM_D27, IOMUX_CONFIG_ALT1);
	mxc_iomux_set_pad(MX51_PIN_EIM_D27, PAD_CTL_DRV_HIGH |
			  PAD_CTL_HYS_NONE | PAD_CTL_PUE_KEEPER |
			  PAD_CTL_100K_PU | PAD_CTL_ODE_OPENDRAIN_NONE |
			  PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
	gpio_request(IOMUX_TO_GPIO(MX51_PIN_EIM_D27), "usb_phy_resetb");
	gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_EIM_D27), 1);

	/* hphone_det_b */
	mxc_request_iomux(MX51_PIN_DISPB2_SER_RS, IOMUX_CONFIG_ALT4);
	mxc_iomux_set_pad(MX51_PIN_DISPB2_SER_RS, PAD_CTL_100K_PU);
	gpio_request(IOMUX_TO_GPIO(MX51_PIN_DISPB2_SER_RS), "hphone_det_b");	
	gpio_direction_input(IOMUX_TO_GPIO(MX51_PIN_DISPB2_SER_RS));

	/* audio_clk_en_b */
	mxc_request_iomux(MX51_PIN_CSPI1_RDY, IOMUX_CONFIG_ALT3);
	mxc_iomux_set_pad(MX51_PIN_CSPI1_RDY, PAD_CTL_DRV_HIGH |
			  PAD_CTL_HYS_NONE | PAD_CTL_PUE_KEEPER |
			  PAD_CTL_100K_PU | PAD_CTL_ODE_OPENDRAIN_NONE |
			  PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
	gpio_request(IOMUX_TO_GPIO(MX51_PIN_CSPI1_RDY), "audio_clk_en_b");	
	gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_CSPI1_RDY), 0);

	/* Deassert VGA reset to free i2c bus */
	gpio_request(IOMUX_TO_GPIO(MX51_PIN_EIM_A19), "vga_reset");
	gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_EIM_A19), 1);

	/* LCD related gpio */
	gpio_request(IOMUX_TO_GPIO(MX51_PIN_DI1_D1_CS), "lcd_gpio");
	gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_DI1_D1_CS), 0);
	
	/* DVI Reset - Assert for i2c disabled mode */
	gpio_request(IOMUX_TO_GPIO(MX51_PIN_DISPB2_SER_DIN), "dvi_reset");
	gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_DISPB2_SER_DIN), 0);

	/* DVI Power-down */
	gpio_request(IOMUX_TO_GPIO(MX51_PIN_DISPB2_SER_DIO), "dvi_power");
	gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_DISPB2_SER_DIO), 1);

	//retrieve board id rev1.1: 1,1	rev1.2: 0,1    notice that this cannot be execute too early!
	gpio_request(IOMUX_TO_GPIO(MX51_PIN_NANDF_CS0), "board_id1");
	gpio_direction_input(IOMUX_TO_GPIO(MX51_PIN_NANDF_CS0));
	board_id[0] = gpio_get_value(IOMUX_TO_GPIO(MX51_PIN_NANDF_CS0));

	gpio_request(IOMUX_TO_GPIO(MX51_PIN_NANDF_CS1), "board_id2");
	gpio_direction_input(IOMUX_TO_GPIO(MX51_PIN_NANDF_CS1));
	board_id[1] = gpio_get_value(IOMUX_TO_GPIO(MX51_PIN_NANDF_CS1));

	/* Watchdog */
	/* board rev1.1: MX51_PIN_DI1_PIN13, rev1.2: MX51_PIN_GPIO1_4 */
	gpio_request(IOMUX_TO_GPIO(MX51_PIN_DI1_PIN13), "wdog_rst");
	gpio_direction_input(MX51_PIN_DI1_PIN13);
}
예제 #17
0
/*!
 * Setup GPIO for a UART port to be active
 *
 * @param  port         a UART port
 * @param  no_irda      indicates if the port is used for SIR
 */
void gpio_uart_active(int port, int no_irda)
{
	/*
	 * Configure the IOMUX control registers for the UART signals
	 * and enable the UART transceivers
	 */
	switch (port) {
		/* UART 1 IOMUX Configs */
	case 0:
		mxc_request_iomux(MX37_PIN_UART1_RXD, IOMUX_CONFIG_ALT0);
		mxc_iomux_set_pad(MX37_PIN_UART1_RXD, PAD_CTL_HYS_ENABLE |
				  PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_PULL |
				  PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
		mxc_iomux_set_input(MUX_IN_UART1_UART_RXD_MUX, INPUT_CTL_PATH4);
		mxc_request_iomux(MX37_PIN_UART1_TXD, IOMUX_CONFIG_ALT0);
		mxc_iomux_set_pad(MX37_PIN_UART1_TXD, PAD_CTL_HYS_ENABLE |
				  PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_PULL |
				  PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
#if 0
		mxc_request_iomux(MX37_PIN_UART1_RTS, IOMUX_CONFIG_ALT0);
		mxc_iomux_set_pad(MX37_PIN_UART1_RTS, PAD_CTL_HYS_ENABLE |
				  PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_PULL |
				  PAD_CTL_DRV_HIGH);
		mxc_iomux_set_input(MUX_IN_UART1_UART_RTS_B, INPUT_CTL_PATH4);
		mxc_request_iomux(MX37_PIN_UART1_CTS, IOMUX_CONFIG_ALT0);
		mxc_iomux_set_pad(MX37_PIN_UART1_CTS, PAD_CTL_HYS_ENABLE |
				  PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_PULL |
				  PAD_CTL_DRV_HIGH);
#endif
		break;
	case 1:
#if 0	//
		mxc_request_iomux(MX37_PIN_UART1_DCD, IOMUX_CONFIG_ALT3);
		mxc_iomux_set_pad(MX37_PIN_UART1_DCD, PAD_CTL_HYS_ENABLE |
				  PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_PULL |
				  PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
		mxc_iomux_set_input(MUX_IN_UART2_UART_RXD_MUX, INPUT_CTL_PATH1);
		mxc_request_iomux(MX37_PIN_UART1_RI, IOMUX_CONFIG_ALT3);
		mxc_iomux_set_pad(MX37_PIN_UART1_RI, PAD_CTL_HYS_ENABLE |
				  PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_PULL |
				  PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
		mxc_request_iomux(MX37_PIN_UART1_DSR, IOMUX_CONFIG_ALT3);
		mxc_iomux_set_pad(MX37_PIN_UART1_DSR, PAD_CTL_HYS_ENABLE |
				  PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_PULL |
				  PAD_CTL_DRV_HIGH);
		mxc_iomux_set_input(MUX_IN_UART2_UART_RTS_B, INPUT_CTL_PATH1);
		mxc_request_iomux(MX37_PIN_UART1_DTR, IOMUX_CONFIG_ALT3);
		mxc_iomux_set_pad(MX37_PIN_UART1_DTR, PAD_CTL_HYS_ENABLE |
				  PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_PULL |
				  PAD_CTL_DRV_HIGH);
#endif
		break;
	case 2:
#if 0
		mxc_iomux_set_input(MUX_IN_UART3_UART_RXD_MUX, INPUT_CTL_PATH0);
		mxc_request_iomux(MX37_PIN_AUD3_BB_TXD, IOMUX_CONFIG_ALT3);
		mxc_iomux_set_pad(MX37_PIN_AUD3_BB_TXD, PAD_CTL_HYS_ENABLE |
				  PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_PULL |
				  PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
		mxc_request_iomux(MX37_PIN_AUD3_BB_RXD, IOMUX_CONFIG_ALT3);
		mxc_iomux_set_pad(MX37_PIN_AUD3_BB_RXD, PAD_CTL_HYS_ENABLE |
				  PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_PULL |
				  PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
#endif
		break;
	default:
		break;
	}
}
예제 #18
0
void __init mx53_evk_io_init(void)
{
	int i;

	for (i = 0; i < ARRAY_SIZE(mxc_iomux_pins); i++) {
		mxc_request_iomux(mxc_iomux_pins[i].pin,
				  mxc_iomux_pins[i].mux_mode);
		if (mxc_iomux_pins[i].pad_cfg)
			mxc_iomux_set_pad(mxc_iomux_pins[i].pin,
					  mxc_iomux_pins[i].pad_cfg);
		if (mxc_iomux_pins[i].in_select)
			mxc_iomux_set_input(mxc_iomux_pins[i].in_select,
					    mxc_iomux_pins[i].in_mode);
	}

	if (board_is_mx53_arm2()) {
		/* MX53 ARM2 CPU board */
		pr_info("MX53 ARM2 board \n");
		for (i = 0; i < ARRAY_SIZE(mx53_arm2_iomux_pins); i++) {
			mxc_request_iomux(mx53_arm2_iomux_pins[i].pin,
					  mx53_arm2_iomux_pins[i].mux_mode);
			if (mx53_arm2_iomux_pins[i].pad_cfg)
				mxc_iomux_set_pad(mx53_arm2_iomux_pins[i].pin,
						  mx53_arm2_iomux_pins[i].pad_cfg);
			if (mx53_arm2_iomux_pins[i].in_select)
				mxc_iomux_set_input(mx53_arm2_iomux_pins[i].in_select,
						    mx53_arm2_iomux_pins[i].in_mode);
		}

		/* Config GPIO for OTG VBus */
		mxc_iomux_set_pad(MX53_PIN_EIM_D22, PAD_CTL_DRV_HIGH |
				PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
		gpio_request(IOMUX_TO_GPIO(MX53_PIN_EIM_D22), "gpio3_22");
		gpio_direction_output(IOMUX_TO_GPIO(MX53_PIN_EIM_D22), 0);
		gpio_set_value(IOMUX_TO_GPIO(MX53_PIN_EIM_D22), 1);

		gpio_request(IOMUX_TO_GPIO(MX53_PIN_GPIO_1), "gpio1_1");
		gpio_direction_input(IOMUX_TO_GPIO(MX53_PIN_GPIO_1));	/* SD1 CD */

		gpio_request(IOMUX_TO_GPIO(MX53_PIN_DI0_PIN4), "gpio4_20");
		gpio_direction_output(IOMUX_TO_GPIO(MX53_PIN_DI0_PIN4), 0);
		gpio_set_value(IOMUX_TO_GPIO(MX53_PIN_DI0_PIN4), 1);
	} else {
		/* MX53 EVK board */
		pr_info("MX53 EVK board \n");
			for (i = 0; i < ARRAY_SIZE(mx53_evk_iomux_pins); i++) {
			mxc_request_iomux(mx53_evk_iomux_pins[i].pin,
					  mx53_evk_iomux_pins[i].mux_mode);
			if (mx53_evk_iomux_pins[i].pad_cfg)
				mxc_iomux_set_pad(mx53_evk_iomux_pins[i].pin,
						  mx53_evk_iomux_pins[i].pad_cfg);
			if (mx53_evk_iomux_pins[i].in_select)
				mxc_iomux_set_input(mx53_evk_iomux_pins[i].in_select,
						    mx53_evk_iomux_pins[i].in_mode);
		}
		/* Host1 Vbus with GPIO high */
		mxc_iomux_set_pad(MX53_PIN_ATA_DA_2, PAD_CTL_DRV_HIGH |
				PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
		gpio_request(IOMUX_TO_GPIO(MX53_PIN_ATA_DA_2), "gpio7_8");
		gpio_direction_output(IOMUX_TO_GPIO(MX53_PIN_ATA_DA_2), 1);
		/* shutdown the Host1 Vbus when system bring up,
		 * Vbus will be opened in Host1 driver's probe function */
		gpio_set_value(IOMUX_TO_GPIO(MX53_PIN_ATA_DA_2), 0);

		/* USB HUB RESET - De-assert USB HUB RESET_N */
		mxc_iomux_set_pad(MX53_PIN_CSI0_DATA_EN, PAD_CTL_DRV_HIGH |
				  PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
		gpio_request(IOMUX_TO_GPIO(MX53_PIN_CSI0_DATA_EN), "gpio5_20");
		gpio_direction_output(IOMUX_TO_GPIO(MX53_PIN_CSI0_DATA_EN), 0);

		msleep(1);
		gpio_set_value(IOMUX_TO_GPIO(MX53_PIN_CSI0_DATA_EN), 0);
		msleep(1);
		gpio_set_value(IOMUX_TO_GPIO(MX53_PIN_CSI0_DATA_EN), 1);

		/* Config GPIO for OTG VBus */
		mxc_iomux_set_pad(MX53_PIN_EIM_A23, PAD_CTL_DRV_HIGH |
				PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
		gpio_request(IOMUX_TO_GPIO(MX53_PIN_EIM_A23), "gpio6_6");
		gpio_direction_output(IOMUX_TO_GPIO(MX53_PIN_EIM_A23), 0);

		if (board_is_mx53_evk_a()) /*rev A,"1" disable, "0" enable vbus*/
			gpio_set_value(IOMUX_TO_GPIO(MX53_PIN_EIM_A23), 1);
		else if (board_is_mx53_evk_b()) /* rev B,"0" disable,"1" enable Vbus*/
			gpio_set_value(IOMUX_TO_GPIO(MX53_PIN_EIM_A23), 0);

		gpio_request(IOMUX_TO_GPIO(MX53_PIN_EIM_DA13), "gpio3_13");
		gpio_direction_input(IOMUX_TO_GPIO(MX53_PIN_EIM_DA13));	/* SD1 CD */
		gpio_request(IOMUX_TO_GPIO(MX53_PIN_EIM_DA14), "gpio3_14");
		gpio_direction_input(IOMUX_TO_GPIO(MX53_PIN_EIM_DA14));	/* SD1 WP */

		/* SD3 CD */
		gpio_request(IOMUX_TO_GPIO(MX53_PIN_EIM_DA11), "gpio3_11");
		gpio_direction_input(IOMUX_TO_GPIO(MX53_PIN_EIM_DA11));

		/* SD3 WP */
		gpio_request(IOMUX_TO_GPIO(MX53_PIN_EIM_DA12), "gpio3_12");
		gpio_direction_input(IOMUX_TO_GPIO(MX53_PIN_EIM_DA11));

		/* reset FEC PHY */
		gpio_request(IOMUX_TO_GPIO(MX53_PIN_ATA_DA_0), "gpio7_6");
		gpio_direction_output(IOMUX_TO_GPIO(MX53_PIN_ATA_DA_0), 0);
		gpio_set_value(IOMUX_TO_GPIO(MX53_PIN_ATA_DA_0), 0);
		msleep(1);
		gpio_set_value(IOMUX_TO_GPIO(MX53_PIN_ATA_DA_0), 1);

		/* CS42888 reset GPIO */
		gpio_direction_output(IOMUX_TO_GPIO(MX53_PIN_GPIO_12), 0);
		gpio_set_value(IOMUX_TO_GPIO(MX53_PIN_GPIO_12), 0);

	}

	/* DVI Detect */
	gpio_request(IOMUX_TO_GPIO(MX53_PIN_EIM_D31), "gpio3_31");
	gpio_direction_input(IOMUX_TO_GPIO(MX53_PIN_EIM_D31));
	/* DVI Reset - Assert for i2c disabled mode */
	gpio_request(IOMUX_TO_GPIO(MX53_PIN_EIM_WAIT), "gpio5_0");
	gpio_set_value(IOMUX_TO_GPIO(MX53_PIN_EIM_WAIT), 0);
	gpio_direction_output(IOMUX_TO_GPIO(MX53_PIN_EIM_WAIT), 0);
	/* DVI Power-down */
	gpio_request(IOMUX_TO_GPIO(MX53_PIN_EIM_D24), "gpio3_24");
	gpio_direction_output(IOMUX_TO_GPIO(MX53_PIN_EIM_D24), 0);
	gpio_set_value(IOMUX_TO_GPIO(MX53_PIN_EIM_D24), 1);
	/* DVI I2C enable */
	gpio_request(IOMUX_TO_GPIO(MX53_PIN_EIM_D28), "gpio3_28");
	gpio_direction_output(IOMUX_TO_GPIO(MX53_PIN_EIM_D28), 0);
	gpio_set_value(IOMUX_TO_GPIO(MX53_PIN_EIM_D28), 0);

	for (i = 0; i <  ARRAY_SIZE(nand_iomux_pins); i++) {
		mxc_request_iomux(nand_iomux_pins[i].pin,
					nand_iomux_pins[i].mux_mode);
		if (nand_iomux_pins[i].pad_cfg)
			mxc_iomux_set_pad(nand_iomux_pins[i].pin,
					nand_iomux_pins[i].pad_cfg);
		if (nand_iomux_pins[i].in_select)
			mxc_iomux_set_input(nand_iomux_pins[i].in_select,
					nand_iomux_pins[i].in_mode);
	}

	gpio_request(IOMUX_TO_GPIO(MX53_PIN_GPIO_16), "gpio7_11");
	gpio_direction_input(IOMUX_TO_GPIO(MX53_PIN_GPIO_16));	/*PMIC_INT*/

	/* headphone_det_b */
	mxc_request_iomux(MX53_PIN_ATA_DATA5, IOMUX_CONFIG_GPIO);
	mxc_iomux_set_pad(MX53_PIN_ATA_DATA5, PAD_CTL_100K_PU);
	gpio_request(IOMUX_TO_GPIO(MX53_PIN_ATA_DATA5), "gpio2_5");
	gpio_direction_input(IOMUX_TO_GPIO(MX53_PIN_ATA_DATA5));

	/* power key */

	/* LCD related gpio */

	/* Camera reset */
	gpio_request(IOMUX_TO_GPIO(MX53_PIN_GPIO_10), "gpio4_0");
	gpio_direction_output(IOMUX_TO_GPIO(MX53_PIN_GPIO_10), 0);
	gpio_set_value(IOMUX_TO_GPIO(MX53_PIN_GPIO_10), 1);

	/* TVIN reset */
	gpio_request(IOMUX_TO_GPIO(MX53_PIN_CSI0_D7), "gpio5_25");
	gpio_direction_output(IOMUX_TO_GPIO(MX53_PIN_CSI0_D7), 0);
	gpio_set_value(IOMUX_TO_GPIO(MX53_PIN_CSI0_D7), 0);
	msleep(5);
	gpio_set_value(IOMUX_TO_GPIO(MX53_PIN_CSI0_D7), 1);

	/* CAN1 enable GPIO*/
	gpio_direction_output(IOMUX_TO_GPIO(MX53_PIN_GPIO_18), 0);
	gpio_set_value(IOMUX_TO_GPIO(MX53_PIN_GPIO_18), 0);
	gpio_direction_output(IOMUX_TO_GPIO(MX53_PIN_GPIO_17), 0);
	gpio_set_value(IOMUX_TO_GPIO(MX53_PIN_GPIO_17), 0);

	/* CAN2 enable GPIO*/
	gpio_direction_output(IOMUX_TO_GPIO(MX53_PIN_CSI0_D6), 0);
	gpio_set_value(IOMUX_TO_GPIO(MX53_PIN_CSI0_D6), 0);
	gpio_direction_output(IOMUX_TO_GPIO(MX53_PIN_GPIO_14), 0);
	gpio_set_value(IOMUX_TO_GPIO(MX53_PIN_GPIO_14), 0);

	if (enable_spdif) {
		mxc_free_iomux(MX53_PIN_GPIO_19, IOMUX_CONFIG_ALT1);
		mxc_request_iomux(MX53_PIN_GPIO_19, IOMUX_CONFIG_ALT3);
		mxc_iomux_set_pad(MX53_PIN_GPIO_19,
			PAD_CTL_DRV_HIGH | PAD_CTL_HYS_ENABLE |
			PAD_CTL_PUE_PULL | PAD_CTL_100K_PU |
			PAD_CTL_PKE_ENABLE);
	} else {
		/* GPIO for CAN 12V */
		gpio_direction_output(IOMUX_TO_GPIO(MX53_PIN_GPIO_19), 0);
		gpio_set_value(IOMUX_TO_GPIO(MX53_PIN_GPIO_19), 0);
	}
}
예제 #19
0
void __init mx51_babbage_io_init(void)
{
	int i;

	/* Work-around For external USB HUB chip to use default configuration
	   by reseting hub with i2c lines pulled low */
	mxc_request_iomux(MX51_PIN_GPIO1_7, IOMUX_CONFIG_GPIO);
	mxc_iomux_set_pad(MX51_PIN_GPIO1_7, PAD_CTL_DRV_HIGH |
			  PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
	gpio_request(IOMUX_TO_GPIO(MX51_PIN_GPIO1_7), "gpio1_7");
	gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_GPIO1_7), 0);

	if (cpu_is_mx51_rev(CHIP_REV_1_1) == 1) {
		/* Drive I2C1 SDA line low */
		mxc_request_iomux(MX51_PIN_GPIO1_3, IOMUX_CONFIG_ALT0);
		mxc_iomux_set_pad(MX51_PIN_GPIO1_3, PAD_CTL_DRV_HIGH |
				  PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
		gpio_request(IOMUX_TO_GPIO(MX51_PIN_GPIO1_3), "gpio1_3");
		gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_GPIO1_3), 0);
		gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_GPIO1_3), 0);

		/* Drive I2C1 SCL line low */
		mxc_request_iomux(MX51_PIN_GPIO1_2, IOMUX_CONFIG_ALT0);
		mxc_iomux_set_pad(MX51_PIN_GPIO1_2, PAD_CTL_DRV_HIGH |
				  PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
		gpio_request(IOMUX_TO_GPIO(MX51_PIN_GPIO1_2), "gpio1_2");
		gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_GPIO1_2), 0);
		gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_GPIO1_2), 0);

		msleep(5);
		mxc_free_iomux(MX51_PIN_GPIO1_2, IOMUX_CONFIG_ALT2);
		mxc_free_iomux(MX51_PIN_GPIO1_3, IOMUX_CONFIG_ALT2);
	}

	/* USB HUB RESET - De-assert USB HUB RESET_N */
	msleep(1);
	gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_GPIO1_7), 0);
	msleep(1);
	gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_GPIO1_7), 1);

	for (i = 0; i < ARRAY_SIZE(mxc_iomux_pins); i++) {
		mxc_request_iomux(mxc_iomux_pins[i].pin,
				  mxc_iomux_pins[i].mux_mode);
		if (mxc_iomux_pins[i].pad_cfg)
			mxc_iomux_set_pad(mxc_iomux_pins[i].pin,
					  mxc_iomux_pins[i].pad_cfg);
		if (mxc_iomux_pins[i].in_select)
			mxc_iomux_set_input(mxc_iomux_pins[i].in_select,
					    mxc_iomux_pins[i].in_mode);
	}

	gpio_request(IOMUX_TO_GPIO(MX51_PIN_GPIO1_8), "gpio1_8");
	gpio_request(IOMUX_TO_GPIO(MX51_PIN_GPIO1_0), "gpio1_0");
	gpio_request(IOMUX_TO_GPIO(MX51_PIN_GPIO1_1), "gpio1_1");
	gpio_direction_input(IOMUX_TO_GPIO(MX51_PIN_GPIO1_8));
	gpio_direction_input(IOMUX_TO_GPIO(MX51_PIN_GPIO1_0));	/* SD1 CD */
	gpio_direction_input(IOMUX_TO_GPIO(MX51_PIN_GPIO1_1));	/* SD1 WP */
	if (board_is_rev(BOARD_REV_2)) {
		/* SD2 CD for BB2.5 */
		gpio_request(IOMUX_TO_GPIO(MX51_PIN_GPIO1_6), "gpio1_6");
		gpio_direction_input(IOMUX_TO_GPIO(MX51_PIN_GPIO1_6));
	} else {
		/* SD2 CD for BB2.0 */
		gpio_request(IOMUX_TO_GPIO(MX51_PIN_GPIO1_4), "gpio1_4");
		gpio_direction_input(IOMUX_TO_GPIO(MX51_PIN_GPIO1_4));
	}
	gpio_request(IOMUX_TO_GPIO(MX51_PIN_GPIO1_5), "gpio1_5");
	gpio_direction_input(IOMUX_TO_GPIO(MX51_PIN_GPIO1_5));	/* SD2 WP */

	/* reset FEC PHY */
	gpio_request(IOMUX_TO_GPIO(MX51_PIN_EIM_A20), "eim_a20");
	gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_EIM_A20), 0);
	gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_EIM_A20), 0);
	msleep(10);
	gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_EIM_A20), 1);

	/* reset FM */
	gpio_request(IOMUX_TO_GPIO(MX51_PIN_EIM_A21), "eim_a21");
	gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_EIM_A21), 0);
	gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_EIM_A21), 0);
	msleep(10);
	gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_EIM_A21), 1);

	if (cpu_is_mx51_rev(CHIP_REV_1_1) == 1) {
		/* MX51_PIN_EIM_CRE - De-assert USB PHY RESETB */
		gpio_request(IOMUX_TO_GPIO(MX51_PIN_EIM_CRE), "eim_cre");
		gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_EIM_CRE), 0);
		gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_EIM_CRE), 1);

		/* hphone_det_b */
		gpio_request(IOMUX_TO_GPIO(MX51_PIN_NANDF_CS0), "nandf_cs0");
		gpio_direction_input(IOMUX_TO_GPIO(MX51_PIN_NANDF_CS0));
	} else {
		mxc_free_iomux(MX51_PIN_EIM_D21, IOMUX_CONFIG_ALT2);
		mxc_free_iomux(MX51_PIN_EIM_A24, IOMUX_CONFIG_ALT2);
		mxc_free_iomux(MX51_PIN_EIM_A25, IOMUX_CONFIG_ALT2);
		mxc_free_iomux(MX51_PIN_EIM_D18, IOMUX_CONFIG_ALT2);
		mxc_free_iomux(MX51_PIN_EIM_D20, IOMUX_CONFIG_ALT2);
		mxc_free_iomux(MX51_PIN_EIM_D21, IOMUX_CONFIG_ALT2);
		mxc_free_iomux(MX51_PIN_EIM_D16, IOMUX_CONFIG_ALT2);
		mxc_free_iomux(MX51_PIN_EIM_D17, IOMUX_CONFIG_ALT2);
		mxc_free_iomux(MX51_PIN_EIM_D19, IOMUX_CONFIG_ALT2);
		mxc_free_iomux(MX51_PIN_GPIO1_2, IOMUX_CONFIG_ALT2);
		mxc_free_iomux(MX51_PIN_GPIO1_3, IOMUX_CONFIG_ALT2);
		mxc_free_iomux(MX51_PIN_EIM_LBA, IOMUX_CONFIG_GPIO);
		mxc_free_iomux(MX51_PIN_NANDF_CS0, IOMUX_CONFIG_GPIO);

		/* i2c1 SDA */
		mxc_request_iomux(MX51_PIN_EIM_D16,
				  IOMUX_CONFIG_ALT4 | IOMUX_CONFIG_SION);
		mxc_iomux_set_input(MUX_IN_I2C1_IPP_SDA_IN_SELECT_INPUT,
				    INPUT_CTL_PATH0);
		mxc_iomux_set_pad(MX51_PIN_EIM_D16, PAD_CTL_SRE_FAST |
				  PAD_CTL_ODE_OPENDRAIN_ENABLE |
				  PAD_CTL_DRV_HIGH | PAD_CTL_100K_PU |
				  PAD_CTL_HYS_ENABLE);

		/* i2c1 SCL */
		mxc_request_iomux(MX51_PIN_EIM_D19,
				  IOMUX_CONFIG_ALT4 | IOMUX_CONFIG_SION);
		mxc_iomux_set_input(MUX_IN_I2C1_IPP_SCL_IN_SELECT_INPUT,
				    INPUT_CTL_PATH0);
		mxc_iomux_set_pad(MX51_PIN_EIM_D19, PAD_CTL_SRE_FAST |
				  PAD_CTL_ODE_OPENDRAIN_ENABLE |
				  PAD_CTL_DRV_HIGH | PAD_CTL_100K_PU |
				  PAD_CTL_HYS_ENABLE);

		/* i2c2 SDA */
		mxc_request_iomux(MX51_PIN_KEY_COL5,
				  IOMUX_CONFIG_ALT3 | IOMUX_CONFIG_SION);
		mxc_iomux_set_input(MUX_IN_I2C2_IPP_SDA_IN_SELECT_INPUT,
				    INPUT_CTL_PATH1);
		mxc_iomux_set_pad(MX51_PIN_KEY_COL5,
				  PAD_CTL_SRE_FAST |
				  PAD_CTL_ODE_OPENDRAIN_ENABLE |
				  PAD_CTL_DRV_HIGH | PAD_CTL_100K_PU |
				  PAD_CTL_HYS_ENABLE);

		/* i2c2 SCL */
		mxc_request_iomux(MX51_PIN_KEY_COL4,
				  IOMUX_CONFIG_ALT3 | IOMUX_CONFIG_SION);
		mxc_iomux_set_input(MUX_IN_I2C2_IPP_SCL_IN_SELECT_INPUT,
				    INPUT_CTL_PATH1);
		mxc_iomux_set_pad(MX51_PIN_KEY_COL4,
				  PAD_CTL_SRE_FAST |
				  PAD_CTL_ODE_OPENDRAIN_ENABLE |
				  PAD_CTL_DRV_HIGH | PAD_CTL_100K_PU |
				  PAD_CTL_HYS_ENABLE);

		/* Drive 26M_OSC_EN line high */
		mxc_request_iomux(MX51_PIN_DI1_PIN12, IOMUX_CONFIG_ALT4);
		mxc_iomux_set_pad(MX51_PIN_DI1_PIN12, PAD_CTL_DRV_HIGH |
				  PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
		gpio_request(IOMUX_TO_GPIO(MX51_PIN_DI1_PIN12), "di1_pin12");
		gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_DI1_PIN12), 0);
		gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_DI1_PIN12), 1);

		/* Drive USB_CLK_EN_B line low */
		mxc_request_iomux(MX51_PIN_EIM_D17, IOMUX_CONFIG_ALT1);
		mxc_iomux_set_pad(MX51_PIN_EIM_D17, PAD_CTL_DRV_HIGH |
				  PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
		gpio_request(IOMUX_TO_GPIO(MX51_PIN_EIM_D17), "eim_d17");
		gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_EIM_D17), 0);
		gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_EIM_D17), 0);

		/* MX51_PIN_EIM_D21 - De-assert USB PHY RESETB */
		mxc_request_iomux(MX51_PIN_EIM_D21, IOMUX_CONFIG_ALT1);
		mxc_iomux_set_pad(MX51_PIN_EIM_D21, PAD_CTL_DRV_HIGH |
				  PAD_CTL_HYS_NONE | PAD_CTL_PUE_KEEPER |
				  PAD_CTL_100K_PU | PAD_CTL_ODE_OPENDRAIN_NONE |
				  PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
		gpio_request(IOMUX_TO_GPIO(MX51_PIN_EIM_D21), "eim_d21");
		gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_EIM_D21), 0);
		gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_EIM_D21), 1);

		/* hphone_det_b */
		mxc_request_iomux(MX51_PIN_NANDF_D14, IOMUX_CONFIG_ALT3);
		mxc_iomux_set_pad(MX51_PIN_NANDF_D14, PAD_CTL_100K_PU);
		gpio_request(IOMUX_TO_GPIO(MX51_PIN_NANDF_D14), "nandf_d14");
		gpio_direction_input(IOMUX_TO_GPIO(MX51_PIN_NANDF_D14));

		/* audio_clk_en_b */
		mxc_request_iomux(MX51_PIN_CSPI1_RDY, IOMUX_CONFIG_ALT3);
		mxc_iomux_set_pad(MX51_PIN_CSPI1_RDY, PAD_CTL_DRV_HIGH |
				  PAD_CTL_HYS_NONE | PAD_CTL_PUE_KEEPER |
				  PAD_CTL_100K_PU | PAD_CTL_ODE_OPENDRAIN_NONE |
				  PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
		gpio_request(IOMUX_TO_GPIO(MX51_PIN_CSPI1_RDY), "cspi1_rdy");
		gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_CSPI1_RDY), 0);
		gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_CSPI1_RDY), 0);

		/* power key */
		mxc_request_iomux(MX51_PIN_EIM_A27, IOMUX_CONFIG_ALT1);
		mxc_iomux_set_pad(MX51_PIN_EIM_A27, PAD_CTL_SRE_FAST |
				  PAD_CTL_ODE_OPENDRAIN_NONE |
				  PAD_CTL_DRV_HIGH | PAD_CTL_100K_PU |
				  PAD_CTL_HYS_NONE);
		gpio_request(IOMUX_TO_GPIO(MX51_PIN_EIM_A27), "eim_a27");
		gpio_direction_input(IOMUX_TO_GPIO(MX51_PIN_EIM_A27));
	}

	if (cpu_is_mx51_rev(CHIP_REV_3_0) > 0) {
		/* DVI_I2C_ENB = 0 tristates the DVI I2C level shifter */
		mxc_request_iomux(MX51_PIN_CSI2_HSYNC, IOMUX_CONFIG_ALT3);
		mxc_iomux_set_pad(MX51_PIN_CSI2_HSYNC, PAD_CTL_DRV_HIGH |
				  PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
		gpio_request(IOMUX_TO_GPIO(MX51_PIN_CSI2_HSYNC), "csi2_hsync");
		gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_CSI2_HSYNC), 0);
		gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_CSI2_HSYNC), 0);
		/* TO3 doesn't need pad to drive CSI_DATA_EN[0] high */
		mxc_request_iomux(MX51_PIN_DI_GP3, IOMUX_CONFIG_ALT0);
	}

	/* Deassert VGA reset to free i2c bus */
	gpio_request(IOMUX_TO_GPIO(MX51_PIN_EIM_A19), "eim_a19");
	gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_EIM_A19), 0);
	gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_EIM_A19), 1);

	/* LCD related gpio */
	gpio_request(IOMUX_TO_GPIO(MX51_PIN_DI1_D1_CS), "di1_d1_cs");
	gpio_request(IOMUX_TO_GPIO(MX51_PIN_DI1_D0_CS), "di1_d0_cs");
	gpio_request(IOMUX_TO_GPIO(MX51_PIN_CSI2_D12), "csi2_d12");
	gpio_request(IOMUX_TO_GPIO(MX51_PIN_CSI2_D13), "csi2_d13");
	gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_DI1_D1_CS), 0);
	gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_DI1_D0_CS), 0);
	gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_CSI2_D12), 0);
	gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_CSI2_D13), 0);

	/* Camera reset */
	gpio_request(IOMUX_TO_GPIO(MX51_PIN_EIM_D23), "eim_d23");
	gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_EIM_D23), 0);
	gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_EIM_D23), 1);

	/* Camera low power */
	gpio_request(IOMUX_TO_GPIO(MX51_PIN_CSI2_D19), "csi2_d19");
	gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_CSI2_D19), 0);
	gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_CSI2_D19), 0);

	/* OSC_EN */
	gpio_request(IOMUX_TO_GPIO(MX51_PIN_EIM_D18), "eim_d18");
	gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_EIM_D18), 0);
	gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_EIM_D18), 1);

	if (enable_w1) {
		/* OneWire */
		mxc_request_iomux(MX51_PIN_OWIRE_LINE, IOMUX_CONFIG_ALT0);
		mxc_iomux_set_pad(MX51_PIN_OWIRE_LINE, PAD_CTL_HYS_ENABLE |
				PAD_CTL_PKE_ENABLE |
				PAD_CTL_ODE_OPENDRAIN_ENABLE |
				PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST |
				PAD_CTL_100K_PU | PAD_CTL_PUE_PULL);
	} else {
		/* SPDIF Out */
		mxc_request_iomux(MX51_PIN_OWIRE_LINE, IOMUX_CONFIG_ALT6);
		mxc_iomux_set_pad(MX51_PIN_OWIRE_LINE, PAD_CTL_DRV_HIGH |
				PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_PULL |
				PAD_CTL_100K_PU | PAD_CTL_SRE_FAST);
	}
}
예제 #20
0
void gpio_activate_esai_ports(void)
{
	unsigned int pad_val;

	/* ESAI1-HCKR */
	mxc_request_iomux(MX53_PIN_FEC_RX_ER, IOMUX_CONFIG_ALT2);
	/* ESAI1-SCKR */
	mxc_request_iomux(MX53_PIN_FEC_MDIO, IOMUX_CONFIG_ALT2);
	/* ESAI1-FSR */
	mxc_request_iomux(MX53_PIN_FEC_REF_CLK, IOMUX_CONFIG_ALT2);
	/* ESAI1-HCKT */
	mxc_request_iomux(MX53_PIN_FEC_RXD0, IOMUX_CONFIG_ALT2);
	/* ESAI1-SCKT */
	mxc_request_iomux(MX53_PIN_FEC_CRS_DV, IOMUX_CONFIG_ALT2);
	/* ESAI1-FST */
	mxc_request_iomux(MX53_PIN_FEC_RXD1, IOMUX_CONFIG_ALT2);
	/* ESAI1-TX5-RX0 */
	mxc_request_iomux(MX53_PIN_FEC_MDC, IOMUX_CONFIG_ALT2);
	/* ESAI1-TX4-RX1 */
	mxc_request_iomux(MX53_PIN_FEC_TXD0, IOMUX_CONFIG_ALT2);
	/* ESAI1-TX3-RX2 */
	mxc_request_iomux(MX53_PIN_FEC_TX_EN, IOMUX_CONFIG_ALT2);
	/* ESAI1-TX2-RX3 */
	mxc_request_iomux(MX53_PIN_FEC_TXD1, IOMUX_CONFIG_ALT2);
	/* ESAI1-TX1 */
	mxc_request_iomux(MX53_PIN_NANDF_CS3, IOMUX_CONFIG_ALT3);
	/* ESAI1-TX0 */
	mxc_request_iomux(MX53_PIN_NANDF_CS2, IOMUX_CONFIG_ALT3);

	pad_val = PAD_CTL_DRV_HIGH | PAD_CTL_HYS_ENABLE |
		    PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_PULL |
		    PAD_CTL_100K_PU | PAD_CTL_ODE_OPENDRAIN_NONE;

	/* ESAI1-HCKR */
	mxc_iomux_set_pad(MX53_PIN_FEC_RX_ER, pad_val);
	/* ESAI1-SCKR */
	mxc_iomux_set_pad(MX53_PIN_FEC_MDIO, pad_val);
	/* ESAI1-FSR */
	mxc_iomux_set_pad(MX53_PIN_FEC_REF_CLK, pad_val);
	/* ESAI1-HCKT */
	mxc_iomux_set_pad(MX53_PIN_FEC_RXD0, pad_val);
	/* ESAI1-SCKT */
	mxc_iomux_set_pad(MX53_PIN_FEC_CRS_DV, pad_val);
	/* ESAI1-FST */
	mxc_iomux_set_pad(MX53_PIN_FEC_RXD1, pad_val);
	/* ESAI1-TX5-RX0 */
	mxc_iomux_set_pad(MX53_PIN_FEC_MDC, pad_val);
	/* ESAI1-TX4-RX1 */
	mxc_iomux_set_pad(MX53_PIN_FEC_TXD0, pad_val);
	/* ESAI1-TX3-RX2 */
	mxc_iomux_set_pad(MX53_PIN_FEC_TX_EN, pad_val);
	/* ESAI1-TX2-RX3 */
	mxc_iomux_set_pad(MX53_PIN_FEC_TXD1, pad_val);
	/* ESAI1-TX1 */
	mxc_iomux_set_pad(MX53_PIN_NANDF_CS3, pad_val);
	/* ESAI1-TX0 */
	mxc_iomux_set_pad(MX53_PIN_NANDF_CS2, pad_val);

	/* ESAI1-HCKR */
	mxc_iomux_set_input(MUX_IN_ESAI1_IPP_IND_HCKR_SELECT_INPUT,
		INPUT_CTL_PATH0);
	/* ESAI1-SCKR */
	mxc_iomux_set_input(MUX_IN_ESAI1_IPP_IND_SCKR_SELECT_INPUT,
		INPUT_CTL_PATH0);
	/* ESAI1-FSR */
	mxc_iomux_set_input(MUX_IN_ESAI1_IPP_IND_FSR_SELECT_INPUT,
		INPUT_CTL_PATH0);
	/* ESAI1-HCKT */
	mxc_iomux_set_input(MUX_IN_ESAI1_IPP_IND_HCKT_SELECT_INPUT,
		INPUT_CTL_PATH0);
	/* ESAI1-SCKT */
	mxc_iomux_set_input(MUX_IN_ESAI1_IPP_IND_SCKT_SELECT_INPUT,
		INPUT_CTL_PATH0);
	/* ESAI1-FST */
	mxc_iomux_set_input(MUX_IN_ESAI1_IPP_IND_FST_SELECT_INPUT,
		INPUT_CTL_PATH0);
	/* ESAI1-TX5-RX0 */
	mxc_iomux_set_input(MUX_IN_ESAI1_IPP_IND_SDO5_SDI0_SELECT_INPUT,
		INPUT_CTL_PATH0);
	/* ESAI1-TX4-RX1 */
	mxc_iomux_set_input(MUX_IN_ESAI1_IPP_IND_SDO4_SDI1_SELECT_INPUT,
		INPUT_CTL_PATH0);
	/* ESAI1-TX3-RX2 */
	mxc_iomux_set_input(MUX_IN_ESAI1_IPP_IND_SDO3_SDI2_SELECT_INPUT,
		INPUT_CTL_PATH0);
	/* ESAI1-TX2-RX3 */
	mxc_iomux_set_input(MUX_IN_ESAI1_IPP_IND_SDO2_SDI3_SELECT_INPUT,
		INPUT_CTL_PATH0);
	/* ESAI1-TX1 */
	mxc_iomux_set_input(MUX_IN_ESAI1_IPP_IND_SDO1_SELECT_INPUT,
		INPUT_CTL_PATH0);
	/* ESAI1-TX0 */
	mxc_iomux_set_input(MUX_IN_ESAI1_IPP_IND_SDO0_SELECT_INPUT,
		INPUT_CTL_PATH0);

}
예제 #21
0
void __init mx53_evk_io_init(void)
{
	int i;

	for (i = 0; i < ARRAY_SIZE(mxc_iomux_pins); i++) {
		mxc_request_iomux(mxc_iomux_pins[i].pin,
				  mxc_iomux_pins[i].mux_mode);
		if (mxc_iomux_pins[i].pad_cfg)
			mxc_iomux_set_pad(mxc_iomux_pins[i].pin,
					  mxc_iomux_pins[i].pad_cfg);
		if (mxc_iomux_pins[i].in_select)
			mxc_iomux_set_input(mxc_iomux_pins[i].in_select,
					    mxc_iomux_pins[i].in_mode);
	}

	if (board_is_mx53_arm2()) {
		/* MX53 ARM2 CPU board */
		pr_info("MX53 ARM2 board \n");
		for (i = 0; i < ARRAY_SIZE(mx53_arm2_iomux_pins); i++) {
			mxc_request_iomux(mx53_arm2_iomux_pins[i].pin,
					  mx53_arm2_iomux_pins[i].mux_mode);
			if (mx53_arm2_iomux_pins[i].pad_cfg)
				mxc_iomux_set_pad(mx53_arm2_iomux_pins[i].pin,
						  mx53_arm2_iomux_pins[i].pad_cfg);
			if (mx53_arm2_iomux_pins[i].in_select)
				mxc_iomux_set_input(mx53_arm2_iomux_pins[i].in_select,
						    mx53_arm2_iomux_pins[i].in_mode);
		}

		/* Enable OTG VBus with GPIO low */
		mxc_iomux_set_pad(MX53_PIN_EIM_D22, PAD_CTL_DRV_HIGH |
				PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
		gpio_request(IOMUX_TO_GPIO(MX53_PIN_EIM_D22), "gpio3_22");
		gpio_direction_output(IOMUX_TO_GPIO(MX53_PIN_EIM_D22), 0);
		gpio_set_value(IOMUX_TO_GPIO(MX53_PIN_EIM_D22), 0);

		gpio_request(IOMUX_TO_GPIO(MX53_PIN_GPIO_1), "gpio1_1");
		gpio_direction_input(IOMUX_TO_GPIO(MX53_PIN_GPIO_1));	/* SD1 CD */

		gpio_request(IOMUX_TO_GPIO(MX53_PIN_DI0_PIN4), "gpio4_20");
		gpio_direction_output(IOMUX_TO_GPIO(MX53_PIN_DI0_PIN4), 0);
		gpio_set_value(IOMUX_TO_GPIO(MX53_PIN_DI0_PIN4), 1);
	} else {
		/* MX53 EVK board */
		pr_info("MX53 EVK board \n");
			for (i = 0; i < ARRAY_SIZE(mx53_evk_iomux_pins); i++) {
			mxc_request_iomux(mx53_evk_iomux_pins[i].pin,
					  mx53_evk_iomux_pins[i].mux_mode);
			if (mx53_evk_iomux_pins[i].pad_cfg)
				mxc_iomux_set_pad(mx53_evk_iomux_pins[i].pin,
						  mx53_evk_iomux_pins[i].pad_cfg);
			if (mx53_evk_iomux_pins[i].in_select)
				mxc_iomux_set_input(mx53_evk_iomux_pins[i].in_select,
						    mx53_evk_iomux_pins[i].in_mode);
		}
		/* Host1 Vbus with GPIO high */
		mxc_iomux_set_pad(MX53_PIN_ATA_DA_2, PAD_CTL_DRV_HIGH |
				PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
		gpio_request(IOMUX_TO_GPIO(MX53_PIN_ATA_DA_2), "gpio7_8");
		gpio_direction_output(IOMUX_TO_GPIO(MX53_PIN_ATA_DA_2), 1);

		/* USB HUB RESET - De-assert USB HUB RESET_N */
		mxc_iomux_set_pad(MX53_PIN_CSI0_DATA_EN, PAD_CTL_DRV_HIGH |
				  PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
		gpio_request(IOMUX_TO_GPIO(MX53_PIN_CSI0_DATA_EN), "gpio5_20");
		gpio_direction_output(IOMUX_TO_GPIO(MX53_PIN_CSI0_DATA_EN), 0);

		msleep(1);
		gpio_set_value(IOMUX_TO_GPIO(MX53_PIN_CSI0_DATA_EN), 0);
		msleep(1);
		gpio_set_value(IOMUX_TO_GPIO(MX53_PIN_CSI0_DATA_EN), 1);

		/* Enable OTG VBus with GPIO low */
		mxc_iomux_set_pad(MX53_PIN_EIM_A23, PAD_CTL_DRV_HIGH |
				PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
		gpio_request(IOMUX_TO_GPIO(MX53_PIN_EIM_A23), "gpio6_6");
		gpio_direction_output(IOMUX_TO_GPIO(MX53_PIN_EIM_A23), 0);
		gpio_set_value(IOMUX_TO_GPIO(MX53_PIN_EIM_A23), 0);

		gpio_request(IOMUX_TO_GPIO(MX53_PIN_EIM_DA13), "gpio3_13");
		gpio_direction_input(IOMUX_TO_GPIO(MX53_PIN_EIM_DA13));	/* SD1 CD */
		gpio_request(IOMUX_TO_GPIO(MX53_PIN_EIM_DA14), "gpio3_14");
		gpio_direction_input(IOMUX_TO_GPIO(MX53_PIN_EIM_DA14));	/* SD1 WP */

		/* SD3 CD */
		gpio_request(IOMUX_TO_GPIO(MX53_PIN_EIM_DA11), "gpio3_11");
		gpio_direction_input(IOMUX_TO_GPIO(MX53_PIN_EIM_DA11));

		/* SD3 WP */
		gpio_request(IOMUX_TO_GPIO(MX53_PIN_EIM_DA12), "gpio3_12");
		gpio_direction_input(IOMUX_TO_GPIO(MX53_PIN_EIM_DA11));

		/* reset FEC PHY */
		gpio_request(IOMUX_TO_GPIO(MX53_PIN_ATA_DA_0), "gpio7_6");
		gpio_direction_output(IOMUX_TO_GPIO(MX53_PIN_ATA_DA_0), 0);
		gpio_set_value(IOMUX_TO_GPIO(MX53_PIN_ATA_DA_0), 0);
		msleep(1);
		gpio_set_value(IOMUX_TO_GPIO(MX53_PIN_ATA_DA_0), 1);

	}

	/* DVI Detect */
	gpio_request(IOMUX_TO_GPIO(MX53_PIN_EIM_D31), "gpio3_31");
	gpio_direction_input(IOMUX_TO_GPIO(MX53_PIN_EIM_D31));
	/* DVI Reset - Assert for i2c disabled mode */
	gpio_request(IOMUX_TO_GPIO(MX53_PIN_EIM_WAIT), "gpio5_0");
	gpio_set_value(IOMUX_TO_GPIO(MX53_PIN_EIM_WAIT), 0);
	gpio_direction_output(IOMUX_TO_GPIO(MX53_PIN_EIM_WAIT), 0);
	/* DVI Power-down */
	gpio_request(IOMUX_TO_GPIO(MX53_PIN_EIM_D24), "gpio3_24");
	gpio_direction_output(IOMUX_TO_GPIO(MX53_PIN_EIM_D24), 0);
	gpio_set_value(IOMUX_TO_GPIO(MX53_PIN_EIM_D24), 1);
	/* DVI I2C enable */
	gpio_request(IOMUX_TO_GPIO(MX53_PIN_EIM_D28), "gpio3_28");
	gpio_direction_output(IOMUX_TO_GPIO(MX53_PIN_EIM_D28), 0);
	gpio_set_value(IOMUX_TO_GPIO(MX53_PIN_EIM_D28), 0);

	for (i = 0; i <  ARRAY_SIZE(nand_iomux_pins); i++) {
		mxc_request_iomux(nand_iomux_pins[i].pin,
					nand_iomux_pins[i].mux_mode);
		if (nand_iomux_pins[i].pad_cfg)
			mxc_iomux_set_pad(nand_iomux_pins[i].pin,
					nand_iomux_pins[i].pad_cfg);
		if (nand_iomux_pins[i].in_select)
			mxc_iomux_set_input(nand_iomux_pins[i].in_select,
					nand_iomux_pins[i].in_mode);
	}

	gpio_request(IOMUX_TO_GPIO(MX53_PIN_GPIO_16), "gpio7_11");
	gpio_direction_input(IOMUX_TO_GPIO(MX53_PIN_GPIO_16));	/*PMIC_INT*/

	/* headphone_det_b */
	mxc_request_iomux(MX53_PIN_ATA_DATA5, IOMUX_CONFIG_GPIO);
	mxc_iomux_set_pad(MX53_PIN_ATA_DATA5, PAD_CTL_100K_PU);
	gpio_request(IOMUX_TO_GPIO(MX53_PIN_ATA_DATA5), "gpio2_5");
	gpio_direction_input(IOMUX_TO_GPIO(MX53_PIN_ATA_DATA5));

	/* power key */

	/* LCD related gpio */

	/* Camera reset */
	gpio_request(IOMUX_TO_GPIO(MX53_PIN_GPIO_10), "gpio4_0");
	gpio_direction_output(IOMUX_TO_GPIO(MX53_PIN_GPIO_10), 0);
	gpio_set_value(IOMUX_TO_GPIO(MX53_PIN_GPIO_10), 1);

	/* Camera low power */
	gpio_request(IOMUX_TO_GPIO(MX53_PIN_CSI0_D5), "gpio5_23");
	gpio_direction_output(IOMUX_TO_GPIO(MX53_PIN_CSI0_D5), 0);
	gpio_set_value(IOMUX_TO_GPIO(MX53_PIN_CSI0_D5), 0);

	/* CAN1 enable GPIO*/
	gpio_direction_output(IOMUX_TO_GPIO(MX53_PIN_GPIO_18), 0);
	gpio_set_value(IOMUX_TO_GPIO(MX53_PIN_GPIO_18), 0);
	gpio_direction_output(IOMUX_TO_GPIO(MX53_PIN_GPIO_17), 0);
	gpio_set_value(IOMUX_TO_GPIO(MX53_PIN_GPIO_17), 0);

	/* CAN2 enable GPIO*/
	gpio_direction_output(IOMUX_TO_GPIO(MX53_PIN_CSI0_D6), 0);
	gpio_set_value(IOMUX_TO_GPIO(MX53_PIN_CSI0_D6), 0);
	gpio_direction_output(IOMUX_TO_GPIO(MX53_PIN_GPIO_14), 0);
	gpio_set_value(IOMUX_TO_GPIO(MX53_PIN_GPIO_14), 0);

	/* GPIO for 12V */
	gpio_direction_output(IOMUX_TO_GPIO(MX53_PIN_GPIO_19), 0);
	gpio_set_value(IOMUX_TO_GPIO(MX53_PIN_GPIO_19), 0);

}
예제 #22
0
void __init mx50_yoshime_io_init(void)
{
	int i;

	for (i = 0; i < ARRAY_SIZE(mxc_iomux_pins); i++) {
		mxc_request_iomux(mxc_iomux_pins[i].pin,
		                  mxc_iomux_pins[i].mux_mode);
		if (mxc_iomux_pins[i].pad_cfg)
		        mxc_iomux_set_pad(mxc_iomux_pins[i].pin,
		                          mxc_iomux_pins[i].pad_cfg);
		if (mxc_iomux_pins[i].in_select)
		        mxc_iomux_set_input(mxc_iomux_pins[i].in_select,
		                            mxc_iomux_pins[i].in_mode);
	}

	/* SD4 CD */
	gpio_request(IOMUX_TO_GPIO(MX50_PIN_DISP_D15), "sd4_cd");
	gpio_direction_input(IOMUX_TO_GPIO(MX50_PIN_DISP_D15));

	/* SD4 WP */
	gpio_request(IOMUX_TO_GPIO(MX50_PIN_DISP_D14), "sd4_wp");
	gpio_direction_input(IOMUX_TO_GPIO(MX50_PIN_DISP_D14));

	/* PMIC Interrupt */
	gpio_request(IOMUX_TO_GPIO(MX50_PIN_UART1_CTS), "pmic_int");
	gpio_direction_input(IOMUX_TO_GPIO(MX50_PIN_UART1_CTS));

	/* WiFi Power */
	gpio_request(IOMUX_TO_GPIO(MX50_PIN_SD3_WP), "sd3_wp");
	gpio_direction_output(IOMUX_TO_GPIO(MX50_PIN_SD3_WP), 0);
	gpio_set_value(IOMUX_TO_GPIO(MX50_PIN_SD3_WP), 1);	

	/* WiFi spec, add delay */
	mdelay(40);

	gpio_request(IOMUX_TO_GPIO(MX50_PIN_SSI_RXC), "gp5_6");
	gpio_direction_output(IOMUX_TO_GPIO(MX50_PIN_SSI_RXC), 0);
	gpio_set_value(IOMUX_TO_GPIO(MX50_PIN_SSI_RXC), 1);
	
	/*hall sensor*/
	gpio_request(IOMUX_TO_GPIO(MX50_PIN_SD2_WP), "hall");
	gpio_direction_input(IOMUX_TO_GPIO(MX50_PIN_SD2_WP));
		
	/*Front light*/
	gpio_request(IOMUX_TO_GPIO(MX50_PIN_PWM1), "fl_cntrl");
	gpio_direction_output(IOMUX_TO_GPIO(MX50_PIN_PWM1), 0);	

	/* Wait 5ms before powering on Papyrus */
	mdelay(5);

#ifdef CONFIG_SND_MXC_SOC
	mxc_request_iomux(MX50_PIN_SSI_TXC, IOMUX_CONFIG_ALT0);
	mxc_iomux_set_pad(MX50_PIN_SSI_TXC, PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
					PAD_CTL_DRV_HIGH | PAD_CTL_ODE_OPENDRAIN_NONE);

	mx50_audio_clock_enable(1);
#endif
	gpio_request(IOMUX_TO_GPIO(MX50_PIN_EPDC_VCOM0), "epdc_vcom");
	gpio_direction_output(IOMUX_TO_GPIO(MX50_PIN_EPDC_VCOM0), 0);

	gpio_request(IOMUX_TO_GPIO(MX50_PIN_EPDC_PWRSTAT), "epdc_pwrstat");
	gpio_direction_input(IOMUX_TO_GPIO(MX50_PIN_EPDC_PWRSTAT));

	gpio_request(IOMUX_TO_GPIO(MX50_PIN_EPDC_PWRCOM), "epdc_pwrcom");
	gpio_direction_input(IOMUX_TO_GPIO(MX50_PIN_EPDC_PWRCOM));

	gpio_request(IOMUX_TO_GPIO(MX50_PIN_EPDC_PWRCTRL0), "epdc_pwrctrl0");
	gpio_direction_output(IOMUX_TO_GPIO(MX50_PIN_EPDC_PWRCTRL0), 0);
	gpio_set_value(IOMUX_TO_GPIO(MX50_PIN_EPDC_PWRCTRL0), 1);

	gpio_request(IOMUX_TO_GPIO(MX50_PIN_EPDC_PWRCTRL1), "epdc_pwrctrl1");
	gpio_direction_input(IOMUX_TO_GPIO(MX50_PIN_EPDC_PWRCTRL1));

#ifdef CONFIG_SND_MXC_SOC
	gpio_request(IOMUX_TO_GPIO(MX50_PIN_EIM_DA4), "eim_da4");
	gpio_direction_input(IOMUX_TO_GPIO(MX50_PIN_EIM_DA4));
#endif

	gpio_request(IOMUX_TO_GPIO(MX50_PIN_OWIRE), "owire");
	gpio_direction_input(IOMUX_TO_GPIO(MX50_PIN_OWIRE));

	/* WAN Power */
	gpio_direction_output(IOMUX_TO_GPIO(MX50_PIN_EIM_RW), 0);
	gpio_set_value(IOMUX_TO_GPIO(MX50_PIN_EIM_RW), 0);

	/* WAN USB */
	gpio_direction_output(IOMUX_TO_GPIO(MX50_PIN_DISP_RD), 0);
	gpio_set_value(IOMUX_TO_GPIO(MX50_PIN_DISP_RD), 0);

	/* WAN RF */
	gpio_direction_output(IOMUX_TO_GPIO(MX50_PIN_EIM_DA10), 0);
	gpio_set_value(IOMUX_TO_GPIO(MX50_PIN_EIM_DA10), 0);

	/* WAN HMI Host->Modem IRQ */
	gpio_direction_output(IOMUX_TO_GPIO(MX50_PIN_EIM_DA9), 0);

	/* WAN MHI : Modem->Host IRQ */
	gpio_direction_input(IOMUX_TO_GPIO(MX50_PIN_EIM_DA8));	

	/* WAN FW Ready */
	gpio_direction_input(IOMUX_TO_GPIO(MX50_PIN_EIM_DA6));

	/* EIM_DA10 and EIM_DA11 */
	gpio_direction_output(IOMUX_TO_GPIO(MX50_PIN_EIM_DA11), 0);
	gpio_set_value(IOMUX_TO_GPIO(MX50_PIN_EIM_DA11), 0);

	gpio_direction_output(IOMUX_TO_GPIO(MX50_PIN_EIM_DA12), 0);
	gpio_set_value(IOMUX_TO_GPIO(MX50_PIN_EIM_DA12), 0);

	/* Proximity */
	gpio_direction_input(IOMUX_TO_GPIO(MX50_PIN_DISP_D0));

	gpio_direction_input(IOMUX_TO_GPIO(MX50_PIN_EIM_DA0));

	/* Proximity Reset */
	gpio_direction_output(IOMUX_TO_GPIO(MX50_PIN_DISP_D7), 0);

	/* Accelerometer IRQ2 moved after Whitney protos */
	gpio_request(IOMUX_TO_GPIO(MX50_PIN_SD1_D2), "sd1_d2");
	gpio_direction_input(IOMUX_TO_GPIO(MX50_PIN_SD1_D2));

	gpio_request(IOMUX_TO_GPIO(MX50_PIN_SD1_D3), "sd1_d3");
	gpio_direction_input(IOMUX_TO_GPIO(MX50_PIN_SD1_D3));

	if (mx50_board_is(BOARD_ID_WHITNEY) || 
		mx50_board_is(BOARD_ID_WHITNEY_WFO) )  {
		printk("Configure EMI_CS1 for whitney \n");

		mxc_request_iomux(MX50_PIN_EIM_CS1, IOMUX_CONFIG_GPIO);
		gpio_direction_input(IOMUX_TO_GPIO(MX50_PIN_EIM_CS1));
		mxc_iomux_set_pad(MX50_PIN_EIM_CS1, PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_PULL |
					PAD_CTL_ODE_OPENDRAIN_NONE | PAD_CTL_DRV_HIGH |
					PAD_CTL_100K_PD);
	}

	/* EPDC */
	gpio_request(IOMUX_TO_GPIO(MX50_PIN_EPDC_SDCE0), "epdc_sdce0");	
	gpio_direction_output(IOMUX_TO_GPIO(MX50_PIN_EPDC_SDCE0), 0);

	gpio_request(IOMUX_TO_GPIO(MX50_PIN_EPDC_GDSP), "epdc_gdsp");
	gpio_direction_output(IOMUX_TO_GPIO(MX50_PIN_EPDC_GDSP), 0);

	/* Accessory charging */
	gpio_direction_input(IOMUX_TO_GPIO(MX50_PIN_EIM_DA13));

	/* UART4 is not needed on !FINKLE */
	if (!mx50_board_is(BOARD_ID_FINKLE_EVT1)) {
		mxc_free_iomux(MX50_PIN_UART4_TXD, IOMUX_CONFIG_ALT0);
		mxc_request_iomux(MX50_PIN_UART4_TXD, IOMUX_CONFIG_ALT1);
		gpio_request(IOMUX_TO_GPIO(MX50_PIN_UART4_TXD), "uart4_txd");
		gpio_direction_output(IOMUX_TO_GPIO(MX50_PIN_UART4_TXD), 0);
		gpio_set_value(IOMUX_TO_GPIO(MX50_PIN_UART4_TXD), 0);
	}

#ifndef CONFIG_MX50_YOSHI_SDCARD
	gpio_direction_input(IOMUX_TO_GPIO(MX50_PIN_DISP_D8));
	gpio_direction_input(IOMUX_TO_GPIO(MX50_PIN_DISP_D9));
	gpio_direction_input(IOMUX_TO_GPIO(MX50_PIN_DISP_D10));
	gpio_direction_input(IOMUX_TO_GPIO(MX50_PIN_DISP_D11));
	gpio_direction_input(IOMUX_TO_GPIO(MX50_PIN_DISP_D12));
	gpio_direction_input(IOMUX_TO_GPIO(MX50_PIN_DISP_D13));
	gpio_direction_input(IOMUX_TO_GPIO(MX50_PIN_DISP_D14));
	gpio_direction_input(IOMUX_TO_GPIO(MX50_PIN_DISP_D15));
#endif

	/* NAND family - 1.8V */
	__raw_writel(0x2000, IO_ADDRESS(IOMUXC_BASE_ADDR) + 0x06c0);

	__raw_writel(0x2000, IO_ADDRESS(IOMUXC_BASE_ADDR) + 0x069c);
}
void __init mx51_babbage_io_init(void)
{
	int i;

	/* Work-around For external USB HUB chip to use default configuration
	   by reseting hub with i2c lines pulled low */
	mxc_request_iomux(MX51_PIN_GPIO1_7, IOMUX_CONFIG_GPIO);
	mxc_iomux_set_pad(MX51_PIN_GPIO1_7, PAD_CTL_DRV_HIGH |
			  PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
	mxc_set_gpio_direction(MX51_PIN_GPIO1_7, 0);

	if (cpu_is_mx51_rev(CHIP_REV_1_1) == 1) {
		/* Drive I2C1 SDA line low */
		mxc_request_iomux(MX51_PIN_GPIO1_3, IOMUX_CONFIG_ALT0);
		mxc_iomux_set_pad(MX51_PIN_GPIO1_3, PAD_CTL_DRV_HIGH |
				  PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
		mxc_set_gpio_direction(MX51_PIN_GPIO1_3, 0);
		mxc_set_gpio_dataout(MX51_PIN_GPIO1_3, 0);

		/* Drive I2C1 SCL line low */
		mxc_request_iomux(MX51_PIN_GPIO1_2, IOMUX_CONFIG_ALT0);
		mxc_iomux_set_pad(MX51_PIN_GPIO1_2, PAD_CTL_DRV_HIGH |
				  PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
		mxc_set_gpio_direction(MX51_PIN_GPIO1_2, 0);
		mxc_set_gpio_dataout(MX51_PIN_GPIO1_2, 0);

		msleep(5);
		mxc_free_iomux(MX51_PIN_GPIO1_2, IOMUX_CONFIG_ALT2);
		mxc_free_iomux(MX51_PIN_GPIO1_3, IOMUX_CONFIG_ALT2);
	}

	/* USB HUB RESET - De-assert USB HUB RESET_N */
	msleep(1);
	mxc_set_gpio_dataout(MX51_PIN_GPIO1_7, 0);
	msleep(1);
	mxc_set_gpio_dataout(MX51_PIN_GPIO1_7, 1);

	for (i = 0; i < ARRAY_SIZE(mxc_iomux_pins); i++) {
		mxc_request_iomux(mxc_iomux_pins[i].pin,
				  mxc_iomux_pins[i].mux_mode);
		if (mxc_iomux_pins[i].pad_cfg)
			mxc_iomux_set_pad(mxc_iomux_pins[i].pin,
					  mxc_iomux_pins[i].pad_cfg);
		if (mxc_iomux_pins[i].in_select)
			mxc_iomux_set_input(mxc_iomux_pins[i].in_select,
					    mxc_iomux_pins[i].in_mode);
	}

	mxc_set_gpio_direction(MX51_PIN_GPIO1_8, 1);
	mxc_set_gpio_direction(MX51_PIN_GPIO1_0, 1);	/* SD1 CD */
	mxc_set_gpio_direction(MX51_PIN_GPIO1_1, 1);	/* SD1 WP */
	if (board_is_babbage_2_5() == 1)
		/* BB2.5 */
		mxc_set_gpio_direction(MX51_PIN_GPIO1_6, 1);	/* SD2 CD */
	else
		/* BB2.0 */
		mxc_set_gpio_direction(MX51_PIN_GPIO1_4, 1);	/* SD2 CD */
	mxc_set_gpio_direction(MX51_PIN_GPIO1_5, 1);	/* SD2 WP */

	/* reset FEC PHY */
	mxc_set_gpio_direction(MX51_PIN_EIM_A20, 0);
	mxc_set_gpio_dataout(MX51_PIN_EIM_A20, 0);
	msleep(10);
	mxc_set_gpio_dataout(MX51_PIN_EIM_A20, 1);

	/* reset FM */
	mxc_set_gpio_dataout(MX51_PIN_EIM_A21, 0);
	mxc_set_gpio_direction(MX51_PIN_EIM_A21, 0);
	msleep(10);
	mxc_set_gpio_dataout(MX51_PIN_EIM_A21, 1);

	if (cpu_is_mx51_rev(CHIP_REV_1_1) == 1) {
		/* MX51_PIN_EIM_CRE - De-assert USB PHY RESETB */
		mxc_set_gpio_direction(MX51_PIN_EIM_CRE, 0);
		mxc_set_gpio_dataout(MX51_PIN_EIM_CRE, 1);

		/* hphone_det_b */
		mxc_set_gpio_direction(MX51_PIN_NANDF_CS0, 1);
	} else {
		mxc_free_iomux(MX51_PIN_EIM_D21, IOMUX_CONFIG_ALT2);
		mxc_free_iomux(MX51_PIN_EIM_A24, IOMUX_CONFIG_ALT2);
		mxc_free_iomux(MX51_PIN_EIM_A25, IOMUX_CONFIG_ALT2);
		mxc_free_iomux(MX51_PIN_EIM_D18, IOMUX_CONFIG_ALT2);
		mxc_free_iomux(MX51_PIN_EIM_D20, IOMUX_CONFIG_ALT2);
		mxc_free_iomux(MX51_PIN_EIM_D21, IOMUX_CONFIG_ALT2);
		mxc_free_iomux(MX51_PIN_EIM_D23, IOMUX_CONFIG_ALT2);
		mxc_free_iomux(MX51_PIN_EIM_D16, IOMUX_CONFIG_ALT2);
		mxc_free_iomux(MX51_PIN_EIM_D17, IOMUX_CONFIG_ALT2);
		mxc_free_iomux(MX51_PIN_EIM_D19, IOMUX_CONFIG_ALT2);
		mxc_free_iomux(MX51_PIN_GPIO1_2, IOMUX_CONFIG_ALT2);
		mxc_free_iomux(MX51_PIN_GPIO1_3, IOMUX_CONFIG_ALT2);
		mxc_free_iomux(MX51_PIN_EIM_LBA, IOMUX_CONFIG_GPIO);
		mxc_free_iomux(MX51_PIN_NANDF_CS0, IOMUX_CONFIG_GPIO);

		/* i2c1 SDA */
		mxc_request_iomux(MX51_PIN_EIM_D16,
				  IOMUX_CONFIG_ALT4 | IOMUX_CONFIG_SION);
		mxc_iomux_set_input(MUX_IN_I2C1_IPP_SDA_IN_SELECT_INPUT,
				    INPUT_CTL_PATH1);
		mxc_iomux_set_pad(MX51_PIN_EIM_D16, PAD_CTL_SRE_FAST |
				  PAD_CTL_ODE_OPENDRAIN_ENABLE |
				  PAD_CTL_DRV_HIGH | PAD_CTL_100K_PU |
				  PAD_CTL_HYS_ENABLE);

		/* i2c1 SCL */
		mxc_request_iomux(MX51_PIN_EIM_D19,
				  IOMUX_CONFIG_ALT4 | IOMUX_CONFIG_SION);
		mxc_iomux_set_input(MUX_IN_I2C1_IPP_SCL_IN_SELECT_INPUT,
				    INPUT_CTL_PATH1);
		mxc_iomux_set_pad(MX51_PIN_EIM_D19, PAD_CTL_SRE_FAST |
				  PAD_CTL_ODE_OPENDRAIN_ENABLE |
				  PAD_CTL_DRV_HIGH | PAD_CTL_100K_PU |
				  PAD_CTL_HYS_ENABLE);

		/* i2c2 SDA */
		mxc_request_iomux(MX51_PIN_KEY_COL5,
				  IOMUX_CONFIG_ALT3 | IOMUX_CONFIG_SION);
		mxc_iomux_set_input(MUX_IN_I2C2_IPP_SDA_IN_SELECT_INPUT,
				    INPUT_CTL_PATH1);
		mxc_iomux_set_pad(MX51_PIN_KEY_COL5,
				  PAD_CTL_SRE_FAST |
				  PAD_CTL_ODE_OPENDRAIN_ENABLE |
				  PAD_CTL_DRV_HIGH | PAD_CTL_100K_PU |
				  PAD_CTL_HYS_ENABLE);

		/* i2c2 SCL */
		mxc_request_iomux(MX51_PIN_KEY_COL4,
				  IOMUX_CONFIG_ALT3 | IOMUX_CONFIG_SION);
		mxc_iomux_set_input(MUX_IN_I2C2_IPP_SCL_IN_SELECT_INPUT,
				    INPUT_CTL_PATH1);
		mxc_iomux_set_pad(MX51_PIN_KEY_COL4,
				  PAD_CTL_SRE_FAST |
				  PAD_CTL_ODE_OPENDRAIN_ENABLE |
				  PAD_CTL_DRV_HIGH | PAD_CTL_100K_PU |
				  PAD_CTL_HYS_ENABLE);

		/* Drive 26M_OSC_EN line high */
		mxc_request_iomux(MX51_PIN_DI1_PIN12, IOMUX_CONFIG_ALT4);
		mxc_iomux_set_pad(MX51_PIN_DI1_PIN12, PAD_CTL_DRV_HIGH |
				  PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
		mxc_set_gpio_direction(MX51_PIN_DI1_PIN12, 0);
		mxc_set_gpio_dataout(MX51_PIN_DI1_PIN12, 1);

		/* Drive USB_CLK_EN_B line low */
		mxc_request_iomux(MX51_PIN_EIM_D17, IOMUX_CONFIG_ALT1);
		mxc_iomux_set_pad(MX51_PIN_EIM_D17, PAD_CTL_DRV_HIGH |
				  PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
		mxc_set_gpio_direction(MX51_PIN_EIM_D17, 0);
		mxc_set_gpio_dataout(MX51_PIN_EIM_D17, 0);

		/* MX51_PIN_EIM_D21 - De-assert USB PHY RESETB */
		mxc_request_iomux(MX51_PIN_EIM_D21, IOMUX_CONFIG_ALT1);
		mxc_iomux_set_pad(MX51_PIN_EIM_D21, PAD_CTL_DRV_HIGH |
				  PAD_CTL_HYS_NONE | PAD_CTL_PUE_KEEPER |
				  PAD_CTL_100K_PU | PAD_CTL_ODE_OPENDRAIN_NONE |
				  PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
		mxc_set_gpio_direction(MX51_PIN_EIM_D21, 0);
		mxc_set_gpio_dataout(MX51_PIN_EIM_D21, 1);

		/* hphone_det_b */
		mxc_request_iomux(MX51_PIN_NANDF_D14, IOMUX_CONFIG_ALT3);
		mxc_iomux_set_pad(MX51_PIN_NANDF_D14, PAD_CTL_100K_PU);
		mxc_set_gpio_direction(MX51_PIN_NANDF_D14, 1);

		/* audio_clk_en_b */
		mxc_request_iomux(MX51_PIN_CSPI1_RDY, IOMUX_CONFIG_ALT3);
		mxc_iomux_set_pad(MX51_PIN_CSPI1_RDY, PAD_CTL_DRV_HIGH |
				  PAD_CTL_HYS_NONE | PAD_CTL_PUE_KEEPER |
				  PAD_CTL_100K_PU | PAD_CTL_ODE_OPENDRAIN_NONE |
				  PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
		mxc_set_gpio_direction(MX51_PIN_CSPI1_RDY, 0);
		mxc_set_gpio_dataout(MX51_PIN_CSPI1_RDY, 0);

		/* power key */
		mxc_request_iomux(MX51_PIN_EIM_A27, IOMUX_CONFIG_ALT1);
		mxc_iomux_set_pad(MX51_PIN_EIM_A27, PAD_CTL_SRE_FAST |
				  PAD_CTL_ODE_OPENDRAIN_NONE |
				  PAD_CTL_DRV_HIGH | PAD_CTL_100K_PU |
				  PAD_CTL_HYS_NONE);
		mxc_set_gpio_direction(MX51_PIN_EIM_A27, 1);
	}

	/* Deassert VGA reset to free i2c bus */
	mxc_set_gpio_direction(MX51_PIN_EIM_A19, 0);
	mxc_set_gpio_dataout(MX51_PIN_EIM_A19, 1);

	/* LCD related gpio */
	mxc_set_gpio_direction(MX51_PIN_DI1_D1_CS, 0);
}
void __init mx51_3stack_io_init(void)
{
	int i, num;
	struct mxc_iomux_pin_cfg *pin_ptr;

	for (i = 0; i < ARRAY_SIZE(mxc_iomux_pins); i++) {
		mxc_request_iomux(mxc_iomux_pins[i].pin,
				  mxc_iomux_pins[i].mux_mode);
		if (mxc_iomux_pins[i].pad_cfg)
			mxc_iomux_set_pad(mxc_iomux_pins[i].pin,
					  mxc_iomux_pins[i].pad_cfg);
		if (mxc_iomux_pins[i].in_select)
			mxc_iomux_set_input(mxc_iomux_pins[i].in_select,
					  mxc_iomux_pins[i].in_mode);
	}

	if (enable_ata) {
		pin_ptr = ata_iomux_pins;
		num = ARRAY_SIZE(ata_iomux_pins);
	} else if (enable_sim) {
		pin_ptr = sim_iomux_pins;
		num = ARRAY_SIZE(sim_iomux_pins);
	} else {
		pin_ptr = nand_iomux_pins;
		num = ARRAY_SIZE(nand_iomux_pins);
	}

	for (i = 0; i < num; i++) {
		mxc_request_iomux(pin_ptr[i].pin, pin_ptr[i].mux_mode);
		if (pin_ptr[i].pad_cfg)
			mxc_iomux_set_pad(pin_ptr[i].pin, pin_ptr[i].pad_cfg);
		if (pin_ptr[i].in_select)
			mxc_iomux_set_input(pin_ptr[i].in_select,
					pin_ptr[i].in_mode);
	}

	/* Camera low power */
	mxc_set_gpio_direction(MX51_PIN_CSI1_D8, 0);
	mxc_set_gpio_dataout(MX51_PIN_CSI1_D8, 0);
	mxc_set_gpio_direction(MX51_PIN_EIM_EB2, 0);    /* TO1 */
	mxc_set_gpio_dataout(MX51_PIN_EIM_EB2, 0);      /* TO1 */

	/* Camera reset */
	mxc_set_gpio_direction(MX51_PIN_CSI1_D9, 0);
	mxc_set_gpio_dataout(MX51_PIN_CSI1_D9, 1);
	mxc_set_gpio_direction(MX51_PIN_DI1_D1_CS, 0);

	mxc_set_gpio_direction(MX51_PIN_GPIO1_0, 1);	/* SD1 CD */
	mxc_set_gpio_direction(MX51_PIN_GPIO1_1, 1);	/* SD1 WP */

	/* EIM_D16 */
	/* osc_en is shared by SPDIF */
	mxc_set_gpio_direction(MX51_PIN_EIM_D16, 0);
	mxc_set_gpio_dataout(MX51_PIN_EIM_D16, 1);

	/* LCD related gpio */
	mxc_set_gpio_direction(MX51_PIN_DI1_D1_CS, 0);
	mxc_set_gpio_direction(MX51_PIN_DISPB2_SER_DIO, 0);
	mxc_set_gpio_dataout(MX51_PIN_DISPB2_SER_DIO, 0);

	/* GPS related gpio */
	mxc_set_gpio_direction(MX51_PIN_EIM_CS2, 0);
	mxc_set_gpio_dataout(MX51_PIN_EIM_CS2, 0);
	mxc_set_gpio_direction(MX51_PIN_EIM_CRE, 0);
	mxc_set_gpio_dataout(MX51_PIN_EIM_CRE, 0);
	mxc_set_gpio_dataout(MX51_PIN_EIM_CRE, 1);
}