void pci_init(void) { struct pci_controller *hose = &pci9054_hose; /* * Register the hose */ hose->first_busno = 0; hose->last_busno = 0xff; /* System memory space */ pci_set_region(hose->regions + 0, 0x00000000, 0x00000000, 0x01000000, PCI_REGION_MEM | PCI_REGION_SYS_MEMORY); /* PCI Memory space */ pci_set_region(hose->regions + 1, 0x00000000, 0xc0000000, 0x10000000, PCI_REGION_MEM); pci_set_ops(hose, pci_hose_read_config_byte_via_dword, pci_hose_read_config_word_via_dword, pci9054_read_config_dword, pci_hose_write_config_byte_via_dword, pci_hose_write_config_word_via_dword, pci9054_write_config_dword); hose->region_count = 2; pci_register_hose(hose); hose->last_busno = pci_hose_scan(hose); }
void pci_init_board(void) { struct pci_controller* hose = (struct pci_controller *)&local_hose; u16 reg16; hose->first_busno = 0; hose->last_busno = 0xff; pci_set_region(hose->regions + 0, CONFIG_SYS_PCI_MEMORY_BUS, CONFIG_SYS_PCI_MEMORY_PHYS, CONFIG_SYS_PCI_MEMORY_SIZE, PCI_REGION_MEM | PCI_REGION_SYS_MEMORY); /* PCI memory space */ pci_set_region(hose->regions + 1, CONFIG_SYS_PCI_MEM_BUS, CONFIG_SYS_PCI_MEM_PHYS, CONFIG_SYS_PCI_MEM_SIZE, PCI_REGION_MEM); /* ISA/PCI memory space */ pci_set_region(hose->regions + 2, CONFIG_SYS_ISA_MEM_BUS, CONFIG_SYS_ISA_MEM_PHYS, CONFIG_SYS_ISA_MEM_SIZE, PCI_REGION_MEM); /* PCI I/O space */ pci_set_region(hose->regions + 3, CONFIG_SYS_PCI_IO_BUS, CONFIG_SYS_PCI_IO_PHYS, CONFIG_SYS_PCI_IO_SIZE, PCI_REGION_IO); /* ISA/PCI I/O space */ pci_set_region(hose->regions + 4, CONFIG_SYS_ISA_IO_BUS, CONFIG_SYS_ISA_IO_PHYS, CONFIG_SYS_ISA_IO_SIZE, PCI_REGION_IO); hose->region_count = 5; pci_setup_indirect(hose, MPC106_REG_ADDR, MPC106_REG_DATA); pci_register_hose(hose); hose->last_busno = pci_hose_scan(hose); /* Initialises the MPC10x PCI Configuration regs. */ pci_read_config_word (PCI_BDF(0,0,0), PCI_COMMAND, ®16); reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; pci_write_config_word(PCI_BDF(0,0,0), PCI_COMMAND, reg16); /* Clear non-reserved bits in status register */ pci_write_config_word(PCI_BDF(0,0,0), PCI_STATUS, 0xffff); }
void board_pci_setup_hose(struct pci_controller *hose) { hose->first_busno = 0; hose->last_busno = 0; /* PCI memory space */ pci_set_region(hose->regions + 0, CONFIG_PCI_MEM_BUS, CONFIG_PCI_MEM_PHYS, CONFIG_PCI_MEM_SIZE, PCI_REGION_MEM); /* PCI IO space */ pci_set_region(hose->regions + 1, CONFIG_PCI_IO_BUS, CONFIG_PCI_IO_PHYS, CONFIG_PCI_IO_SIZE, PCI_REGION_IO); pci_set_region(hose->regions + 2, CONFIG_PCI_PREF_BUS, CONFIG_PCI_PREF_PHYS, CONFIG_PCI_PREF_SIZE, PCI_REGION_PREFETCH); pci_set_region(hose->regions + 3, 0, 0, gd->ram_size, PCI_REGION_MEM | PCI_REGION_SYS_MEMORY); hose->region_count = 4; }
int pci_set_regions(struct pci_controller *hose) { /* System memory space */ pci_set_region(hose->regions + 0, SC520_PCI_MEMORY_BUS, SC520_PCI_MEMORY_PHYS, SC520_PCI_MEMORY_SIZE, PCI_REGION_MEM | PCI_REGION_SYS_MEMORY); /* ISA/PCI memory space */ pci_set_region(hose->regions + 1, SC520_ISA_MEM_BUS, SC520_ISA_MEM_PHYS, SC520_ISA_MEM_SIZE, PCI_REGION_MEM); /* PCI I/O space */ pci_set_region(hose->regions + 2, SC520_PCI_IO_BUS, SC520_PCI_IO_PHYS, SC520_PCI_IO_SIZE, PCI_REGION_IO); /* ISA/PCI I/O space */ pci_set_region(hose->regions + 3, SC520_ISA_IO_BUS, SC520_ISA_IO_PHYS, SC520_ISA_IO_SIZE, PCI_REGION_IO); return 4; }
void pci_init_board(void) { EFI_STATUS status; tnc_hose.first_busno = 0; tnc_hose.last_busno = 0xff; pci_set_region(tnc_hose.regions + 0, 0, 0, gd->ram_size, PCI_REGION_MEM | PCI_REGION_SYS_MEMORY); pci_set_region(tnc_hose.regions + 1, CONFIG_SYS_PCI_MEM_BUS, CONFIG_SYS_PCI_MEM_PHYS, CONFIG_SYS_PCI_MEM_SIZE, PCI_REGION_MEM); pci_set_region(tnc_hose.regions + 2, CONFIG_SYS_PCI_IO_BUS, CONFIG_SYS_PCI_IO_PHYS, CONFIG_SYS_PCI_IO_SIZE, PCI_REGION_IO); tnc_hose.region_count = 3; pci_setup_type1(&tnc_hose); pci_register_hose(&tnc_hose); tnc_hose.last_busno = pci_hose_scan(&tnc_hose); /* call into FspNotify */ printf("Calling into FSP (notify phase EnumInitPhaseAfterPciEnumeration): "); if ((status = FspNotifyWrapper(NULL, EnumInitPhaseAfterPciEnumeration)) != FSP_SUCCESS) printf("fail, error code %x\n", status); else printf("OK\n"); }
static inline void init_pcie1(void) { volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); #ifdef CONFIG_PCIE1 uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19; volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *)CONFIG_SYS_PCIE1_ADDR; struct pci_controller *hose = &pcie1_hose; int pcie_ep; struct pci_region *r = hose->regions; int pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel); pcie_ep = fsl_setup_hose(hose, CONFIG_SYS_PCIE1_ADDR); if (pcie_configured && !(gur->devdisr & MPC85xx_DEVDISR_PCIE)){ printf ("PCIe: %s, base address %x", pcie_ep ? "Endpoint" : "Root complex", (uint)pci); if (pci->pme_msg_det) { pci->pme_msg_det = 0xffffffff; debug (", with errors. Clearing. Now 0x%08x", pci->pme_msg_det); } puts ("\n"); /* outbound memory */ pci_set_region (r++, CONFIG_SYS_PCIE1_MEM_BASE, CONFIG_SYS_PCIE1_MEM_PHYS, CONFIG_SYS_PCIE1_MEM_SIZE, PCI_REGION_MEM); /* outbound io */ pci_set_region (r++, CONFIG_SYS_PCIE1_IO_BASE, CONFIG_SYS_PCIE1_IO_PHYS, CONFIG_SYS_PCIE1_IO_SIZE, PCI_REGION_IO); hose->region_count = r - hose->regions; hose->first_busno = first_free_busno; fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data); printf (" PCIe on bus %02x..%02x\n", hose->first_busno, hose->last_busno); first_free_busno = hose->last_busno + 1; } else { printf ("PCIe: disabled\n"); } #else /* !CONFIG_PCIE1 */ gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */ #endif /* CONFIG_PCIE1 */ }
static void ftpci_preinit(struct ftpci100_data *priv) { struct ftpci100_ahbc *ftpci100; struct pci_controller *hose = (struct pci_controller *)&local_hose; u32 pci_config_addr; u32 pci_config_data; priv->reg_base = CONFIG_FTPCI100_BASE; priv->io_base = CONFIG_FTPCI100_BASE + CONFIG_FTPCI100_IO_SIZE; priv->mmio_base = CONFIG_FTPCI100_MEM_BASE; priv->mem_base = CONFIG_FTPCI100_MEM_BASE + CONFIG_FTPCI100_MEM_SIZE; ftpci100 = (struct ftpci100_ahbc *)priv->reg_base; pci_config_addr = (u32) &ftpci100->conf; pci_config_data = (u32) &ftpci100->data; /* print device name */ printf("FTPCI100\n"); /* dump basic configuration */ debug("%s: Config addr is %08X, data port is %08X\n", __func__, pci_config_addr, pci_config_data); /* PCI memory space */ pci_set_region(hose->regions + 0, CONFIG_PCI_MEM_BUS, CONFIG_PCI_MEM_PHYS, CONFIG_PCI_MEM_SIZE, PCI_REGION_MEM); hose->region_count++; /* PCI IO space */ pci_set_region(hose->regions + 1, CONFIG_PCI_IO_BUS, CONFIG_PCI_IO_PHYS, CONFIG_PCI_IO_SIZE, PCI_REGION_IO); hose->region_count++; #if defined(CONFIG_PCI_SYS_BUS) /* PCI System Memory space */ pci_set_region(hose->regions + 2, CONFIG_PCI_SYS_BUS, CONFIG_PCI_SYS_PHYS, CONFIG_PCI_SYS_SIZE, PCI_REGION_MEM | PCI_REGION_SYS_MEMORY); hose->region_count++; #endif /* setup indirect read/write function */ pci_setup_indirect(hose, pci_config_addr, pci_config_data); /* register hose */ pci_register_hose(hose); }
int pci_sh4_init(struct pci_controller *hose) { hose->first_busno = 0; hose->region_count = 0; hose->last_busno = 0xff; /* PCI memory space */ pci_set_region(hose->regions + 0, CONFIG_PCI_MEM_BUS, CONFIG_PCI_MEM_PHYS, CONFIG_PCI_MEM_SIZE, PCI_REGION_MEM); hose->region_count++; /* PCI IO space */ pci_set_region(hose->regions + 1, CONFIG_PCI_IO_BUS, CONFIG_PCI_IO_PHYS, CONFIG_PCI_IO_SIZE, PCI_REGION_IO); hose->region_count++; #if defined(CONFIG_PCI_SYS_BUS) /* PCI System Memory space */ pci_set_region(hose->regions + 2, CONFIG_PCI_SYS_BUS, CONFIG_PCI_SYS_PHYS, CONFIG_PCI_SYS_SIZE, PCI_REGION_MEM | PCI_REGION_SYS_MEMORY); hose->region_count++; #endif udelay(1000); pci_set_ops(hose, pci_hose_read_config_byte_via_dword, pci_hose_read_config_word_via_dword, pci_sh4_read_config_dword, pci_hose_write_config_byte_via_dword, pci_hose_write_config_word_via_dword, pci_sh4_write_config_dword); pci_register_hose(hose); udelay(1000); #ifdef CONFIG_PCI_SCAN_SHOW printf("PCI: Bus Dev VenId DevId Class Int\n"); #endif hose->last_busno = pci_hose_scan(hose); return 0; }
void pci_mpc824x_init (struct pci_controller *hose) { hose->first_busno = 0; hose->last_busno = 0xff; /* System memory space */ pci_set_region(hose->regions + 0, CHRP_PCI_MEMORY_BUS, CHRP_PCI_MEMORY_PHYS, CHRP_PCI_MEMORY_SIZE, PCI_REGION_MEM | PCI_REGION_SYS_MEMORY); /* PCI memory space */ pci_set_region(hose->regions + 1, CHRP_PCI_MEM_BUS, CHRP_PCI_MEM_PHYS, CHRP_PCI_MEM_SIZE, PCI_REGION_MEM); /* ISA/PCI memory space */ pci_set_region(hose->regions + 2, CHRP_ISA_MEM_BUS, CHRP_ISA_MEM_PHYS, CHRP_ISA_MEM_SIZE, PCI_REGION_MEM); /* PCI I/O space */ pci_set_region(hose->regions + 3, CHRP_PCI_IO_BUS, CHRP_PCI_IO_PHYS, CHRP_PCI_IO_SIZE, PCI_REGION_IO); /* ISA/PCI I/O space */ pci_set_region(hose->regions + 4, CHRP_ISA_IO_BUS, CHRP_ISA_IO_PHYS, CHRP_ISA_IO_SIZE, PCI_REGION_IO); hose->region_count = 5; pci_setup_indirect(hose, CHRP_REG_ADDR, CHRP_REG_DATA); pci_register_hose(hose); hose->last_busno = pci_hose_scan(hose); }
void pci_init_board(void) { coreboot_hose.config_table = pci_coreboot_config_table; coreboot_hose.first_busno = 0; coreboot_hose.last_busno = 0; pci_set_region(coreboot_hose.regions + 0, 0x0, 0x0, 0xffffffff, PCI_REGION_MEM); coreboot_hose.region_count = 1; pci_setup_type1(&coreboot_hose); pci_register_hose(&coreboot_hose); pci_hose_scan(&coreboot_hose); }
void pci_mcf547x_8x_init(struct pci_controller *hose) { volatile pci_t *pci = (volatile pci_t *) MMAP_PCI; volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; /* Port configuration */ gpio->par_pcibg = GPIO_PAR_PCIBG_PCIBG0(3) | GPIO_PAR_PCIBG_PCIBG1(3) | GPIO_PAR_PCIBG_PCIBG2(3) | GPIO_PAR_PCIBG_PCIBG3(3) | GPIO_PAR_PCIBG_PCIBG4(3); gpio->par_pcibr = GPIO_PAR_PCIBR_PCIBR0(3) | GPIO_PAR_PCIBR_PCIBR1(3) | GPIO_PAR_PCIBR_PCIBR2(3) | GPIO_PAR_PCIBR_PCIBR3(3) | GPIO_PAR_PCIBR_PCIBR4(3); /* Assert reset bit */ pci->gscr |= PCI_GSCR_PR; pci->tcr1 = PCI_TCR1_P; /* Initiator windows */ pci->iw0btar = CFG_PCI_MEM_PHYS | (CFG_PCI_MEM_PHYS >> 16); pci->iw1btar = CFG_PCI_IO_PHYS | (CFG_PCI_IO_PHYS >> 16); pci->iw2btar = CFG_PCI_CFG_PHYS | (CFG_PCI_CFG_PHYS >> 16); pci->iwcr = PCI_IWCR_W0C_EN | PCI_IWCR_W1C_EN | PCI_IWCR_W1C_IO | PCI_IWCR_W2C_EN | PCI_IWCR_W2C_IO; pci->icr = 0; /* Enable bus master and mem access */ pci->scr = PCI_SCR_B | PCI_SCR_M; /* Cache line size and master latency */ pci->cr1 = PCI_CR1_CLS(8) | PCI_CR1_LTMR(0xF8); pci->cr2 = 0; #ifdef CFG_PCI_BAR0 pci->bar0 = PCI_BAR_BAR0(CFG_PCI_BAR0); pci->tbatr0a = CFG_PCI_TBATR0 | PCI_TBATR_EN; #endif #ifdef CFG_PCI_BAR1 pci->bar1 = PCI_BAR_BAR1(CFG_PCI_BAR1); pci->tbatr1a = CFG_PCI_TBATR1 | PCI_TBATR_EN; #endif /* Deassert reset bit */ pci->gscr &= ~PCI_GSCR_PR; udelay(1000); /* Enable PCI bus master support */ hose->first_busno = 0; hose->last_busno = 0xff; pci_set_region(hose->regions + 0, CFG_PCI_MEM_BUS, CFG_PCI_MEM_PHYS, CFG_PCI_MEM_SIZE, PCI_REGION_MEM); pci_set_region(hose->regions + 1, CFG_PCI_IO_BUS, CFG_PCI_IO_PHYS, CFG_PCI_IO_SIZE, PCI_REGION_IO); pci_set_region(hose->regions + 2, CFG_PCI_SYS_MEM_BUS, CFG_PCI_SYS_MEM_PHYS, CFG_PCI_SYS_MEM_SIZE, PCI_REGION_MEM | PCI_REGION_MEMORY); hose->region_count = 3; hose->cfg_addr = &(pci->car); hose->cfg_data = (volatile unsigned char *)CFG_PCI_CFG_BUS; pci_set_ops(hose, pci_read_cfg_byte, pci_read_cfg_word, pci_read_cfg_dword, pci_write_cfg_byte, pci_write_cfg_word, pci_write_cfg_dword); /* Hose scan */ pci_register_hose(hose); hose->last_busno = pci_hose_scan(hose); }
PCI_INIT_RET_TYPE pci_init_board (void) { #ifdef CONFIG_ATH_EMULATION prmsg("--- Skipping %s for emulation\n", __func__); #else uint32_t cmd; if (is_drqfn() && !is_qca953x()) { /* * Dont enable PCIe in DRQFN package as it has some issues * related to PCIe */ PCI_INIT_RETURN; } #if defined(CONFIG_MACH_QCA953x) if (ath_reg_rd(RST_BOOTSTRAP_ADDRESS) & RST_BOOTSTRAP_TESTROM_ENABLE_MASK) { ath_reg_rmw_clear(RST_MISC2_ADDRESS, RST_MISC2_PERSTN_RCPHY_SET(1)); ath_reg_wr(PCIE_PHY_REG_1_ADDRESS, PCIE_PHY_REG_1_RESET_1); ath_reg_wr(PCIE_PHY_REG_3_ADDRESS, PCIE_PHY_REG_3_RESET_1); ath_reg_rmw_set(PCIE_PWR_MGMT_ADDRESS, PCIE_PWR_MGMT_ASSERT_CLKREQN_SET(1)); ath_reg_rmw_set(PCIE_PLL_CONFIG_ADDRESS, PCIE_PLL_CONFIG_PLLPWD_SET(1)); ath_reg_rmw_set(RST_RESET_ADDRESS, RST_RESET_PCIE_RESET_SET(1)); ath_reg_rmw_set(RST_RESET_ADDRESS, RST_RESET_PCIE_PHY_RESET_SET(1)); ath_reg_rmw_clear(RST_CLKGAT_EN_ADDRESS, RST_CLKGAT_EN_PCIE_RC_SET(1)); PCI_INIT_RETURN; } else { /* Honeybee -The PCIe reference clock frequency is being changed to vary from 99.968MHz to 99.999MHz using SS modulation */ ath_reg_wr_nf(PCIE_PLL_DITHER_DIV_MAX_ADDRESS, PCIE_PLL_DITHER_DIV_MAX_EN_DITHER_SET(0x1) | PCIE_PLL_DITHER_DIV_MAX_USE_MAX_SET(0x1) | PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_INT_SET(0x17) | PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_FRAC_SET(0x3fff)); ath_reg_wr_nf(PCIE_PLL_DITHER_DIV_MIN_ADDRESS, PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_FRAC_SET(0x3f84)| PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_INT_SET(0x17)); } #else #if defined(CONFIG_MACH_QCA956x) ath_reg_rmw_set(PCIE_PHY_REG_1_ADDRESS, PCIE_PHY_REG_1_S_SET(PCIE_PHY_REG_1_S_RESET)); ath_reg_wr_nf(PCIE_PLL_DITHER_DIV_MAX_ADDRESS, PCIE_PLL_DITHER_DIV_MAX_USE_MAX_SET(0x1) | PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_INT_SET(0x17) | PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_FRAC_SET(0x3fff)); ath_reg_wr_nf(PCIE_PLL_DITHER_DIV_MIN_ADDRESS, PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_FRAC_SET(0x3f84) | PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_INT_SET(0x17)); #else // common for rc1 and rc2 ath_reg_wr_nf(PCIE_PLL_DITHER_DIV_MAX_ADDRESS, PCIE_PLL_DITHER_DIV_MAX_EN_DITHER_SET(0x1) | PCIE_PLL_DITHER_DIV_MAX_USE_MAX_SET(0x1) | PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_INT_SET(0x14) | PCIE_PLL_DITHER_DIV_MAX_DIV_MAX_FRAC_SET(0x3ff)); ath_reg_wr_nf(PCIE_PLL_DITHER_DIV_MIN_ADDRESS, PCIE_PLL_DITHER_DIV_MIN_DIV_MIN_INT_SET(0x14)); #endif #endif ath_reg_wr_nf(PCIE_PLL_CONFIG_ADDRESS, PCIE_PLL_CONFIG_REFDIV_SET(1) | PCIE_PLL_CONFIG_BYPASS_SET(1) | PCIE_PLL_CONFIG_PLLPWD_SET(1)); udelay(10000); ath_reg_rmw_clear(PCIE_PLL_CONFIG_ADDRESS, PCIE_PLL_CONFIG_PLLPWD_SET(1)); udelay(1000); ath_reg_rmw_clear(PCIE_PLL_CONFIG_ADDRESS, PCIE_PLL_CONFIG_BYPASS_SET(1)); udelay(1000); #if !defined(CONFIG_MACH_QCA956x) #ifdef PCIE2_APP_ADDRESS if (!(ath_reg_rd(RST_BOOTSTRAP_ADDRESS) & RST_BOOTSTRAP_PCIE_RC_EP_SELECT_MASK)) { pci_rc2_init_board(); return; } #endif ath_reg_rmw_set(RST_RESET_ADDRESS, RST_RESET_PCIE_PHY_RESET_SET(1)); udelay(10000); ath_reg_rmw_set(RST_RESET_ADDRESS, RST_RESET_PCIE_RESET_SET(1)); udelay(10000); #ifdef PCIE2_APP_ADDRESS ath_reg_rmw_clear(RST_MISC2_ADDRESS, RST_MISC2_PERSTN_RCPHY_SET(1)); udelay(10000); #endif ath_reg_wr_nf(PCIE_RESET_ADDRESS, 0); // Put endpoint in reset udelay(100000); #ifdef PCIE2_APP_ADDRESS ath_reg_rmw_set(RST_MISC2_ADDRESS, RST_MISC2_PERSTN_RCPHY_SET(1)); udelay(10000); #endif ath_reg_rmw_clear(RST_RESET_ADDRESS, RST_RESET_PCIE_PHY_RESET_SET(1)); udelay(10000); ath_reg_rmw_clear(RST_RESET_ADDRESS, RST_RESET_PCIE_RESET_SET(1)); udelay(10000); ath_reg_wr_nf(PCIE_APP_ADDRESS, PCIE_APP_PCIE_BAR_MSN_SET(1) | PCIE_APP_CFG_BE_SET(0xf) | PCIE_APP_SLV_RESP_ERR_MAP_SET(0x3f) | PCIE_APP_LTSSM_ENABLE_SET(1)); cmd = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE | PCI_COMMAND_PARITY | PCI_COMMAND_SERR | PCI_COMMAND_FAST_BACK; ath_local_write_config(PCI_COMMAND, 4, cmd); ath_local_write_config(0x20, 4, 0x1ff01000); ath_local_write_config(0x24, 4, 0x1ff01000); ath_reg_wr_nf(PCIE_RESET_ADDRESS, 4); // Pull endpoint out of reset udelay(100000); /* * Check if the WLAN PCI-E H/W is present, If the * WLAN H/W is not present, skip the PCI platform * initialization code and return */ if (((ath_reg_rd(PCIE_RESET_ADDRESS)) & 0x1) == 0x0) { prmsg("*** Warning *** : PCIe WLAN Module not found !!!\n"); } #endif #ifdef PCIE2_APP_ADDRESS pci_rc2_init_board(); #endif #ifndef COMPRESSED_UBOOT /* * Now, configure for u-boot tools */ hose.first_busno = 0; hose.last_busno = 0xff; /* System space */ pci_set_region( &hose.regions[0], 0x80000000, 0x00000000, 32 * 1024 * 1024, PCI_REGION_MEM | PCI_REGION_MEMORY); /* PCI memory space */ pci_set_region( &hose.regions[1], 0x10000000, 0x10000000, 128 * 1024 * 1024, PCI_REGION_MEM); hose.region_count = 2; pci_register_hose(&hose); pci_set_ops( &hose, pci_hose_read_config_byte_via_dword, pci_hose_read_config_word_via_dword, ath_pci_read_config, pci_hose_write_config_byte_via_dword, pci_hose_write_config_word_via_dword, ath_pci_write_config); #endif plat_dev_init(); #endif /* CONFIG_ATH_EMULATION */ PCI_INIT_RETURN; }
void pci_init_board(void) { volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19; uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16; #ifdef CONFIG_PCI1 { volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI1_ADDR; struct pci_controller *hose = &pci1_hose; struct pci_config_table *table; struct pci_region *r = hose->regions; uint pci_32 = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_PCI32; /* PORDEVSR[15] */ uint pci_arb = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; /* PORDEVSR[14] */ uint pci_clk_sel = gur->porpllsr & MPC85xx_PORDEVSR_PCI1_SPD; /* PORPLLSR[16] */ uint pci_agent = (host_agent == 3) || (host_agent == 4 ) || (host_agent == 6); uint pci_speed = get_clock_freq (); /* PCI PSPEED in [4:5] */ if (!(gur->devdisr & MPC85xx_DEVDISR_PCI1)) { printf (" PCI: %d bit, %s MHz, %s, %s, %s\n", (pci_32) ? 32 : 64, (pci_speed == 33333000) ? "33" : (pci_speed == 66666000) ? "66" : "unknown", pci_clk_sel ? "sync" : "async", pci_agent ? "agent" : "host", pci_arb ? "arbiter" : "external-arbiter" ); /* inbound */ r += fsl_pci_setup_inbound_windows(r); /* outbound memory */ pci_set_region(r++, CONFIG_SYS_PCI1_MEM_BASE, CONFIG_SYS_PCI1_MEM_PHYS, CONFIG_SYS_PCI1_MEM_SIZE, PCI_REGION_MEM); /* outbound io */ pci_set_region(r++, CONFIG_SYS_PCI1_IO_BASE, CONFIG_SYS_PCI1_IO_PHYS, CONFIG_SYS_PCI1_IO_SIZE, PCI_REGION_IO); hose->region_count = r - hose->regions; /* relocate config table pointers */ hose->config_table = \ (struct pci_config_table *)((uint)hose->config_table + gd->reloc_off); for (table = hose->config_table; table && table->vendor; table++) table->config_device += gd->reloc_off; hose->first_busno=first_free_busno; pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data); fsl_pci_init(hose); first_free_busno=hose->last_busno+1; printf ("PCI on bus %02x - %02x\n",hose->first_busno,hose->last_busno); #ifdef CONFIG_PCIX_CHECK if (!(gur->pordevsr & PORDEVSR_PCI)) { /* PCI-X init */ if (CONFIG_SYS_CLK_FREQ < 66000000) printf("PCI-X will only work at 66 MHz\n"); reg16 = PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ | PCI_X_CMD_ERO | PCI_X_CMD_DPERR_E; pci_hose_write_config_word(hose, bus, PCIX_COMMAND, reg16); } #endif } else { printf (" PCI: disabled\n"); } } #else gur->devdisr |= MPC85xx_DEVDISR_PCI1; /* disable */ #endif #ifdef CONFIG_PCI2 { uint pci2_clk_sel = gur->porpllsr & 0x4000; /* PORPLLSR[17] */ uint pci_dual = get_pci_dual (); /* PCI DUAL in CM_PCI[3] */ if (pci_dual) { printf (" PCI2: 32 bit, 66 MHz, %s\n", pci2_clk_sel ? "sync" : "async"); } else { printf (" PCI2: disabled\n"); } } #else gur->devdisr |= MPC85xx_DEVDISR_PCI2; /* disable */ #endif /* CONFIG_PCI2 */ #ifdef CONFIG_PCIE1 { volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR; struct pci_controller *hose = &pcie1_hose; int pcie_ep = (host_agent == 0) || (host_agent == 2 ) || (host_agent == 3); struct pci_region *r = hose->regions; int pcie_configured = io_sel >= 1; if (pcie_configured && !(gur->devdisr & MPC85xx_DEVDISR_PCIE)){ printf ("\n PCIE connected to slot as %s (base address %x)", pcie_ep ? "End Point" : "Root Complex", (uint)pci); if (pci->pme_msg_det) { pci->pme_msg_det = 0xffffffff; debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det); } printf ("\n"); /* inbound */ r += fsl_pci_setup_inbound_windows(r); /* outbound memory */ pci_set_region(r++, CONFIG_SYS_PCIE1_MEM_BASE, CONFIG_SYS_PCIE1_MEM_PHYS, CONFIG_SYS_PCIE1_MEM_SIZE, PCI_REGION_MEM); /* outbound io */ pci_set_region(r++, CONFIG_SYS_PCIE1_IO_BASE, CONFIG_SYS_PCIE1_IO_PHYS, CONFIG_SYS_PCIE1_IO_SIZE, PCI_REGION_IO); hose->region_count = r - hose->regions; hose->first_busno=first_free_busno; pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data); fsl_pci_init(hose); printf ("PCIE on bus %d - %d\n",hose->first_busno,hose->last_busno); first_free_busno=hose->last_busno+1; } else { printf (" PCIE: disabled\n"); } } #else gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */ #endif }
void pci_init_board(void) { volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19; uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16; #ifdef CONFIG_PCI1 { pib_init(); volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCI1_ADDR; extern void fsl_pci_init(struct pci_controller *hose); struct pci_controller *hose = &pci1_hose; uint pci_32 = 1; /* PORDEVSR[15] */ uint pci_arb = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; /* PORDEVSR[14] */ uint pci_clk_sel = gur->porpllsr & MPC85xx_PORDEVSR_PCI1_SPD; /* PORPLLSR[16] */ uint pci_agent = (host_agent == 3) || (host_agent == 4 ) || (host_agent == 6); uint pci_speed = 66666000; if (!(gur->devdisr & MPC85xx_DEVDISR_PCI1)) { printf (" PCI: %d bit, %s MHz, %s, %s, %s\n", (pci_32) ? 32 : 64, (pci_speed == 33333000) ? "33" : (pci_speed == 66666000) ? "66" : "unknown", pci_clk_sel ? "sync" : "async", pci_agent ? "agent" : "host", pci_arb ? "arbiter" : "external-arbiter" ); /* inbound */ pci_set_region(hose->regions + 0, CFG_PCI_MEMORY_BUS, CFG_PCI_MEMORY_PHYS, CFG_PCI_MEMORY_SIZE, PCI_REGION_MEM | PCI_REGION_MEMORY); /* outbound memory */ pci_set_region(hose->regions + 1, CFG_PCI1_MEM_BASE, CFG_PCI1_MEM_PHYS, CFG_PCI1_MEM_SIZE, PCI_REGION_MEM); /* outbound io */ pci_set_region(hose->regions + 2, CFG_PCI1_IO_BASE, CFG_PCI1_IO_PHYS, CFG_PCI1_IO_SIZE, PCI_REGION_IO); hose->region_count = 3; hose->first_busno = first_free_busno; pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data); fsl_pci_init(hose); first_free_busno = hose->last_busno+1; printf ("PCI on bus %02x - %02x\n",hose->first_busno,hose->last_busno); } else { printf (" PCI: disabled\n"); } } #else gur->devdisr |= MPC85xx_DEVDISR_PCI1; /* disable */ #endif #ifdef CONFIG_PCIE1 { volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCIE1_ADDR; extern void fsl_pci_init(struct pci_controller *hose); struct pci_controller *hose = &pcie1_hose; int pcie_ep = (host_agent == 0) || (host_agent == 2 ) || (host_agent == 3); int pcie_configured = io_sel >= 1; if (pcie_configured && !(gur->devdisr & MPC85xx_DEVDISR_PCIE)){ printf ("\n PCIE connected to slot as %s (base address %x)", pcie_ep ? "End Point" : "Root Complex", (uint)pci); if (pci->pme_msg_det) { pci->pme_msg_det = 0xffffffff; debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det); } printf ("\n"); /* inbound */ pci_set_region(hose->regions + 0, CFG_PCI_MEMORY_BUS, CFG_PCI_MEMORY_PHYS, CFG_PCI_MEMORY_SIZE, PCI_REGION_MEM | PCI_REGION_MEMORY); /* outbound memory */ pci_set_region(hose->regions + 1, CFG_PCIE1_MEM_BASE, CFG_PCIE1_MEM_PHYS, CFG_PCIE1_MEM_SIZE, PCI_REGION_MEM); /* outbound io */ pci_set_region(hose->regions + 2, CFG_PCIE1_IO_BASE, CFG_PCIE1_IO_PHYS, CFG_PCIE1_IO_SIZE, PCI_REGION_IO); hose->region_count = 3; hose->first_busno=first_free_busno; pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data); fsl_pci_init(hose); printf ("PCIE on bus %02x - %02x\n",hose->first_busno,hose->last_busno); first_free_busno=hose->last_busno+1; } else { printf (" PCIE: disabled\n"); } } #else gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */ #endif }
void pci_init_board(void) { #ifdef CONFIG_PCI1 { volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI1_ADDR; struct pci_controller *hose = &pci1_hose; struct pci_region *r = hose->regions; volatile immap_t *immap = (immap_t *) CONFIG_SYS_CCSRBAR; volatile ccsr_gur_t *gur = &immap->im_gur; uint devdisr = gur->devdisr; uint io_sel = (gur->pordevsr & MPC8641_PORDEVSR_IO_SEL) >> MPC8641_PORDEVSR_IO_SEL_SHIFT; #ifdef DEBUG uint host1_agent = (gur->porbmsr & MPC8641_PORBMSR_HA) >> MPC8641_PORBMSR_HA_SHIFT; uint pex1_agent = (host1_agent == 0) || (host1_agent == 1); #endif if ((io_sel == 2 || io_sel == 3 || io_sel == 5 || io_sel == 6 || io_sel == 7 || io_sel == 0xF) && !(devdisr & MPC86xx_DEVDISR_PCIEX1)) { debug("PCI-EXPRESS 1: %s \n", pex1_agent ? "Agent" : "Host"); debug("0x%08x=0x%08x ", &pci->pme_msg_det, pci->pme_msg_det); if (pci->pme_msg_det) { pci->pme_msg_det = 0xffffffff; debug(" with errors. Clearing. Now 0x%08x", pci->pme_msg_det); } debug("\n"); /* outbound memory */ pci_set_region(r++, CONFIG_SYS_PCI1_MEM_BUS, CONFIG_SYS_PCI1_MEM_PHYS, CONFIG_SYS_PCI1_MEM_SIZE, PCI_REGION_MEM); /* outbound io */ pci_set_region(r++, CONFIG_SYS_PCI1_IO_BUS, CONFIG_SYS_PCI1_IO_PHYS, CONFIG_SYS_PCI1_IO_SIZE, PCI_REGION_IO); /* inbound */ r += fsl_pci_setup_inbound_windows(r); hose->region_count = r - hose->regions; hose->first_busno=first_free_busno; pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data); fsl_pci_init(hose); first_free_busno=hose->last_busno+1; printf (" PCI-EXPRESS 1 on bus %02x - %02x\n", hose->first_busno,hose->last_busno); /* * Activate ULI1575 legacy chip by performing a fake * memory access. Needed to make ULI RTC work. */ in_be32((unsigned *) ((char *)(CONFIG_SYS_PCI1_MEM_VIRT + CONFIG_SYS_PCI1_MEM_SIZE - 0x1000000))); } else { puts("PCI-EXPRESS 1: Disabled\n"); } } #else puts("PCI-EXPRESS1: Disabled\n"); #endif /* CONFIG_PCI1 */ #ifdef CONFIG_PCI2 { volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI2_ADDR; struct pci_controller *hose = &pci2_hose; struct pci_region *r = hose->regions; /* outbound memory */ pci_set_region(r++, CONFIG_SYS_PCI2_MEM_BUS, CONFIG_SYS_PCI2_MEM_PHYS, CONFIG_SYS_PCI2_MEM_SIZE, PCI_REGION_MEM); /* outbound io */ pci_set_region(r++, CONFIG_SYS_PCI2_IO_BUS, CONFIG_SYS_PCI2_IO_PHYS, CONFIG_SYS_PCI2_IO_SIZE, PCI_REGION_IO); /* inbound */ r += fsl_pci_setup_inbound_windows(r); hose->region_count = r - hose->regions; hose->first_busno=first_free_busno; pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data); fsl_pci_init(hose); first_free_busno=hose->last_busno+1; printf (" PCI-EXPRESS 2 on bus %02x - %02x\n", hose->first_busno,hose->last_busno); } #else puts("PCI-EXPRESS 2: Disabled\n"); #endif /* CONFIG_PCI2 */ }
static inline void init_pci1(void) { volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); #ifdef CONFIG_PCI1 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *)CONFIG_SYS_PCI1_ADDR; struct pci_controller *hose = &pci1_hose; struct pci_region *r = hose->regions; /* PORDEVSR[15] */ uint pci_32 = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_PCI32; /* PORDEVSR[14] */ uint pci_arb = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; /* PORPLLSR[16] */ uint pci_clk_sel = gur->porpllsr & MPC85xx_PORDEVSR_PCI1_SPD; int pci_agent = fsl_setup_hose(hose, CONFIG_SYS_PCI1_ADDR); uint pci_speed = CONFIG_SYS_CLK_FREQ; /* PCI PSPEED in [4:5] */ if (!(gur->devdisr & MPC85xx_DEVDISR_PCI1)) { printf ("PCI1: %d bit, %s MHz, %s, %s, %s\n", (pci_32) ? 32 : 64, (pci_speed == 33333333) ? "33" : (pci_speed == 66666666) ? "66" : "unknown", pci_clk_sel ? "sync" : "async", pci_agent ? "agent" : "host", pci_arb ? "arbiter" : "external-arbiter"); /* outbound memory */ pci_set_region (r++, CONFIG_SYS_PCI1_MEM_BASE, CONFIG_SYS_PCI1_MEM_PHYS, CONFIG_SYS_PCI1_MEM_SIZE, PCI_REGION_MEM); /* outbound io */ pci_set_region (r++, CONFIG_SYS_PCI1_IO_BASE, CONFIG_SYS_PCI1_IO_PHYS, CONFIG_SYS_PCI1_IO_SIZE, PCI_REGION_IO); hose->region_count = r - hose->regions; hose->first_busno = first_free_busno; fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data); printf (" PCI on bus %02x..%02x\n", hose->first_busno, hose->last_busno); first_free_busno = hose->last_busno + 1; #ifdef CONFIG_PCIX_CHECK if (!(gur->pordevsr & MPC85xx_PORDEVSR_PCI1)) { ushort reg16 = PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ | PCI_X_CMD_ERO | PCI_X_CMD_DPERR_E; uint dev = PCI_BDF(hose->first_busno, 0, 0); /* PCI-X init */ if (CONFIG_SYS_CLK_FREQ < 66000000) puts ("PCI-X will only work at 66 MHz\n"); pci_hose_write_config_word (hose, dev, PCIX_COMMAND, reg16); } #endif } else { puts ("PCI1: disabled\n"); } #else /* !CONFIG_PCI1 */ gur->devdisr |= MPC85xx_DEVDISR_PCI1; /* disable */ #endif /* CONFIG_PCI1 */ }
int pci_440_init (struct pci_controller *hose) { int reg_num = 0; #ifndef CONFIG_DISABLE_PISE_TEST /*--------------------------------------------------------------------------+ * The PCI initialization sequence enable bit must be set ... if not abort * pci setup since updating the bit requires chip reset. *--------------------------------------------------------------------------*/ #if defined(CONFIG_440GX) || defined(CONFIG_440SP) || defined(CONFIG_440SPE) unsigned long strap; mfsdr(sdr_sdstp1,strap); if ((strap & SDR0_SDSTP1_PISE_MASK) == 0) { printf("PCI: SDR0_STRP1[PISE] not set.\n"); printf("PCI: Configuration aborted.\n"); return -1; } #elif defined(CONFIG_440GP) unsigned long strap; strap = mfdcr(cpc0_strp1); if ((strap & CPC0_STRP1_PISE_MASK) == 0) { printf("PCI: CPC0_STRP1[PISE] not set.\n"); printf("PCI: Configuration aborted.\n"); return -1; } #endif #endif /* CONFIG_DISABLE_PISE_TEST */ /*--------------------------------------------------------------------------+ * PCI controller init *--------------------------------------------------------------------------*/ hose->first_busno = 0; hose->last_busno = 0; /* PCI I/O space */ pci_set_region(hose->regions + reg_num++, 0x00000000, PCIX0_IOBASE, 0x10000, PCI_REGION_IO); /* PCI memory space */ pci_set_region(hose->regions + reg_num++, CONFIG_SYS_PCI_TARGBASE, CONFIG_SYS_PCI_MEMBASE, #ifdef CONFIG_SYS_PCI_MEMSIZE CONFIG_SYS_PCI_MEMSIZE, #else 0x10000000, #endif PCI_REGION_MEM ); #if defined(CONFIG_PCI_SYS_MEM_BUS) && defined(CONFIG_PCI_SYS_MEM_PHYS) && \ defined(CONFIG_PCI_SYS_MEM_SIZE) /* System memory space */ pci_set_region(hose->regions + reg_num++, CONFIG_PCI_SYS_MEM_BUS, CONFIG_PCI_SYS_MEM_PHYS, CONFIG_PCI_SYS_MEM_SIZE, PCI_REGION_MEM | PCI_REGION_SYS_MEMORY ); #endif hose->region_count = reg_num; pci_setup_indirect(hose, PCIX0_CFGADR, PCIX0_CFGDATA); /* Let board change/modify hose & do initial checks */ if (pci_pre_init (hose) == 0) { printf("PCI: Board-specific initialization failed.\n"); printf("PCI: Configuration aborted.\n"); return -1; } pci_register_hose( hose ); /*--------------------------------------------------------------------------+ * PCI target init *--------------------------------------------------------------------------*/ #if defined(CONFIG_SYS_PCI_TARGET_INIT) pci_target_init(hose); /* Let board setup pci target */ #else out16r( PCIX0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID ); out16r( PCIX0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_ID ); out16r( PCIX0_CLS, 0x00060000 ); /* Bridge, host bridge */ #endif #if defined(CONFIG_440GX) || defined(CONFIG_440SPE) || \ defined(CONFIG_460EX) || defined(CONFIG_460GT) out32r( PCIX0_BRDGOPT1, 0x04000060 ); /* PLB Rq pri highest */ out32r( PCIX0_BRDGOPT2, in32(PCIX0_BRDGOPT2) | 0x83 ); /* Enable host config, clear Timeout, ensure int src1 */ #elif defined(PCIX0_BRDGOPT1) out32r( PCIX0_BRDGOPT1, 0x10000060 ); /* PLB Rq pri highest */ out32r( PCIX0_BRDGOPT2, in32(PCIX0_BRDGOPT2) | 1 ); /* Enable host config */ #endif /*--------------------------------------------------------------------------+ * PCI master init: default is one 256MB region for PCI memory: * 0x3_00000000 - 0x3_0FFFFFFF ==> CONFIG_SYS_PCI_MEMBASE *--------------------------------------------------------------------------*/ #if defined(CONFIG_SYS_PCI_MASTER_INIT) pci_master_init(hose); /* Let board setup pci master */ #else out32r( PCIX0_POM0SA, 0 ); /* disable */ out32r( PCIX0_POM1SA, 0 ); /* disable */ out32r( PCIX0_POM2SA, 0 ); /* disable */ #if defined(CONFIG_440SPE) || \ defined(CONFIG_460EX) || defined(CONFIG_460GT) out32r( PCIX0_POM0LAL, 0x10000000 ); out32r( PCIX0_POM0LAH, 0x0000000c ); #else out32r( PCIX0_POM0LAL, 0x00000000 ); out32r( PCIX0_POM0LAH, 0x00000003 ); #endif out32r( PCIX0_POM0PCIAL, CONFIG_SYS_PCI_MEMBASE ); out32r( PCIX0_POM0PCIAH, 0x00000000 ); out32r( PCIX0_POM0SA, 0xf0000001 ); /* 256MB, enabled */ out32r( PCIX0_STS, in32r( PCIX0_STS ) & ~0x0000fff8 ); #endif /*--------------------------------------------------------------------------+ * PCI host configuration -- we don't make any assumptions here ... the * _board_must_indicate_ what to do -- there's just too many runtime * scenarios in environments like cPCI, PPMC, etc. to make a determination * based on hard-coded values or state of arbiter enable. *--------------------------------------------------------------------------*/ if (is_pci_host(hose)) { #ifdef CONFIG_PCI_SCAN_SHOW printf("PCI: Bus Dev VenId DevId Class Int\n"); #endif #if !defined(CONFIG_440EP) && !defined(CONFIG_440GR) && \ !defined(CONFIG_440EPX) && !defined(CONFIG_440GRX) out16r( PCIX0_CMD, in16r( PCIX0_CMD ) | PCI_COMMAND_MASTER); #endif hose->last_busno = pci_hose_scan(hose); } return hose->last_busno; }
/*-----------------------------------------------------------------------------+ * pci_init. Initializes the 405GP PCI Configuration regs. *-----------------------------------------------------------------------------*/ void pci_405gp_init(struct pci_controller *hose) { int i, reg_num = 0; bd_t *bd = gd->bd; unsigned short temp_short; unsigned long ptmpcila[2] = {CONFIG_SYS_PCI_PTM1PCI, CONFIG_SYS_PCI_PTM2PCI}; #if defined(CONFIG_CPCI405) || defined(CONFIG_PMC405) char *ptmla_str, *ptmms_str; #endif unsigned long ptmla[2] = {CONFIG_SYS_PCI_PTM1LA, CONFIG_SYS_PCI_PTM2LA}; unsigned long ptmms[2] = {CONFIG_SYS_PCI_PTM1MS, CONFIG_SYS_PCI_PTM2MS}; #if defined(CONFIG_PIP405) || defined (CONFIG_MIP405) unsigned long pmmla[3] = {0x80000000, 0xA0000000, 0}; unsigned long pmmma[3] = {0xE0000001, 0xE0000001, 0}; unsigned long pmmpcila[3] = {0x80000000, 0x00000000, 0}; unsigned long pmmpciha[3] = {0x00000000, 0x00000000, 0}; #else unsigned long pmmla[3] = {0x80000000, 0,0}; unsigned long pmmma[3] = {0xC0000001, 0,0}; unsigned long pmmpcila[3] = {0x80000000, 0,0}; unsigned long pmmpciha[3] = {0x00000000, 0,0}; #endif #ifdef CONFIG_PCI_PNP #if (CONFIG_PCI_HOST == PCI_HOST_AUTO) char *s; #endif #endif #if defined(CONFIG_CPCI405) || defined(CONFIG_PMC405) ptmla_str = getenv("ptm1la"); ptmms_str = getenv("ptm1ms"); if(NULL != ptmla_str && NULL != ptmms_str ) { ptmla[0] = simple_strtoul (ptmla_str, NULL, 16); ptmms[0] = simple_strtoul (ptmms_str, NULL, 16); } ptmla_str = getenv("ptm2la"); ptmms_str = getenv("ptm2ms"); if(NULL != ptmla_str && NULL != ptmms_str ) { ptmla[1] = simple_strtoul (ptmla_str, NULL, 16); ptmms[1] = simple_strtoul (ptmms_str, NULL, 16); } #endif /* * Register the hose */ hose->first_busno = 0; hose->last_busno = 0xff; /* ISA/PCI I/O space */ pci_set_region(hose->regions + reg_num++, MIN_PCI_PCI_IOADDR, MIN_PLB_PCI_IOADDR, 0x10000, PCI_REGION_IO); /* PCI I/O space */ pci_set_region(hose->regions + reg_num++, 0x00800000, 0xe8800000, 0x03800000, PCI_REGION_IO); reg_num = 2; /* Memory spaces */ for (i=0; i<2; i++) if (ptmms[i] & 1) { if (!i) hose->pci_fb = hose->regions + reg_num; pci_set_region(hose->regions + reg_num++, ptmpcila[i], ptmla[i], ~(ptmms[i] & 0xfffff000) + 1, PCI_REGION_MEM | PCI_REGION_SYS_MEMORY); } /* PCI memory spaces */ for (i=0; i<3; i++) if (pmmma[i] & 1) { pci_set_region(hose->regions + reg_num++, pmmpcila[i], pmmla[i], ~(pmmma[i] & 0xfffff000) + 1, PCI_REGION_MEM); } hose->region_count = reg_num; pci_setup_indirect(hose, PCICFGADR, PCICFGDATA); if (hose->pci_fb) pciauto_region_init(hose->pci_fb); /* Let board change/modify hose & do initial checks */ if (pci_pre_init (hose) == 0) { printf("PCI: Board-specific initialization failed.\n"); printf("PCI: Configuration aborted.\n"); return; } pci_register_hose(hose); /*--------------------------------------------------------------------------+ * 405GP PCI Master configuration. * Map one 512 MB range of PLB/processor addresses to PCI memory space. * PLB address 0x80000000-0xBFFFFFFF ==> PCI address 0x80000000-0xBFFFFFFF * Use byte reversed out routines to handle endianess. *--------------------------------------------------------------------------*/ out32r(PMM0MA, (pmmma[0]&~0x1)); /* disable, configure PMMxLA, PMMxPCILA first */ out32r(PMM0LA, pmmla[0]); out32r(PMM0PCILA, pmmpcila[0]); out32r(PMM0PCIHA, pmmpciha[0]); out32r(PMM0MA, pmmma[0]); /*--------------------------------------------------------------------------+ * PMM1 is not used. Initialize them to zero. *--------------------------------------------------------------------------*/ out32r(PMM1MA, (pmmma[1]&~0x1)); out32r(PMM1LA, pmmla[1]); out32r(PMM1PCILA, pmmpcila[1]); out32r(PMM1PCIHA, pmmpciha[1]); out32r(PMM1MA, pmmma[1]); /*--------------------------------------------------------------------------+ * PMM2 is not used. Initialize them to zero. *--------------------------------------------------------------------------*/ out32r(PMM2MA, (pmmma[2]&~0x1)); out32r(PMM2LA, pmmla[2]); out32r(PMM2PCILA, pmmpcila[2]); out32r(PMM2PCIHA, pmmpciha[2]); out32r(PMM2MA, pmmma[2]); /*--------------------------------------------------------------------------+ * 405GP PCI Target configuration. (PTM1) * Note: PTM1MS is hardwire enabled but we set the enable bit anyway. *--------------------------------------------------------------------------*/ out32r(PTM1LA, ptmla[0]); /* insert address */ out32r(PTM1MS, ptmms[0]); /* insert size, enable bit is 1 */ pci_write_config_dword(PCIDEVID_405GP, PCI_BASE_ADDRESS_1, ptmpcila[0]); /*--------------------------------------------------------------------------+ * 405GP PCI Target configuration. (PTM2) *--------------------------------------------------------------------------*/ out32r(PTM2LA, ptmla[1]); /* insert address */ pci_write_config_dword(PCIDEVID_405GP, PCI_BASE_ADDRESS_2, ptmpcila[1]); if (ptmms[1] == 0) { out32r(PTM2MS, 0x00000001); /* set enable bit */ pci_write_config_dword(PCIDEVID_405GP, PCI_BASE_ADDRESS_2, 0x00000000); out32r(PTM2MS, 0x00000000); /* disable */ } else { out32r(PTM2MS, ptmms[1]); /* insert size, enable bit is 1 */ } /* * Insert Subsystem Vendor and Device ID */ pci_write_config_word(PCIDEVID_405GP, PCI_SUBSYSTEM_VENDOR_ID, CONFIG_SYS_PCI_SUBSYS_VENDORID); #ifdef CONFIG_CPCI405 if (mfdcr(strap) & PSR_PCI_ARBIT_EN) pci_write_config_word(PCIDEVID_405GP, PCI_SUBSYSTEM_ID, CONFIG_SYS_PCI_SUBSYS_DEVICEID); else pci_write_config_word(PCIDEVID_405GP, PCI_SUBSYSTEM_ID, CONFIG_SYS_PCI_SUBSYS_DEVICEID2); #else pci_write_config_word(PCIDEVID_405GP, PCI_SUBSYSTEM_ID, CONFIG_SYS_PCI_SUBSYS_DEVICEID); #endif /* * Insert Class-code */ #ifdef CONFIG_SYS_PCI_CLASSCODE pci_write_config_word(PCIDEVID_405GP, PCI_CLASS_SUB_CODE, CONFIG_SYS_PCI_CLASSCODE); #endif /* CONFIG_SYS_PCI_CLASSCODE */ /*--------------------------------------------------------------------------+ * If PCI speed = 66MHz, set 66MHz capable bit. *--------------------------------------------------------------------------*/ if (bd->bi_pci_busfreq >= 66000000) { pci_read_config_word(PCIDEVID_405GP, PCI_STATUS, &temp_short); pci_write_config_word(PCIDEVID_405GP,PCI_STATUS,(temp_short|PCI_STATUS_66MHZ)); } #if (CONFIG_PCI_HOST != PCI_HOST_ADAPTER) #if (CONFIG_PCI_HOST == PCI_HOST_AUTO) if ((mfdcr(strap) & PSR_PCI_ARBIT_EN) || (((s = getenv("pciscan")) != NULL) && (strcmp(s, "yes") == 0))) #endif { /*--------------------------------------------------------------------------+ * Write the 405GP PCI Configuration regs. * Enable 405GP to be a master on the PCI bus (PMM). * Enable 405GP to act as a PCI memory target (PTM). *--------------------------------------------------------------------------*/ pci_read_config_word(PCIDEVID_405GP, PCI_COMMAND, &temp_short); pci_write_config_word(PCIDEVID_405GP, PCI_COMMAND, temp_short | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); } #endif #if defined(CONFIG_405EP) /* on ppc405ep vendor id is not set */ pci_write_config_word(PCIDEVID_405GP, PCI_VENDOR_ID, 0x1014); /* IBM */ #endif /* * Set HCE bit (Host Configuration Enabled) */ pci_read_config_word(PCIDEVID_405GP, PCIBRDGOPT2, &temp_short); pci_write_config_word(PCIDEVID_405GP, PCIBRDGOPT2, (temp_short | 0x0001)); #ifdef CONFIG_PCI_PNP /*--------------------------------------------------------------------------+ * Scan the PCI bus and configure devices found. *--------------------------------------------------------------------------*/ #if (CONFIG_PCI_HOST == PCI_HOST_AUTO) if ((mfdcr(strap) & PSR_PCI_ARBIT_EN) || (((s = getenv("pciscan")) != NULL) && (strcmp(s, "yes") == 0))) #endif { #ifdef CONFIG_PCI_SCAN_SHOW printf("PCI: Bus Dev VenId DevId Class Int\n"); #endif hose->last_busno = pci_hose_scan(hose); } #endif /* CONFIG_PCI_PNP */ }
void pci_init_board(void) { volatile immap_t *immap = (immap_t *) CFG_CCSRBAR; volatile ccsr_gur_t *gur = &immap->im_gur; uint devdisr = gur->devdisr; uint io_sel = (gur->pordevsr & MPC8641_PORDEVSR_IO_SEL) >> MPC8641_PORDEVSR_IO_SEL_SHIFT; #ifdef CONFIG_PCI1 { volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCI1_ADDR; extern void fsl_pci_init(struct pci_controller *hose); struct pci_controller *hose = &pci1_hose; #ifdef DEBUG uint host1_agent = (gur->porbmsr & MPC8641_PORBMSR_HA) >> MPC8641_PORBMSR_HA_SHIFT; uint pex1_agent = (host1_agent == 0) || (host1_agent == 1); #endif if ((io_sel == 2 || io_sel == 3 || io_sel == 5 || io_sel == 6 || io_sel == 7 || io_sel == 0xF) && !(devdisr & MPC86xx_DEVDISR_PCIEX1)) { debug("PCI-EXPRESS 1: %s \n", pex1_agent ? "Agent" : "Host"); debug("0x%08x=0x%08x ", &pci->pme_msg_det, pci->pme_msg_det); if (pci->pme_msg_det) { pci->pme_msg_det = 0xffffffff; debug(" with errors. Clearing. Now 0x%08x", pci->pme_msg_det); } debug("\n"); /* inbound */ pci_set_region(hose->regions + 0, CFG_PCI_MEMORY_BUS, CFG_PCI_MEMORY_PHYS, CFG_PCI_MEMORY_SIZE, PCI_REGION_MEM | PCI_REGION_MEMORY); /* outbound memory */ pci_set_region(hose->regions + 1, CFG_PCI1_MEM_BASE, CFG_PCI1_MEM_PHYS, CFG_PCI1_MEM_SIZE, PCI_REGION_MEM); /* outbound io */ pci_set_region(hose->regions + 2, CFG_PCI1_IO_BASE, CFG_PCI1_IO_PHYS, CFG_PCI1_IO_SIZE, PCI_REGION_IO); hose->region_count = 3; hose->first_busno=first_free_busno; pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data); fsl_pci_init(hose); first_free_busno=hose->last_busno+1; printf (" PCI-EXPRESS 1 on bus %02x - %02x\n", hose->first_busno,hose->last_busno); } else { puts("PCI-EXPRESS 1: Disabled\n"); } } #else puts("PCI-EXPRESS1: Disabled\n"); #endif /* CONFIG_PCI1 */ #ifdef CONFIG_PCI2 { volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCI2_ADDR; extern void fsl_pci_init(struct pci_controller *hose); struct pci_controller *hose = &pci2_hose; /* inbound */ pci_set_region(hose->regions + 0, CFG_PCI_MEMORY_BUS, CFG_PCI_MEMORY_PHYS, CFG_PCI_MEMORY_SIZE, PCI_REGION_MEM | PCI_REGION_MEMORY); /* outbound memory */ pci_set_region(hose->regions + 1, CFG_PCI2_MEM_BASE, CFG_PCI2_MEM_PHYS, CFG_PCI2_MEM_SIZE, PCI_REGION_MEM); /* outbound io */ pci_set_region(hose->regions + 2, CFG_PCI2_IO_BASE, CFG_PCI2_IO_PHYS, CFG_PCI2_IO_SIZE, PCI_REGION_IO); hose->region_count = 3; hose->first_busno=first_free_busno; pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data); fsl_pci_init(hose); first_free_busno=hose->last_busno+1; printf (" PCI-EXPRESS 2 on bus %02x - %02x\n", hose->first_busno,hose->last_busno); } #else puts("PCI-EXPRESS 2: Disabled\n"); #endif /* CONFIG_PCI2 */ }
void pci_init_board(void) { volatile immap_t *immap = (immap_t *) CONFIG_SYS_CCSRBAR; volatile ccsr_gur_t *gur = &immap->im_gur; uint devdisr = gur->devdisr; uint io_sel = (gur->pordevsr & MPC8610_PORDEVSR_IO_SEL) >> MPC8610_PORDEVSR_IO_SEL_SHIFT; uint host_agent = (gur->porbmsr & MPC8610_PORBMSR_HA) >> MPC8610_PORBMSR_HA_SHIFT; printf( " pci_init_board: devdisr=%x, io_sel=%x, host_agent=%x\n", devdisr, io_sel, host_agent); #ifdef CONFIG_PCIE1 { volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR; struct pci_controller *hose = &pcie1_hose; int pcie_configured = (io_sel == 1) || (io_sel == 4); int pcie_ep = (host_agent == 0) || (host_agent == 2) || (host_agent == 5); struct pci_region *r = hose->regions; if (pcie_configured && !(devdisr & MPC86xx_DEVDISR_PCIE1)) { printf(" PCIe 1 connected to Uli as %s (base address %x)\n", pcie_ep ? "End Point" : "Root Complex", (uint)pci); if (pci->pme_msg_det) pci->pme_msg_det = 0xffffffff; /* inbound */ r += fsl_pci_setup_inbound_windows(r); /* outbound memory */ pci_set_region(r++, CONFIG_SYS_PCIE1_MEM_BUS, CONFIG_SYS_PCIE1_MEM_PHYS, CONFIG_SYS_PCIE1_MEM_SIZE, PCI_REGION_MEM); /* outbound io */ pci_set_region(r++, CONFIG_SYS_PCIE1_IO_BUS, CONFIG_SYS_PCIE1_IO_PHYS, CONFIG_SYS_PCIE1_IO_SIZE, PCI_REGION_IO); hose->region_count = r - hose->regions; hose->first_busno = first_free_busno; pci_setup_indirect(hose, (int)&pci->cfg_addr, (int)&pci->cfg_data); fsl_pci_init(hose); first_free_busno = hose->last_busno + 1; printf(" PCI-Express 1 on bus %02x - %02x\n", hose->first_busno, hose->last_busno); } else puts(" PCI-Express 1: Disabled\n"); } #else puts("PCI-Express 1: Disabled\n"); #endif /* CONFIG_PCIE1 */ #ifdef CONFIG_PCIE2 { volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE2_ADDR; struct pci_controller *hose = &pcie2_hose; struct pci_region *r = hose->regions; int pcie_configured = (io_sel == 0) || (io_sel == 4); int pcie_ep = (host_agent == 0) || (host_agent == 1) || (host_agent == 4); if (pcie_configured && !(devdisr & MPC86xx_DEVDISR_PCIE2)) { printf(" PCI-Express 2 connected to slot as %s" \ " (base address %x)\n", pcie_ep ? "End Point" : "Root Complex", (uint)pci); if (pci->pme_msg_det) pci->pme_msg_det = 0xffffffff; /* inbound */ r += fsl_pci_setup_inbound_windows(r); /* outbound memory */ pci_set_region(r++, CONFIG_SYS_PCIE2_MEM_BUS, CONFIG_SYS_PCIE2_MEM_PHYS, CONFIG_SYS_PCIE2_MEM_SIZE, PCI_REGION_MEM); /* outbound io */ pci_set_region(r++, CONFIG_SYS_PCIE2_IO_BUS, CONFIG_SYS_PCIE2_IO_PHYS, CONFIG_SYS_PCIE2_IO_SIZE, PCI_REGION_IO); hose->region_count = r - hose->regions; hose->first_busno = first_free_busno; pci_setup_indirect(hose, (int)&pci->cfg_addr, (int)&pci->cfg_data); fsl_pci_init(hose); first_free_busno = hose->last_busno + 1; printf(" PCI-Express 2 on bus %02x - %02x\n", hose->first_busno, hose->last_busno); } else puts(" PCI-Express 2: Disabled\n"); } #else puts("PCI-Express 2: Disabled\n"); #endif /* CONFIG_PCIE2 */ #ifdef CONFIG_PCI1 { volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI1_ADDR; struct pci_controller *hose = &pci1_hose; int pci_agent = (host_agent >= 4) && (host_agent <= 6); struct pci_region *r = hose->regions; if ( !(devdisr & MPC86xx_DEVDISR_PCI1)) { printf(" PCI connected to PCI slots as %s" \ " (base address %x)\n", pci_agent ? "Agent" : "Host", (uint)pci); /* inbound */ r += fsl_pci_setup_inbound_windows(r); /* outbound memory */ pci_set_region(r++, CONFIG_SYS_PCI1_MEM_BUS, CONFIG_SYS_PCI1_MEM_PHYS, CONFIG_SYS_PCI1_MEM_SIZE, PCI_REGION_MEM); /* outbound io */ pci_set_region(r++, CONFIG_SYS_PCI1_IO_BUS, CONFIG_SYS_PCI1_IO_PHYS, CONFIG_SYS_PCI1_IO_SIZE, PCI_REGION_IO); hose->region_count = r - hose->regions; hose->first_busno = first_free_busno; pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data); fsl_pci_init(hose); first_free_busno = hose->last_busno + 1; printf(" PCI on bus %02x - %02x\n", hose->first_busno, hose->last_busno); } else puts(" PCI: Disabled\n"); } #endif /* CONFIG_PCI1 */ }
void pci_init_board(void) { volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); uint devdisr = gur->devdisr; uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19; uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16; debug (" pci_init_board: devdisr=%x, io_sel=%x, host_agent=%x\n", devdisr, io_sel, host_agent); if (io_sel & 1) { if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII1_DIS)) printf (" eTSEC1 is in sgmii mode.\n"); if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS)) printf (" eTSEC3 is in sgmii mode.\n"); } #ifdef CONFIG_PCIE3 { volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE3_ADDR; struct pci_controller *hose = &pcie3_hose; int pcie_ep = (host_agent == 1); int pcie_configured = io_sel >= 6; struct pci_region *r = hose->regions; if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){ printf ("\n PCIE3 connected to ULI as %s (base address %x)", pcie_ep ? "End Point" : "Root Complex", (uint)pci); if (pci->pme_msg_det) { pci->pme_msg_det = 0xffffffff; debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det); } printf ("\n"); /* inbound */ r += fsl_pci_setup_inbound_windows(r); /* outbound memory */ pci_set_region(r++, CONFIG_SYS_PCIE3_MEM_BUS, CONFIG_SYS_PCIE3_MEM_PHYS, CONFIG_SYS_PCIE3_MEM_SIZE, PCI_REGION_MEM); /* outbound io */ pci_set_region(r++, CONFIG_SYS_PCIE3_IO_BUS, CONFIG_SYS_PCIE3_IO_PHYS, CONFIG_SYS_PCIE3_IO_SIZE, PCI_REGION_IO); #ifdef CONFIG_SYS_PCIE3_MEM_BUS2 /* outbound memory */ pci_set_region(r++, CONFIG_SYS_PCIE3_MEM_BUS2, CONFIG_SYS_PCIE3_MEM_PHYS2, CONFIG_SYS_PCIE3_MEM_SIZE2, PCI_REGION_MEM); #endif hose->region_count = r - hose->regions; hose->first_busno=first_free_busno; pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data); fsl_pci_init(hose); first_free_busno=hose->last_busno+1; printf (" PCIE3 on bus %02x - %02x\n", hose->first_busno,hose->last_busno); /* * Activate ULI1575 legacy chip by performing a fake * memory access. Needed to make ULI RTC work. */ in_be32((u32 *)CONFIG_SYS_PCIE3_MEM_BUS); } else { printf (" PCIE3: disabled\n"); } } #else gur->devdisr |= MPC85xx_DEVDISR_PCIE3; /* disable */ #endif #ifdef CONFIG_PCIE1 { volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR; struct pci_controller *hose = &pcie1_hose; int pcie_ep = (host_agent == 5); int pcie_configured = io_sel >= 2; struct pci_region *r = hose->regions; if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){ printf ("\n PCIE1 connected to Slot2 as %s (base address %x)", pcie_ep ? "End Point" : "Root Complex", (uint)pci); if (pci->pme_msg_det) { pci->pme_msg_det = 0xffffffff; debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det); } printf ("\n"); /* inbound */ r += fsl_pci_setup_inbound_windows(r); /* outbound memory */ pci_set_region(r++, CONFIG_SYS_PCIE1_MEM_BUS, CONFIG_SYS_PCIE1_MEM_PHYS, CONFIG_SYS_PCIE1_MEM_SIZE, PCI_REGION_MEM); /* outbound io */ pci_set_region(r++, CONFIG_SYS_PCIE1_IO_BUS, CONFIG_SYS_PCIE1_IO_PHYS, CONFIG_SYS_PCIE1_IO_SIZE, PCI_REGION_IO); #ifdef CONFIG_SYS_PCIE1_MEM_BUS2 /* outbound memory */ pci_set_region(r++, CONFIG_SYS_PCIE1_MEM_BUS2, CONFIG_SYS_PCIE1_MEM_PHYS2, CONFIG_SYS_PCIE1_MEM_SIZE2, PCI_REGION_MEM); #endif hose->region_count = r - hose->regions; hose->first_busno=first_free_busno; pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data); fsl_pci_init(hose); first_free_busno=hose->last_busno+1; printf(" PCIE1 on bus %02x - %02x\n", hose->first_busno,hose->last_busno); } else { printf (" PCIE1: disabled\n"); } } #else gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */ #endif #ifdef CONFIG_PCIE2 { volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE2_ADDR; struct pci_controller *hose = &pcie2_hose; int pcie_ep = (host_agent == 3); int pcie_configured = io_sel >= 4; struct pci_region *r = hose->regions; if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){ printf ("\n PCIE2 connected to Slot 1 as %s (base address %x)", pcie_ep ? "End Point" : "Root Complex", (uint)pci); if (pci->pme_msg_det) { pci->pme_msg_det = 0xffffffff; debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det); } printf ("\n"); /* inbound */ r += fsl_pci_setup_inbound_windows(r); /* outbound memory */ pci_set_region(r++, CONFIG_SYS_PCIE2_MEM_BUS, CONFIG_SYS_PCIE2_MEM_PHYS, CONFIG_SYS_PCIE2_MEM_SIZE, PCI_REGION_MEM); /* outbound io */ pci_set_region(r++, CONFIG_SYS_PCIE2_IO_BUS, CONFIG_SYS_PCIE2_IO_PHYS, CONFIG_SYS_PCIE2_IO_SIZE, PCI_REGION_IO); #ifdef CONFIG_SYS_PCIE2_MEM_BUS2 /* outbound memory */ pci_set_region(r++, CONFIG_SYS_PCIE2_MEM_BUS2, CONFIG_SYS_PCIE2_MEM_PHYS2, CONFIG_SYS_PCIE2_MEM_SIZE2, PCI_REGION_MEM); #endif hose->region_count = r - hose->regions; hose->first_busno=first_free_busno; pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data); fsl_pci_init(hose); first_free_busno=hose->last_busno+1; printf (" PCIE2 on bus %02x - %02x\n", hose->first_busno,hose->last_busno); } else { printf (" PCIE2: disabled\n"); } } #else gur->devdisr |= MPC85xx_DEVDISR_PCIE2; /* disable */ #endif #ifdef CONFIG_PCI1 { volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI1_ADDR; struct pci_controller *hose = &pci1_hose; struct pci_region *r = hose->regions; uint pci_agent = (host_agent == 6); uint pci_speed = 66666000; /*get_clock_freq (); PCI PSPEED in [4:5] */ uint pci_32 = 1; uint pci_arb = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; /* PORDEVSR[14] */ uint pci_clk_sel = gur->porpllsr & MPC85xx_PORDEVSR_PCI1_SPD; /* PORPLLSR[16] */ if (!(devdisr & MPC85xx_DEVDISR_PCI1)) { printf ("\n PCI: %d bit, %s MHz, %s, %s, %s (base address %x)\n", (pci_32) ? 32 : 64, (pci_speed == 33333000) ? "33" : (pci_speed == 66666000) ? "66" : "unknown", pci_clk_sel ? "sync" : "async", pci_agent ? "agent" : "host", pci_arb ? "arbiter" : "external-arbiter", (uint)pci ); /* inbound */ r += fsl_pci_setup_inbound_windows(r); /* outbound memory */ pci_set_region(r++, CONFIG_SYS_PCI1_MEM_BUS, CONFIG_SYS_PCI1_MEM_PHYS, CONFIG_SYS_PCI1_MEM_SIZE, PCI_REGION_MEM); /* outbound io */ pci_set_region(r++, CONFIG_SYS_PCI1_IO_BUS, CONFIG_SYS_PCI1_IO_PHYS, CONFIG_SYS_PCI1_IO_SIZE, PCI_REGION_IO); #ifdef CONFIG_SYS_PCIE3_MEM_BUS2 /* outbound memory */ pci_set_region(r++, CONFIG_SYS_PCIE3_MEM_BUS2, CONFIG_SYS_PCIE3_MEM_PHYS2, CONFIG_SYS_PCIE3_MEM_SIZE2, PCI_REGION_MEM); #endif hose->region_count = r - hose->regions; hose->first_busno=first_free_busno; pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data); fsl_pci_init(hose); first_free_busno=hose->last_busno+1; printf ("PCI on bus %02x - %02x\n", hose->first_busno,hose->last_busno); } else { printf (" PCI: disabled\n"); } } #else gur->devdisr |= MPC85xx_DEVDISR_PCI1; /* disable */ #endif }
/************************************************************************** * pci_init_board() * * NOTICE: PCI2 is not supported. There is only one * physical PCI slot on the board. * */ void pci_init_board(void) { volatile immap_t * immr; volatile clk83xx_t * clk; volatile law83xx_t * pci_law; volatile pot83xx_t * pci_pot; volatile pcictrl83xx_t * pci_ctrl; volatile pciconf83xx_t * pci_conf; u16 reg16; u32 reg32; u32 dev; struct pci_controller * hose; immr = (immap_t *)CONFIG_SYS_IMMR; clk = (clk83xx_t *)&immr->clk; pci_law = immr->sysconf.pcilaw; pci_pot = immr->ios.pot; pci_ctrl = immr->pci_ctrl; pci_conf = immr->pci_conf; hose = &pci_hose[0]; /* * Configure PCI controller and PCI_CLK_OUTPUT both in 66M mode */ reg32 = clk->occr; udelay(2000); clk->occr = 0xff000000; udelay(2000); /* * Release PCI RST Output signal */ pci_ctrl[0].gcr = 0; udelay(2000); pci_ctrl[0].gcr = 1; #ifdef CONFIG_MPC83XX_PCI2 pci_ctrl[1].gcr = 0; udelay(2000); pci_ctrl[1].gcr = 1; #endif /* We need to wait at least a 1sec based on PCI specs */ { int i; for (i = 0; i < 1000; ++i) udelay (1000); } /* * Configure PCI Local Access Windows */ pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR; pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_1G; pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR; pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_4M; /* * Configure PCI Outbound Translation Windows */ /* PCI1 mem space - prefetch */ pci_pot[0].potar = (CONFIG_SYS_PCI1_MEM_BASE >> 12) & POTAR_TA_MASK; pci_pot[0].pobar = (CONFIG_SYS_PCI1_MEM_PHYS >> 12) & POBAR_BA_MASK; pci_pot[0].pocmr = POCMR_EN | POCMR_PREFETCH_EN | (POCMR_CM_256M & POCMR_CM_MASK); /* PCI1 IO space */ pci_pot[1].potar = (CONFIG_SYS_PCI1_IO_BASE >> 12) & POTAR_TA_MASK; pci_pot[1].pobar = (CONFIG_SYS_PCI1_IO_PHYS >> 12) & POBAR_BA_MASK; pci_pot[1].pocmr = POCMR_EN | POCMR_IO | (POCMR_CM_1M & POCMR_CM_MASK); /* PCI1 mmio - non-prefetch mem space */ pci_pot[2].potar = (CONFIG_SYS_PCI1_MMIO_BASE >> 12) & POTAR_TA_MASK; pci_pot[2].pobar = (CONFIG_SYS_PCI1_MMIO_PHYS >> 12) & POBAR_BA_MASK; pci_pot[2].pocmr = POCMR_EN | (POCMR_CM_256M & POCMR_CM_MASK); /* * Configure PCI Inbound Translation Windows */ /* we need RAM mapped to PCI space for the devices to * access main memory */ pci_ctrl[0].pitar1 = 0x0; pci_ctrl[0].pibar1 = 0x0; pci_ctrl[0].piebar1 = 0x0; pci_ctrl[0].piwar1 = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP | PIWAR_WTT_SNOOP | (__ilog2(gd->ram_size) - 1); hose->first_busno = 0; hose->last_busno = 0xff; /* PCI memory prefetch space */ pci_set_region(hose->regions + 0, CONFIG_SYS_PCI1_MEM_BASE, CONFIG_SYS_PCI1_MEM_PHYS, CONFIG_SYS_PCI1_MEM_SIZE, PCI_REGION_MEM|PCI_REGION_PREFETCH); /* PCI memory space */ pci_set_region(hose->regions + 1, CONFIG_SYS_PCI1_MMIO_BASE, CONFIG_SYS_PCI1_MMIO_PHYS, CONFIG_SYS_PCI1_MMIO_SIZE, PCI_REGION_MEM); /* PCI IO space */ pci_set_region(hose->regions + 2, CONFIG_SYS_PCI1_IO_BASE, CONFIG_SYS_PCI1_IO_PHYS, CONFIG_SYS_PCI1_IO_SIZE, PCI_REGION_IO); /* System memory space */ pci_set_region(hose->regions + 3, CONFIG_PCI_SYS_MEM_BUS, CONFIG_PCI_SYS_MEM_PHYS, gd->ram_size, PCI_REGION_MEM | PCI_REGION_SYS_MEMORY); hose->region_count = 4; pci_setup_indirect(hose, (CONFIG_SYS_IMMR+0x8300), (CONFIG_SYS_IMMR+0x8304)); pci_register_hose(hose); /* * Write to Command register */ reg16 = 0xff; dev = PCI_BDF(hose->first_busno, 0, 0); pci_hose_read_config_word (hose, dev, PCI_COMMAND, ®16); reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; pci_hose_write_config_word(hose, dev, PCI_COMMAND, reg16); /* * Clear non-reserved bits in status register. */ pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff); pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80); pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08); #ifdef CONFIG_PCI_SCAN_SHOW printf("PCI: Bus Dev VenId DevId Class Int\n"); #endif /* * Hose scan. */ hose->last_busno = pci_hose_scan(hose); #ifdef CONFIG_MPC83XX_PCI2 hose = &pci_hose[1]; /* * Configure PCI Outbound Translation Windows */ /* PCI2 mem space - prefetch */ pci_pot[3].potar = (CONFIG_SYS_PCI2_MEM_BASE >> 12) & POTAR_TA_MASK; pci_pot[3].pobar = (CONFIG_SYS_PCI2_MEM_PHYS >> 12) & POBAR_BA_MASK; pci_pot[3].pocmr = POCMR_EN | POCMR_PCI2 | POCMR_PREFETCH_EN | (POCMR_CM_256M & POCMR_CM_MASK); /* PCI2 IO space */ pci_pot[4].potar = (CONFIG_SYS_PCI2_IO_BASE >> 12) & POTAR_TA_MASK; pci_pot[4].pobar = (CONFIG_SYS_PCI2_IO_PHYS >> 12) & POBAR_BA_MASK; pci_pot[4].pocmr = POCMR_EN | POCMR_PCI2 | POCMR_IO | (POCMR_CM_1M & POCMR_CM_MASK); /* PCI2 mmio - non-prefetch mem space */ pci_pot[5].potar = (CONFIG_SYS_PCI2_MMIO_BASE >> 12) & POTAR_TA_MASK; pci_pot[5].pobar = (CONFIG_SYS_PCI2_MMIO_PHYS >> 12) & POBAR_BA_MASK; pci_pot[5].pocmr = POCMR_EN | POCMR_PCI2 | (POCMR_CM_256M & POCMR_CM_MASK); /* * Configure PCI Inbound Translation Windows */ /* we need RAM mapped to PCI space for the devices to * access main memory */ pci_ctrl[1].pitar1 = 0x0; pci_ctrl[1].pibar1 = 0x0; pci_ctrl[1].piebar1 = 0x0; pci_ctrl[1].piwar1 = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP | PIWAR_WTT_SNOOP | (__ilog2(gd->ram_size) - 1); hose->first_busno = pci_hose[0].last_busno + 1; hose->last_busno = 0xff; /* PCI memory prefetch space */ pci_set_region(hose->regions + 0, CONFIG_SYS_PCI2_MEM_BASE, CONFIG_SYS_PCI2_MEM_PHYS, CONFIG_SYS_PCI2_MEM_SIZE, PCI_REGION_MEM|PCI_REGION_PREFETCH); /* PCI memory space */ pci_set_region(hose->regions + 1, CONFIG_SYS_PCI2_MMIO_BASE, CONFIG_SYS_PCI2_MMIO_PHYS, CONFIG_SYS_PCI2_MMIO_SIZE, PCI_REGION_MEM); /* PCI IO space */ pci_set_region(hose->regions + 2, CONFIG_SYS_PCI2_IO_BASE, CONFIG_SYS_PCI2_IO_PHYS, CONFIG_SYS_PCI2_IO_SIZE, PCI_REGION_IO); /* System memory space */ pci_set_region(hose->regions + 3, CONFIG_PCI_SYS_MEM_BUS, CONFIG_PCI_SYS_MEM_PHYS, gd->ram_size, PCI_REGION_MEM | PCI_REGION_SYS_MEMORY); hose->region_count = 4; pci_setup_indirect(hose, (CONFIG_SYS_IMMR+0x8380), (CONFIG_SYS_IMMR+0x8384)); pci_register_hose(hose); /* * Write to Command register */ reg16 = 0xff; dev = PCI_BDF(hose->first_busno, 0, 0); pci_hose_read_config_word (hose, dev, PCI_COMMAND, ®16); reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; pci_hose_write_config_word(hose, dev, PCI_COMMAND, reg16); /* * Clear non-reserved bits in status register. */ pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff); pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80); pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08); /* * Hose scan. */ hose->last_busno = pci_hose_scan(hose); #endif }
void pcie_setup_hoses(int busno) { struct pci_controller *hose; int i, bus; char *env; unsigned int delay; /* * assume we're called after the PCIX hose is initialized, which takes * bus ID 0 and therefore start numbering PCIe's from 1. */ bus = busno; for (i = 0; i <= 2; i++) { /* Check for yucca card presence */ if (!yucca_pcie_card_present(i)) continue; #ifdef PCIE_ENDPOINT yucca_setup_pcie_fpga_endpoint(i); if (ppc440spe_init_pcie_endport(i)) { #else yucca_setup_pcie_fpga_rootpoint(i); if (ppc440spe_init_pcie_rootport(i)) { #endif printf("PCIE%d: initialization failed\n", i); continue; } hose = &pcie_hose[i]; hose->first_busno = bus; hose->last_busno = bus; hose->current_busno = bus; /* setup mem resource */ pci_set_region(hose->regions + 0, CFG_PCIE_MEMBASE + i * CFG_PCIE_MEMSIZE, CFG_PCIE_MEMBASE + i * CFG_PCIE_MEMSIZE, CFG_PCIE_MEMSIZE, PCI_REGION_MEM ); hose->region_count = 1; pci_register_hose(hose); #ifdef PCIE_ENDPOINT ppc440spe_setup_pcie_endpoint(hose, i); /* * Reson for no scanning is endpoint can not generate * upstream configuration accesses. */ #else ppc440spe_setup_pcie_rootpoint(hose, i); env = getenv ("pciscandelay"); if (env != NULL) { delay = simple_strtoul (env, NULL, 10); if (delay > 5) printf ("Warning, expect noticable delay before PCIe" "scan due to 'pciscandelay' value!\n"); mdelay (delay * 1000); } /* * Config access can only go down stream */ hose->last_busno = pci_hose_scan(hose); bus = hose->last_busno + 1; #endif } } #endif /* defined(CONFIG_PCI) */ int misc_init_f (void) { uint reg; #if defined(CONFIG_STRESS) uint i ; uint disp; #endif out16(FPGA_REG10, (in16(FPGA_REG10) & ~(FPGA_REG10_AUTO_NEG_DIS|FPGA_REG10_RESET_ETH)) | FPGA_REG10_10MHZ_ENABLE | FPGA_REG10_100MHZ_ENABLE | FPGA_REG10_GIGABIT_ENABLE | FPGA_REG10_FULL_DUPLEX ); udelay(10000); /* wait 10ms */ out16(FPGA_REG10, (in16(FPGA_REG10) | FPGA_REG10_RESET_ETH)); /* minimal init for PCIe */ /* pci express 0 Endpoint Mode */ mfsdr(SDR0_PE0DLPSET, reg); reg &= (~0x00400000); mtsdr(SDR0_PE0DLPSET, reg); /* pci express 1 Rootpoint Mode */ mfsdr(SDR0_PE1DLPSET, reg); reg |= 0x00400000; mtsdr(SDR0_PE1DLPSET, reg); /* pci express 2 Rootpoint Mode */ mfsdr(SDR0_PE2DLPSET, reg); reg |= 0x00400000; mtsdr(SDR0_PE2DLPSET, reg); out16(FPGA_REG1C,(in16 (FPGA_REG1C) & ~FPGA_REG1C_PE0_ROOTPOINT & ~FPGA_REG1C_PE1_ENDPOINT & ~FPGA_REG1C_PE2_ENDPOINT)); #if defined(CONFIG_STRESS) /* * all this setting done by linux only needed by stress an charac. test * procedure * PCIe 1 Rootpoint PCIe2 Endpoint * PCIe 0 FIR Pre-emphasis Filter Coefficients & Transmit Driver * Power Level */ for (i = 0, disp = 0; i < 8; i++, disp += 3) { mfsdr(SDR0_PE0HSSSET1L0 + disp, reg); reg |= 0x33000000; mtsdr(SDR0_PE0HSSSET1L0 + disp, reg); } /* * PCIe 1 FIR Pre-emphasis Filter Coefficients & Transmit Driver * Power Level */ for (i = 0, disp = 0; i < 4; i++, disp += 3) { mfsdr(SDR0_PE1HSSSET1L0 + disp, reg); reg |= 0x33000000; mtsdr(SDR0_PE1HSSSET1L0 + disp, reg); } /* * PCIE 2 FIR Pre-emphasis Filter Coefficients & Transmit Driver * Power Level */ for (i = 0, disp = 0; i < 4; i++, disp += 3) { mfsdr(SDR0_PE2HSSSET1L0 + disp, reg); reg |= 0x33000000; mtsdr(SDR0_PE2HSSSET1L0 + disp, reg); } reg = 0x21242222; mtsdr(SDR0_PE2UTLSET1, reg); reg = 0x11000000; mtsdr(SDR0_PE2UTLSET2, reg); /* pci express 1 Endpoint Mode */ reg = 0x00004000; mtsdr(SDR0_PE2DLPSET, reg); mtsdr(SDR0_UART1, 0x2080005a); /* patch for TG */ #endif return 0; }
void pci_init_board(void) { int mem_target, mem_attr, i; int bus = 0; u32 reg; u32 soc_ctrl = readl(MVEBU_SYSTEM_REG_BASE + 0x4); /* Check SoC Control Power State */ debug("%s: SoC Control %08x, 0en %01lx, 1en %01lx, 2en %01lx\n", __func__, soc_ctrl, SELECT(soc_ctrl, 0), SELECT(soc_ctrl, 1), SELECT(soc_ctrl, 2)); for (i = 0; i < MAX_PEX; i++) { struct mvebu_pcie *pcie = &pcie_bus[i]; struct pci_controller *hose = &pcie->hose; /* Get port number, lane number and memory target / attr */ mvebu_get_port_lane(pcie, i, &mem_target, &mem_attr); /* Don't read at all from pci registers if port power is down */ if (pcie->lane == 0 && SELECT(soc_ctrl, pcie->port) == 0) { i += 3; debug("%s: skipping port %d\n", __func__, pcie->port); continue; } pcie->base = (void __iomem *)PCIE_BASE(i); /* Check link and skip ports that have no link */ if (!mvebu_pcie_link_up(pcie)) { debug("%s: PCIe %d.%d - down\n", __func__, pcie->port, pcie->lane); continue; } debug("%s: PCIe %d.%d - up, base %08x\n", __func__, pcie->port, pcie->lane, (u32)pcie->base); /* Read Id info and local bus/dev */ debug("direct conf read %08x, local bus %d, local dev %d\n", readl(pcie->base), mvebu_pcie_get_local_bus_nr(pcie), mvebu_pcie_get_local_dev_nr(pcie)); mvebu_pcie_set_local_bus_nr(pcie, bus); mvebu_pcie_set_local_dev_nr(pcie, 0); pcie->dev = PCI_BDF(bus, 0, 0); pcie->mem.start = (u32)mvebu_pcie_membase; pcie->mem.end = pcie->mem.start + PCIE_MEM_SIZE - 1; mvebu_pcie_membase += PCIE_MEM_SIZE; if (mvebu_mbus_add_window_by_id(mem_target, mem_attr, (phys_addr_t)pcie->mem.start, PCIE_MEM_SIZE)) { printf("PCIe unable to add mbus window for mem at %08x+%08x\n", (u32)pcie->mem.start, PCIE_MEM_SIZE); } /* Setup windows and configure host bridge */ mvebu_pcie_setup_wins(pcie); /* Master + slave enable. */ reg = readl(pcie->base + PCIE_CMD_OFF); reg |= PCI_COMMAND_MEMORY; reg |= PCI_COMMAND_MASTER; reg |= BIT(10); /* disable interrupts */ writel(reg, pcie->base + PCIE_CMD_OFF); /* Setup U-Boot PCI Controller */ hose->first_busno = 0; hose->current_busno = bus; /* PCI memory space */ pci_set_region(hose->regions + 0, pcie->mem.start, pcie->mem.start, PCIE_MEM_SIZE, PCI_REGION_MEM); pci_set_region(hose->regions + 1, 0, 0, gd->ram_size, PCI_REGION_MEM | PCI_REGION_SYS_MEMORY); hose->region_count = 2; pci_set_ops(hose, pci_hose_read_config_byte_via_dword, pci_hose_read_config_word_via_dword, mvebu_pcie_read_config_dword, pci_hose_write_config_byte_via_dword, pci_hose_write_config_word_via_dword, mvebu_pcie_write_config_dword); pci_register_hose(hose); hose->last_busno = pci_hose_scan(hose); /* Set BAR0 to internal registers */ writel(SOC_REGS_PHY_BASE, pcie->base + PCIE_BAR_LO_OFF(0)); writel(0, pcie->base + PCIE_BAR_HI_OFF(0)); bus = hose->last_busno + 1; } }
void pci_mcf5445x_init(struct pci_controller *hose) { pci_t *pci = (pci_t *)MMAP_PCI; pciarb_t *pciarb = (pciarb_t *)MMAP_PCIARB; gpio_t *gpio = (gpio_t *) MMAP_GPIO; u32 barEn = 0; out_be32(&pciarb->acr, 0x001f001f); /* Set PCIGNT1, PCIREQ1, PCIREQ0/PCIGNTIN, PCIGNT0/PCIREQOUT, PCIREQ2, PCIGNT2 */ out_be16(&gpio->par_pci, GPIO_PAR_PCI_GNT3_GNT3 | GPIO_PAR_PCI_GNT2 | GPIO_PAR_PCI_GNT1 | GPIO_PAR_PCI_GNT0 | GPIO_PAR_PCI_REQ3_REQ3 | GPIO_PAR_PCI_REQ2 | GPIO_PAR_PCI_REQ1 | GPIO_PAR_PCI_REQ0); /* Assert reset bit */ setbits_be32(&pci->gscr, PCI_GSCR_PR); setbits_be32(&pci->tcr1, PCI_TCR1_P); /* Initiator windows */ out_be32(&pci->iw0btar, CONFIG_SYS_PCI_MEM_PHYS | (CONFIG_SYS_PCI_MEM_PHYS >> 16)); out_be32(&pci->iw1btar, CONFIG_SYS_PCI_IO_PHYS | (CONFIG_SYS_PCI_IO_PHYS >> 16)); out_be32(&pci->iw2btar, CONFIG_SYS_PCI_CFG_PHYS | (CONFIG_SYS_PCI_CFG_PHYS >> 16)); out_be32(&pci->iwcr, PCI_IWCR_W0C_EN | PCI_IWCR_W1C_EN | PCI_IWCR_W1C_IO | PCI_IWCR_W2C_EN | PCI_IWCR_W2C_IO); out_be32(&pci->icr, 0); /* Enable bus master and mem access */ out_be32(&pci->scr, PCI_SCR_B | PCI_SCR_M); /* Cache line size and master latency */ out_be32(&pci->cr1, PCI_CR1_CLS(8) | PCI_CR1_LTMR(0xF8)); out_be32(&pci->cr2, 0); #ifdef CONFIG_SYS_PCI_BAR0 out_be32(&pci->bar0, PCI_BAR_BAR0(CONFIG_SYS_PCI_BAR0)); out_be32(&pci->tbatr0, CONFIG_SYS_PCI_TBATR0 | PCI_TBATR_EN); barEn |= PCI_TCR2_B0E; #endif #ifdef CONFIG_SYS_PCI_BAR1 out_be32(&pci->bar1, PCI_BAR_BAR1(CONFIG_SYS_PCI_BAR1)); out_be32(&pci->tbatr1, CONFIG_SYS_PCI_TBATR1 | PCI_TBATR_EN); barEn |= PCI_TCR2_B1E; #endif #ifdef CONFIG_SYS_PCI_BAR2 out_be32(&pci->bar2, PCI_BAR_BAR2(CONFIG_SYS_PCI_BAR2)); out_be32(&pci->tbatr2, CONFIG_SYS_PCI_TBATR2 | PCI_TBATR_EN); barEn |= PCI_TCR2_B2E; #endif #ifdef CONFIG_SYS_PCI_BAR3 out_be32(&pci->bar3, PCI_BAR_BAR3(CONFIG_SYS_PCI_BAR3)); out_be32(&pci->tbatr3, CONFIG_SYS_PCI_TBATR3 | PCI_TBATR_EN); barEn |= PCI_TCR2_B3E; #endif #ifdef CONFIG_SYS_PCI_BAR4 out_be32(&pci->bar4, PCI_BAR_BAR4(CONFIG_SYS_PCI_BAR4)); out_be32(&pci->tbatr4, CONFIG_SYS_PCI_TBATR4 | PCI_TBATR_EN); barEn |= PCI_TCR2_B4E; #endif #ifdef CONFIG_SYS_PCI_BAR5 out_be32(&pci->bar5, PCI_BAR_BAR5(CONFIG_SYS_PCI_BAR5)); out_be32(&pci->tbatr5, CONFIG_SYS_PCI_TBATR5 | PCI_TBATR_EN); barEn |= PCI_TCR2_B5E; #endif out_be32(&pci->tcr2, barEn); /* Deassert reset bit */ clrbits_be32(&pci->gscr, PCI_GSCR_PR); udelay(1000); /* Enable PCI bus master support */ hose->first_busno = 0; hose->last_busno = 0xff; pci_set_region(hose->regions + 0, CONFIG_SYS_PCI_MEM_BUS, CONFIG_SYS_PCI_MEM_PHYS, CONFIG_SYS_PCI_MEM_SIZE, PCI_REGION_MEM); pci_set_region(hose->regions + 1, CONFIG_SYS_PCI_IO_BUS, CONFIG_SYS_PCI_IO_PHYS, CONFIG_SYS_PCI_IO_SIZE, PCI_REGION_IO); pci_set_region(hose->regions + 2, CONFIG_SYS_PCI_SYS_MEM_BUS, CONFIG_SYS_PCI_SYS_MEM_PHYS, CONFIG_SYS_PCI_SYS_MEM_SIZE, PCI_REGION_MEM | PCI_REGION_SYS_MEMORY); hose->region_count = 3; hose->cfg_addr = &(pci->car); hose->cfg_data = (volatile unsigned char *)CONFIG_SYS_PCI_CFG_BUS; pci_set_ops(hose, pci_read_cfg_byte, pci_read_cfg_word, pci_read_cfg_dword, pci_write_cfg_byte, pci_write_cfg_word, pci_write_cfg_dword); /* Hose scan */ pci_register_hose(hose); hose->last_busno = pci_hose_scan(hose); }
void pci_init_board(void) { struct pci_controller* hose = (struct pci_controller *)&local_hose; u32 reg32; u16 reg16; hose->first_busno = 0; hose->last_busno = 0xff; pci_set_region(hose->regions + 0, CFG_PCI_MEMORY_BUS, CFG_PCI_MEMORY_PHYS, /* * Attention: pci_hose_phys_to_bus() failes in address compare, * so we need (CFG_PCI_MEMORY_SIZE-1) */ CFG_PCI_MEMORY_SIZE-1, PCI_REGION_MEM | PCI_REGION_MEMORY); /* PCI memory space */ pci_set_region(hose->regions + 1, CFG_PCI_MEM_BUS, CFG_PCI_MEM_PHYS, CFG_PCI_MEM_SIZE, PCI_REGION_MEM); /* ISA/PCI memory space */ pci_set_region(hose->regions + 2, CFG_ISA_MEM_BUS, CFG_ISA_MEM_PHYS, CFG_ISA_MEM_SIZE, PCI_REGION_MEM); /* PCI I/O space */ pci_set_region(hose->regions + 3, CFG_PCI_IO_BUS, CFG_PCI_IO_PHYS, CFG_PCI_IO_SIZE, PCI_REGION_IO); /* ISA/PCI I/O space */ pci_set_region(hose->regions + 4, CFG_ISA_IO_BUS, CFG_ISA_IO_PHYS, CFG_ISA_IO_SIZE, PCI_REGION_IO); hose->region_count = 5; pci_setup_indirect(hose, MPC106_REG_ADDR, MPC106_REG_DATA); pci_register_hose(hose); hose->last_busno = pci_hose_scan(hose); /* Initialises the MPC10x PCI Configuration regs. */ pci_read_config_dword (PCI_BDF(0,0,0), PCI_PICR2, ®32); reg32 |= PICR2_CF_SNOOP_WS(3) | PICR2_CF_FLUSH_L2 | PICR2_CF_L2_HIT_DELAY(3) | PICR2_CF_APHASE_WS(3); reg32 &= ~(PICR2_L2_EN | PICR2_L2_UPDATE_EN); pci_write_config_dword (PCI_BDF(0,0,0), PCI_PICR2, reg32); pci_read_config_word (PCI_BDF(0,0,0), PCI_COMMAND, ®16); reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; pci_write_config_word(PCI_BDF(0,0,0), PCI_COMMAND, reg16); /* Clear non-reserved bits in status register */ pci_write_config_word(PCI_BDF(0,0,0), PCI_STATUS, 0xffff); pci_read_config_dword (PCI_BDF(0,0,0), PCI_PICR1, ®32); reg32 |= PICR1_CF_CBA(63) | PICR1_CF_BREAD_WS(2) | PICR1_MCP_EN | PICR1_CF_DPARK | PICR1_PROC_TYPE_604 | PICR1_CF_LOOP_SNOOP | PICR1_CF_APARK; pci_write_config_dword (PCI_BDF(0,0,0), PCI_PICR1, reg32); }
void pci_init_board(void) { volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); uint devdisr = gur->devdisr; uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19; uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16; debug (" pci_init_board: devdisr=%x, io_sel=%x, host_agent=%x\n", devdisr, io_sel, host_agent); /* explicitly set 'Clock out select register' to echo SYSCLK input to our CPLD */ gur->clkocr |= MPC85xx_ATUM_CLKOCR; if (io_sel & 1) { if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII1_DIS)) printf (" eTSEC1 is in sgmii mode.\n"); if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII2_DIS)) printf (" eTSEC2 is in sgmii mode.\n"); if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS)) printf (" eTSEC3 is in sgmii mode.\n"); if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII4_DIS)) printf (" eTSEC4 is in sgmii mode.\n"); } #ifdef CONFIG_PCIE1 { volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR; struct pci_controller *hose = &pcie1_hose; int pcie_ep = (host_agent == 5); int pcie_configured = io_sel & 6; struct pci_region *r = hose->regions; if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){ printf ("\n PCIE1 connected to slot as %s (base address %x)", pcie_ep ? "End Point" : "Root Complex", (uint)pci); if (pci->pme_msg_det) { pci->pme_msg_det = 0xffffffff; debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det); } printf ("\n"); /* inbound */ r += fsl_pci_setup_inbound_windows(r); /* outbound memory */ pci_set_region(r++, CONFIG_SYS_PCIE1_MEM_BASE, CONFIG_SYS_PCIE1_MEM_PHYS, CONFIG_SYS_PCIE1_MEM_SIZE, PCI_REGION_MEM); /* outbound io */ pci_set_region(r++, CONFIG_SYS_PCIE1_IO_BASE, CONFIG_SYS_PCIE1_IO_PHYS, CONFIG_SYS_PCIE1_IO_SIZE, PCI_REGION_IO); #ifdef CONFIG_SYS_PCIE1_MEM_BASE2 /* outbound memory */ pci_set_region(r++, CONFIG_SYS_PCIE1_MEM_BASE2, CONFIG_SYS_PCIE1_MEM_PHYS2, CONFIG_SYS_PCIE1_MEM_SIZE2, PCI_REGION_MEM); #endif hose->region_count = r - hose->regions; hose->first_busno=first_free_busno; pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data); fsl_pci_init(hose); first_free_busno=hose->last_busno+1; printf(" PCIE1 on bus %02x - %02x\n", hose->first_busno,hose->last_busno); } else { printf (" PCIE1: disabled\n"); } } #else gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */ #endif #ifdef CONFIG_PCI1 { volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI1_ADDR; struct pci_controller *hose = &pci1_hose; struct pci_region *r = hose->regions; uint pci_agent = (host_agent == 6); uint pci_speed = 33333000; /*get_clock_freq (); PCI PSPEED in [4:5] */ uint pci_32 = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_PCI32; /* PORDEVSR[15] */ uint pci_arb = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; /* PORDEVSR[14] */ uint pci_clk_sel = gur->porpllsr & MPC85xx_PORDEVSR_PCI1_SPD; /* PORPLLSR[16] */ if (!(devdisr & MPC85xx_DEVDISR_PCI1)) { printf ("\n PCI1: %d bit, %s MHz, %s, %s, %s (base address %x)\n", (pci_32) ? 32 : 64, (pci_speed == 33333000) ? "33" : (pci_speed == 66666000) ? "66" : "unknown", pci_clk_sel ? "sync" : "async", pci_agent ? "agent" : "host", pci_arb ? "arbiter" : "external-arbiter", (uint)pci ); /* inbound */ r += fsl_pci_setup_inbound_windows(r); /* outbound memory */ pci_set_region(r++, CONFIG_SYS_PCI1_MEM_BASE, CONFIG_SYS_PCI1_MEM_PHYS, CONFIG_SYS_PCI1_MEM_SIZE, PCI_REGION_MEM); /* outbound io */ pci_set_region(r++, CONFIG_SYS_PCI1_IO_BASE, CONFIG_SYS_PCI1_IO_PHYS, CONFIG_SYS_PCI1_IO_SIZE, PCI_REGION_IO); hose->region_count = r - hose->regions; hose->first_busno=first_free_busno; pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data); fsl_pci_init(hose); first_free_busno=hose->last_busno+1; printf ("PCI1 on bus %02x - %02x\n", hose->first_busno,hose->last_busno); } else { printf (" PCI1: disabled\n"); } } #else gur->devdisr |= MPC85xx_DEVDISR_PCI1; /* disable */ #endif #ifdef CONFIG_PCI2 { volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI2_ADDR; struct pci_controller *hose = &pci2_hose; struct pci_region *r = hose->regions; if (!(devdisr & MPC85xx_DEVDISR_PCI2)) { r += fsl_pci_setup_inbound_windows(r); pci_set_region(r++, CONFIG_SYS_PCI2_MEM_BASE, CONFIG_SYS_PCI2_MEM_PHYS, CONFIG_SYS_PCI2_MEM_SIZE, PCI_REGION_MEM); pci_set_region(r++, CONFIG_SYS_PCI2_IO_BASE, CONFIG_SYS_PCI2_IO_PHYS, CONFIG_SYS_PCI2_IO_SIZE, PCI_REGION_IO); hose->region_count = r - hose->regions; hose->first_busno=first_free_busno; pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data); fsl_pci_init(hose); first_free_busno=hose->last_busno+1; printf ("PCI2 on bus %02x - %02x\n", hose->first_busno,hose->last_busno); } else { printf (" PCI2: disabled\n"); } } #else gur->devdisr |= MPC85xx_DEVDISR_PCI2; #endif }
void pcie_setup_hoses(int busno) { struct pci_controller *hose; int i, bus; int ret = 0; char *env; unsigned int delay; /* * assume we're called after the PCIX hose is initialized, which takes * bus ID 0 and therefore start numbering PCIe's from 1. */ bus = busno; for (i = 0; i <= 2; i++) { /* Check for katmai card presence */ if (!katmai_pcie_card_present(i)) continue; if (is_end_point(i)) ret = ppc4xx_init_pcie_endport(i); else ret = ppc4xx_init_pcie_rootport(i); if (ret) { printf("PCIE%d: initialization as %s failed\n", i, is_end_point(i) ? "endpoint" : "root-complex"); continue; } hose = &pcie_hose[i]; hose->first_busno = bus; hose->last_busno = bus; hose->current_busno = bus; /* setup mem resource */ pci_set_region(hose->regions + 0, CONFIG_SYS_PCIE_MEMBASE + i * CONFIG_SYS_PCIE_MEMSIZE, CONFIG_SYS_PCIE_MEMBASE + i * CONFIG_SYS_PCIE_MEMSIZE, CONFIG_SYS_PCIE_MEMSIZE, PCI_REGION_MEM); hose->region_count = 1; pci_register_hose(hose); if (is_end_point(i)) { ppc4xx_setup_pcie_endpoint(hose, i); /* * Reson for no scanning is endpoint can not generate * upstream configuration accesses. */ } else { ppc4xx_setup_pcie_rootpoint(hose, i); env = getenv ("pciscandelay"); if (env != NULL) { delay = simple_strtoul(env, NULL, 10); if (delay > 5) printf("Warning, expect noticable delay before " "PCIe scan due to 'pciscandelay' value!\n"); mdelay(delay * 1000); } /* * Config access can only go down stream */ hose->last_busno = pci_hose_scan(hose); bus = hose->last_busno + 1; } } }
void pci_mpc8250_init (struct pci_controller *hose) { u16 tempShort; volatile immap_t *immap = (immap_t *) CFG_IMMR; pci_dev_t host_devno = PCI_BDF (0, 0, 0); pci_setup_indirect (hose, CFG_IMMR + PCI_CFG_ADDR_REG, CFG_IMMR + PCI_CFG_DATA_REG); /* * Setting required to enable local bus for PCI (SIUMCR [LBPC]). */ #ifdef CONFIG_MPC8266ADS immap->im_siu_conf.sc_siumcr = (immap->im_siu_conf.sc_siumcr & ~SIUMCR_LBPC11) | SIUMCR_LBPC01; #elif defined CONFIG_MPC8272 immap->im_siu_conf.sc_siumcr = (immap->im_siu_conf.sc_siumcr & ~SIUMCR_BBD & ~SIUMCR_ESE & ~SIUMCR_PBSE & ~SIUMCR_CDIS & ~SIUMCR_DPPC11 & ~SIUMCR_L2CPC11 & ~SIUMCR_LBPC11 & ~SIUMCR_APPC11 & ~SIUMCR_CS10PC11 & ~SIUMCR_BCTLC11 & ~SIUMCR_MMR11) | SIUMCR_DPPC11 | SIUMCR_L2CPC01 | SIUMCR_LBPC00 | SIUMCR_APPC10 | SIUMCR_CS10PC00 | SIUMCR_BCTLC00 | SIUMCR_MMR11; #elif defined(CONFIG_TQM8272) /* nothing to do for this Board here */ #else /* * Setting required to enable IRQ1-IRQ7 (SIUMCR [DPPC]), * and local bus for PCI (SIUMCR [LBPC]). */ immap->im_siu_conf.sc_siumcr = (immap->im_siu_conf.sc_siumcr & ~SIUMCR_LBPC11 & ~SIUMCR_CS10PC11 & ~SIUMCR_LBPC11) | SIUMCR_LBPC01 | SIUMCR_CS10PC01 | SIUMCR_APPC10; #endif /* Make PCI lowest priority */ /* Each 4 bits is a device bus request and the MS 4bits is highest priority */ /* Bus 4bit value --- ---------- CPM high 0b0000 CPM middle 0b0001 CPM low 0b0010 PCI reguest 0b0011 Reserved 0b0100 Reserved 0b0101 Internal Core 0b0110 External Master 1 0b0111 External Master 2 0b1000 External Master 3 0b1001 The rest are reserved */ immap->im_siu_conf.sc_ppc_alrh = 0x61207893; /* Park bus on core while modifying PCI Bus accesses */ immap->im_siu_conf.sc_ppc_acr = 0x6; /* * Set up master windows that allow the CPU to access PCI space. These * windows are set up using the two SIU PCIBR registers. */ immap->im_memctl.memc_pcimsk0 = PCIMSK0_MASK; immap->im_memctl.memc_pcibr0 = PCI_MSTR0_LOCAL | PCIBR_ENABLE; #if defined CONFIG_MPC8266ADS || defined CONFIG_MPC8272 immap->im_memctl.memc_pcimsk1 = PCIMSK1_MASK; immap->im_memctl.memc_pcibr1 = PCI_MSTR1_LOCAL | PCIBR_ENABLE; #endif /* Release PCI RST (by default the PCI RST signal is held low) */ immap->im_pci.pci_gcr = cpu_to_le32 (PCIGCR_PCI_BUS_EN); /* give it some time */ { #if defined CONFIG_MPC8266ADS || defined CONFIG_MPC8272 /* Give the PCI cards more time to initialize before query This might be good for other boards also */ int i; for (i = 0; i < 1000; ++i) #endif udelay (1000); } /* * Set up master window that allows the CPU to access PCI Memory (prefetch) * space. This window is set up using the first set of Outbound ATU registers. */ immap->im_pci.pci_potar0 = cpu_to_le32 (PCI_MSTR_MEM_BUS >> 12); /* PCI base */ immap->im_pci.pci_pobar0 = cpu_to_le32 (PCI_MSTR_MEM_LOCAL >> 12); /* Local base */ immap->im_pci.pci_pocmr0 = cpu_to_le32 (POCMR0_MASK_ATTRIB); /* Size & attribute */ /* * Set up master window that allows the CPU to access PCI Memory (non-prefetch) * space. This window is set up using the second set of Outbound ATU registers. */ immap->im_pci.pci_potar1 = cpu_to_le32 (PCI_MSTR_MEMIO_BUS >> 12); /* PCI base */ immap->im_pci.pci_pobar1 = cpu_to_le32 (PCI_MSTR_MEMIO_LOCAL >> 12); /* Local base */ immap->im_pci.pci_pocmr1 = cpu_to_le32 (POCMR1_MASK_ATTRIB); /* Size & attribute */ /* * Set up master window that allows the CPU to access PCI IO space. This window * is set up using the third set of Outbound ATU registers. */ immap->im_pci.pci_potar2 = cpu_to_le32 (PCI_MSTR_IO_BUS >> 12); /* PCI base */ immap->im_pci.pci_pobar2 = cpu_to_le32 (PCI_MSTR_IO_LOCAL >> 12); /* Local base */ immap->im_pci.pci_pocmr2 = cpu_to_le32 (POCMR2_MASK_ATTRIB); /* Size & attribute */ /* * Set up slave window that allows PCI masters to access MPC826x local memory. * This window is set up using the first set of Inbound ATU registers */ immap->im_pci.pci_pitar0 = cpu_to_le32 (PCI_SLV_MEM_LOCAL >> 12); /* PCI base */ immap->im_pci.pci_pibar0 = cpu_to_le32 (PCI_SLV_MEM_BUS >> 12); /* Local base */ immap->im_pci.pci_picmr0 = cpu_to_le32 (PICMR0_MASK_ATTRIB); /* Size & attribute */ /* See above for description - puts PCI request as highest priority */ #ifdef CONFIG_MPC8272 immap->im_siu_conf.sc_ppc_alrh = 0x01236745; #else immap->im_siu_conf.sc_ppc_alrh = 0x03124567; #endif /* Park the bus on the PCI */ immap->im_siu_conf.sc_ppc_acr = PPC_ACR_BUS_PARK_PCI; /* Host mode - specify the bridge as a host-PCI bridge */ pci_hose_write_config_byte (hose, host_devno, PCI_CLASS_CODE, PCI_CLASS_BRIDGE_CTLR); /* Enable the host bridge to be a master on the PCI bus, and to act as a PCI memory target */ pci_hose_read_config_word (hose, host_devno, PCI_COMMAND, &tempShort); pci_hose_write_config_word (hose, host_devno, PCI_COMMAND, tempShort | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); /* do some bridge init, should be done on all 8260 based bridges */ pci_hose_write_config_byte (hose, host_devno, PCI_CACHE_LINE_SIZE, 0x08); pci_hose_write_config_byte (hose, host_devno, PCI_LATENCY_TIMER, 0xF8); hose->first_busno = 0; hose->last_busno = 0xff; /* System memory space */ #if defined CONFIG_MPC8266ADS || defined CONFIG_MPC8272 || defined CONFIG_PM826 pci_set_region (hose->regions + 0, PCI_SLV_MEM_BUS, PCI_SLV_MEM_LOCAL, gd->ram_size, PCI_REGION_MEM | PCI_REGION_MEMORY); #else pci_set_region (hose->regions + 0, CFG_SDRAM_BASE, CFG_SDRAM_BASE, 0x4000000, PCI_REGION_MEM | PCI_REGION_MEMORY); #endif /* PCI memory space */ #if defined CONFIG_MPC8266ADS || defined CONFIG_MPC8272 pci_set_region (hose->regions + 1, PCI_MSTR_MEMIO_BUS, PCI_MSTR_MEMIO_LOCAL, PCI_MSTR_MEMIO_SIZE, PCI_REGION_MEM); #else pci_set_region (hose->regions + 1, PCI_MSTR_MEM_BUS, PCI_MSTR_MEM_LOCAL, PCI_MSTR_MEM_SIZE, PCI_REGION_MEM); #endif /* PCI I/O space */ pci_set_region (hose->regions + 2, PCI_MSTR_IO_BUS, PCI_MSTR_IO_LOCAL, PCI_MSTR_IO_SIZE, PCI_REGION_IO); hose->region_count = 3; pci_register_hose (hose); /* Mask off master abort machine checks */ immap->im_pci.pci_emr &= cpu_to_le32 (~PCI_ERROR_PCI_NO_RSP); eieio (); hose->last_busno = pci_hose_scan (hose); /* clear the error in the error status register */ immap->im_pci.pci_esr = cpu_to_le32 (PCI_ERROR_PCI_NO_RSP); /* unmask master abort machine checks */ immap->im_pci.pci_emr |= cpu_to_le32 (PCI_ERROR_PCI_NO_RSP); }
static int fsl_pci_setup_inbound_windows(struct pci_controller *hose, u64 out_lo, u8 pcie_cap, volatile pit_t *pi) { struct pci_region *r = hose->regions + hose->region_count; u64 sz = min((u64)gd->ram_size, (1ull << 32)); phys_addr_t phys_start = CONFIG_SYS_PCI_MEMORY_PHYS; pci_addr_t bus_start = CONFIG_SYS_PCI_MEMORY_BUS; pci_size_t pci_sz; /* we have no space available for inbound memory mapping */ if (bus_start > out_lo) { printf ("no space for inbound mapping of memory\n"); return 0; } /* limit size */ if ((bus_start + sz) > out_lo) { sz = out_lo - bus_start; debug ("limiting size to %llx\n", sz); } pci_sz = 1ull << __ilog2_u64(sz); /* * we can overlap inbound/outbound windows on PCI-E since RX & TX * links a separate */ if ((pcie_cap == PCI_CAP_ID_EXP) && (pci_sz < sz)) { debug ("R0 bus_start: %llx phys_start: %llx size: %llx\n", (u64)bus_start, (u64)phys_start, (u64)sz); pci_set_region(r, bus_start, phys_start, sz, PCI_REGION_MEM | PCI_REGION_SYS_MEMORY | PCI_REGION_PREFETCH); /* if we aren't an exact power of two match, pci_sz is smaller * round it up to the next power of two. We report the actual * size to pci region tracking. */ if (pci_sz != sz) sz = 2ull << __ilog2_u64(sz); set_inbound_window(pi--, r++, sz); sz = 0; /* make sure we dont set the R2 window */ } else { debug ("R0 bus_start: %llx phys_start: %llx size: %llx\n", (u64)bus_start, (u64)phys_start, (u64)pci_sz); pci_set_region(r, bus_start, phys_start, pci_sz, PCI_REGION_MEM | PCI_REGION_SYS_MEMORY | PCI_REGION_PREFETCH); set_inbound_window(pi--, r++, pci_sz); sz -= pci_sz; bus_start += pci_sz; phys_start += pci_sz; pci_sz = 1ull << __ilog2_u64(sz); if (sz) { debug ("R1 bus_start: %llx phys_start: %llx size: %llx\n", (u64)bus_start, (u64)phys_start, (u64)pci_sz); pci_set_region(r, bus_start, phys_start, pci_sz, PCI_REGION_MEM | PCI_REGION_SYS_MEMORY | PCI_REGION_PREFETCH); set_inbound_window(pi--, r++, pci_sz); sz -= pci_sz; bus_start += pci_sz; phys_start += pci_sz; } } #if defined(CONFIG_PHYS_64BIT) && defined(CONFIG_SYS_PCI_64BIT) /* * On 64-bit capable systems, set up a mapping for all of DRAM * in high pci address space. */ pci_sz = 1ull << __ilog2_u64(gd->ram_size); /* round up to the next largest power of two */ if (gd->ram_size > pci_sz) pci_sz = 1ull << (__ilog2_u64(gd->ram_size) + 1); debug ("R64 bus_start: %llx phys_start: %llx size: %llx\n", (u64)CONFIG_SYS_PCI64_MEMORY_BUS, (u64)CONFIG_SYS_PCI_MEMORY_PHYS, (u64)pci_sz); pci_set_region(r, CONFIG_SYS_PCI64_MEMORY_BUS, CONFIG_SYS_PCI_MEMORY_PHYS, pci_sz, PCI_REGION_MEM | PCI_REGION_SYS_MEMORY | PCI_REGION_PREFETCH); set_inbound_window(pi--, r++, pci_sz); #else pci_sz = 1ull << __ilog2_u64(sz); if (sz) { debug ("R2 bus_start: %llx phys_start: %llx size: %llx\n", (u64)bus_start, (u64)phys_start, (u64)pci_sz); pci_set_region(r, bus_start, phys_start, pci_sz, PCI_REGION_MEM | PCI_REGION_SYS_MEMORY | PCI_REGION_PREFETCH); sz -= pci_sz; bus_start += pci_sz; phys_start += pci_sz; set_inbound_window(pi--, r++, pci_sz); } #endif #ifdef CONFIG_PHYS_64BIT if (sz && (((u64)gd->ram_size) < (1ull << 32))) printf("Was not able to map all of memory via " "inbound windows -- %lld remaining\n", sz); #endif hose->region_count = r - hose->regions; return 1; }