static void __init rbtx4927_mem_setup(void) { if (TX4927_REV_PCODE() == 0x4927) { rbtx4927_clock_init(); tx4927_setup(); } else { rbtx4937_clock_init(); tx4938_setup(); } _machine_restart = toshiba_rbtx4927_restart; #ifdef CONFIG_PCI txx9_alloc_pci_controller(&txx9_primary_pcic, RBTX4927_PCIMEM, RBTX4927_PCIMEM_SIZE, RBTX4927_PCIIO, RBTX4927_PCIIO_SIZE); txx9_board_pcibios_setup = tx4927_pcibios_setup; #else set_io_port_base(KSEG1 + RBTX4927_ISA_IO_OFFSET); #endif /* TX4927-SIO DTR on (PIO[15]) */ gpio_request(15, "sio-dtr"); gpio_direction_output(15, 1); tx4927_sio_init(0, 0); }
static void __init rbtx4927_mem_setup(void) { char *argptr; if (TX4927_REV_PCODE() == 0x4927) { rbtx4927_clock_init(); tx4927_setup(); } else { rbtx4937_clock_init(); tx4938_setup(); } _machine_restart = toshiba_rbtx4927_restart; #ifdef CONFIG_PCI txx9_alloc_pci_controller(&txx9_primary_pcic, RBTX4927_PCIMEM, RBTX4927_PCIMEM_SIZE, RBTX4927_PCIIO, RBTX4927_PCIIO_SIZE); txx9_board_pcibios_setup = tx4927_pcibios_setup; #else set_io_port_base(KSEG1 + RBTX4927_ISA_IO_OFFSET); #endif /* TX4927-SIO DTR on (PIO[15]) */ gpio_request(15, "sio-dtr"); gpio_direction_output(15, 1); tx4927_sio_init(0, 0); #ifdef CONFIG_SERIAL_TXX9_CONSOLE argptr = prom_getcmdline(); if (!strstr(argptr, "console=")) strcat(argptr, " console=ttyS0,38400"); #endif }
static void __init rbtx4927_mem_setup(void) { u32 cp0_config; char *argptr; /* enable caches -- HCP5 does this, pmon does not */ cp0_config = read_c0_config(); cp0_config = cp0_config & ~(TX49_CONF_IC | TX49_CONF_DC); write_c0_config(cp0_config); if (TX4927_REV_PCODE() == 0x4927) { rbtx4927_clock_init(); tx4927_setup(); } else { rbtx4937_clock_init(); tx4938_setup(); } _machine_restart = toshiba_rbtx4927_restart; #ifdef CONFIG_PCI txx9_alloc_pci_controller(&txx9_primary_pcic, RBTX4927_PCIMEM, RBTX4927_PCIMEM_SIZE, RBTX4927_PCIIO, RBTX4927_PCIIO_SIZE); txx9_board_pcibios_setup = tx4927_pcibios_setup; #else set_io_port_base(KSEG1 + RBTX4927_ISA_IO_OFFSET); #endif tx4927_sio_init(0, 0); #ifdef CONFIG_SERIAL_TXX9_CONSOLE argptr = prom_getcmdline(); if (!strstr(argptr, "console=")) strcat(argptr, " console=ttyS0,38400"); #endif }
static void __init rbtx4938_mem_setup(void) { unsigned long long pcfg; if (txx9_master_clock == 0) txx9_master_clock = 25000000; /* 25MHz */ tx4938_setup(); #ifdef CONFIG_PCI txx9_alloc_pci_controller(&txx9_primary_pcic, 0, 0, 0, 0); txx9_board_pcibios_setup = tx4927_pcibios_setup; #else set_io_port_base(RBTX4938_ETHER_BASE); #endif tx4938_sio_init(7372800, 0); #ifdef CONFIG_TOSHIBA_RBTX4938_MPLEX_PIO58_61 pr_info("PIOSEL: disabling both ATA and NAND selection\n"); txx9_clear64(&tx4938_ccfgptr->pcfg, TX4938_PCFG_NDF_SEL | TX4938_PCFG_ATA_SEL); #endif #ifdef CONFIG_TOSHIBA_RBTX4938_MPLEX_NAND pr_info("PIOSEL: enabling NAND selection\n"); txx9_set64(&tx4938_ccfgptr->pcfg, TX4938_PCFG_NDF_SEL); txx9_clear64(&tx4938_ccfgptr->pcfg, TX4938_PCFG_ATA_SEL); #endif #ifdef CONFIG_TOSHIBA_RBTX4938_MPLEX_ATA pr_info("PIOSEL: enabling ATA selection\n"); txx9_set64(&tx4938_ccfgptr->pcfg, TX4938_PCFG_ATA_SEL); txx9_clear64(&tx4938_ccfgptr->pcfg, TX4938_PCFG_NDF_SEL); #endif #ifdef CONFIG_TOSHIBA_RBTX4938_MPLEX_KEEP pcfg = ____raw_readq(&tx4938_ccfgptr->pcfg); pr_info("PIOSEL: NAND %s, ATA %s\n", (pcfg & TX4938_PCFG_NDF_SEL) ? "enabled" : "disabled", (pcfg & TX4938_PCFG_ATA_SEL) ? "enabled" : "disabled"); #endif rbtx4938_spi_setup(); pcfg = ____raw_readq(&tx4938_ccfgptr->pcfg); /* updated */ /* fixup piosel */ if ((pcfg & (TX4938_PCFG_ATA_SEL | TX4938_PCFG_NDF_SEL)) == TX4938_PCFG_ATA_SEL) writeb((readb(rbtx4938_piosel_addr) & 0x03) | 0x04, rbtx4938_piosel_addr); else if ((pcfg & (TX4938_PCFG_ATA_SEL | TX4938_PCFG_NDF_SEL)) == TX4938_PCFG_NDF_SEL) writeb((readb(rbtx4938_piosel_addr) & 0x03) | 0x08, rbtx4938_piosel_addr); else writeb(readb(rbtx4938_piosel_addr) & ~(0x08 | 0x04), rbtx4938_piosel_addr); rbtx4938_fpga_resource.name = "FPGA Registers"; rbtx4938_fpga_resource.start = CPHYSADDR(RBTX4938_FPGA_REG_ADDR); rbtx4938_fpga_resource.end = CPHYSADDR(RBTX4938_FPGA_REG_ADDR) + 0xffff; rbtx4938_fpga_resource.flags = IORESOURCE_MEM | IORESOURCE_BUSY; if (request_resource(&txx9_ce_res[2], &rbtx4938_fpga_resource)) printk(KERN_ERR "request resource for fpga failed\n"); _machine_restart = rbtx4938_machine_restart; writeb(0xff, rbtx4938_led_addr); printk(KERN_INFO "RBTX4938 --- FPGA(Rev %02x) DIPSW:%02x,%02x\n", readb(rbtx4938_fpga_rev_addr), readb(rbtx4938_dipsw_addr), readb(rbtx4938_bdipsw_addr)); }