static void testRingbuffer(int type) { TaskHandle_t th[2]; int i; rb = xRingbufferCreate(32 * 3, type); testtype = TST_MOSTLYFILLED; xTaskCreatePinnedToCore(task1 , "tskone" , 2048, NULL, 3, &th[0], 0); xTaskCreatePinnedToCore(task2 , "tsktwo" , 2048, NULL, 3, &th[1], 0); uartRxInit(); printf("Press 'r' to read an event in isr, any other key to write one.\n"); printf("Test: mostlyfilled; putting 10 items in ringbuff ASAP, reading 1 a second\n"); vTaskDelay(15000 / portTICK_PERIOD_MS); printf("Test: mostlyempty; putting 10 items in ringbuff @ 1/sec, reading as fast as possible\n"); testtype = TST_MOSTLYEMPTY; vTaskDelay(15000 / portTICK_PERIOD_MS); //Shut down all the tasks for (i = 0; i < 2; i++) { vTaskDelete(th[i]); } xt_ints_off(1 << ETS_UART0_INUM); }
/* "inner" restart function for after RTOS, interrupts & anything else on this * core are already stopped. Stalls other core, resets hardware, * triggers restart. */ void IRAM_ATTR esp_restart_noos() { // Disable interrupts xt_ints_off(0xFFFFFFFF); // Enable RTC watchdog for 1 second rtc_wdt_protect_off(); rtc_wdt_disable(); rtc_wdt_set_stage(RTC_WDT_STAGE0, RTC_WDT_STAGE_ACTION_RESET_RTC); rtc_wdt_set_stage(RTC_WDT_STAGE1, RTC_WDT_STAGE_ACTION_RESET_SYSTEM); rtc_wdt_set_length_of_reset_signal(RTC_WDT_SYS_RESET_SIG, RTC_WDT_LENGTH_200ns); rtc_wdt_set_length_of_reset_signal(RTC_WDT_CPU_RESET_SIG, RTC_WDT_LENGTH_200ns); rtc_wdt_set_time(RTC_WDT_STAGE0, 1000); rtc_wdt_flashboot_mode_enable(); // Reset and stall the other CPU. // CPU must be reset before stalling, in case it was running a s32c1i // instruction. This would cause memory pool to be locked by arbiter // to the stalled CPU, preventing current CPU from accessing this pool. const uint32_t core_id = xPortGetCoreID(); const uint32_t other_core_id = (core_id == 0) ? 1 : 0; esp_cpu_reset(other_core_id); esp_cpu_stall(other_core_id); // Other core is now stalled, can access DPORT registers directly esp_dport_access_int_abort(); // Disable TG0/TG1 watchdogs TIMERG0.wdt_wprotect=TIMG_WDT_WKEY_VALUE; TIMERG0.wdt_config0.en = 0; TIMERG0.wdt_wprotect=0; TIMERG1.wdt_wprotect=TIMG_WDT_WKEY_VALUE; TIMERG1.wdt_config0.en = 0; TIMERG1.wdt_wprotect=0; // Flush any data left in UART FIFOs uart_tx_wait_idle(0); uart_tx_wait_idle(1); uart_tx_wait_idle(2); // Disable cache Cache_Read_Disable(0); Cache_Read_Disable(1); // 2nd stage bootloader reconfigures SPI flash signals. // Reset them to the defaults expected by ROM. WRITE_PERI_REG(GPIO_FUNC0_IN_SEL_CFG_REG, 0x30); WRITE_PERI_REG(GPIO_FUNC1_IN_SEL_CFG_REG, 0x30); WRITE_PERI_REG(GPIO_FUNC2_IN_SEL_CFG_REG, 0x30); WRITE_PERI_REG(GPIO_FUNC3_IN_SEL_CFG_REG, 0x30); WRITE_PERI_REG(GPIO_FUNC4_IN_SEL_CFG_REG, 0x30); WRITE_PERI_REG(GPIO_FUNC5_IN_SEL_CFG_REG, 0x30); // Reset wifi/bluetooth/ethernet/sdio (bb/mac) DPORT_SET_PERI_REG_MASK(DPORT_CORE_RST_EN_REG, DPORT_BB_RST | DPORT_FE_RST | DPORT_MAC_RST | DPORT_BT_RST | DPORT_BTMAC_RST | DPORT_SDIO_RST | DPORT_SDIO_HOST_RST | DPORT_EMAC_RST | DPORT_MACPWR_RST | DPORT_RW_BTMAC_RST | DPORT_RW_BTLP_RST); DPORT_REG_WRITE(DPORT_CORE_RST_EN_REG, 0); // Reset timer/spi/uart DPORT_SET_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_TIMERS_RST | DPORT_SPI01_RST | DPORT_UART_RST); DPORT_REG_WRITE(DPORT_PERIP_RST_EN_REG, 0); // Set CPU back to XTAL source, no PLL, same as hard reset rtc_clk_cpu_freq_set_xtal(); // Clear entry point for APP CPU DPORT_REG_WRITE(DPORT_APPCPU_CTRL_D_REG, 0); // Reset CPUs if (core_id == 0) { // Running on PRO CPU: APP CPU is stalled. Can reset both CPUs. esp_cpu_reset(1); esp_cpu_reset(0); } else { // Running on APP CPU: need to reset PRO CPU and unstall it, // then reset APP CPU esp_cpu_reset(0); esp_cpu_unstall(0); esp_cpu_reset(1); } while(true) { ; } }
void timer0_detachInterrupt() { timer0_user_cb = NULL; xt_ints_off(1<<XCHAL_TIMER1_INTERRUPT); }