void MIPrinter::print(const MachineInstr &MI) { const auto *MF = MI.getMF(); const auto &MRI = MF->getRegInfo(); const auto &SubTarget = MF->getSubtarget(); const auto *TRI = SubTarget.getRegisterInfo(); assert(TRI && "Expected target register info"); const auto *TII = SubTarget.getInstrInfo(); assert(TII && "Expected target instruction info"); if (MI.isCFIInstruction()) assert(MI.getNumOperands() == 1 && "Expected 1 operand in CFI instruction"); SmallBitVector PrintedTypes(8); bool ShouldPrintRegisterTies = MI.hasComplexRegisterTies(); unsigned I = 0, E = MI.getNumOperands(); for (; I < E && MI.getOperand(I).isReg() && MI.getOperand(I).isDef() && !MI.getOperand(I).isImplicit(); ++I) { if (I) OS << ", "; print(MI, I, TRI, ShouldPrintRegisterTies, MI.getTypeToPrint(I, PrintedTypes, MRI), /*PrintDef=*/false); } if (I) OS << " = "; if (MI.getFlag(MachineInstr::FrameSetup)) OS << "frame-setup "; OS << TII->getName(MI.getOpcode()); if (I < E) OS << ' '; bool NeedComma = false; for (; I < E; ++I) { if (NeedComma) OS << ", "; print(MI, I, TRI, ShouldPrintRegisterTies, MI.getTypeToPrint(I, PrintedTypes, MRI)); NeedComma = true; } if (MI.getDebugLoc()) { if (NeedComma) OS << ','; OS << " debug-location "; MI.getDebugLoc()->printAsOperand(OS, MST); } if (!MI.memoperands_empty()) { OS << " :: "; const LLVMContext &Context = MF->getFunction().getContext(); bool NeedComma = false; for (const auto *Op : MI.memoperands()) { if (NeedComma) OS << ", "; print(Context, *TII, *Op); NeedComma = true; } } }
void MIPrinter::print(const MachineInstr &MI) { const auto &SubTarget = MI.getParent()->getParent()->getSubtarget(); const auto *TRI = SubTarget.getRegisterInfo(); assert(TRI && "Expected target register info"); const auto *TII = SubTarget.getInstrInfo(); assert(TII && "Expected target instruction info"); if (MI.isCFIInstruction()) assert(MI.getNumOperands() == 1 && "Expected 1 operand in CFI instruction"); bool ShouldPrintRegisterTies = hasComplexRegisterTies(MI); unsigned I = 0, E = MI.getNumOperands(); for (; I < E && MI.getOperand(I).isReg() && MI.getOperand(I).isDef() && !MI.getOperand(I).isImplicit(); ++I) { if (I) OS << ", "; print(MI.getOperand(I), TRI, I, ShouldPrintRegisterTies, /*IsDef=*/true); } if (I) OS << " = "; if (MI.getFlag(MachineInstr::FrameSetup)) OS << "frame-setup "; OS << TII->getName(MI.getOpcode()); if (I < E) OS << ' '; bool NeedComma = false; for (; I < E; ++I) { if (NeedComma) OS << ", "; print(MI.getOperand(I), TRI, I, ShouldPrintRegisterTies); NeedComma = true; } if (MI.getDebugLoc()) { if (NeedComma) OS << ','; OS << " debug-location "; MI.getDebugLoc()->printAsOperand(OS, MST); } if (!MI.memoperands_empty()) { OS << " :: "; bool NeedComma = false; for (const auto *Op : MI.memoperands()) { if (NeedComma) OS << ", "; print(*Op); NeedComma = true; } } }
void MIPrinter::print(const MachineInstr &MI) { const auto &SubTarget = MI.getParent()->getParent()->getSubtarget(); const auto *TRI = SubTarget.getRegisterInfo(); assert(TRI && "Expected target register info"); const auto *TII = SubTarget.getInstrInfo(); assert(TII && "Expected target instruction info"); if (MI.isCFIInstruction()) assert(MI.getNumOperands() == 1 && "Expected 1 operand in CFI instruction"); unsigned I = 0, E = MI.getNumOperands(); for (; I < E && MI.getOperand(I).isReg() && MI.getOperand(I).isDef() && !MI.getOperand(I).isImplicit(); ++I) { if (I) OS << ", "; print(MI.getOperand(I), TRI); } if (I) OS << " = "; if (MI.getFlag(MachineInstr::FrameSetup)) OS << "frame-setup "; OS << TII->getName(MI.getOpcode()); // TODO: Print the bundling instruction flags, machine mem operands. if (I < E) OS << ' '; bool NeedComma = false; for (; I < E; ++I) { if (NeedComma) OS << ", "; print(MI.getOperand(I), TRI); NeedComma = true; } if (MI.getDebugLoc()) { if (NeedComma) OS << ','; OS << " debug-location "; MI.getDebugLoc()->printAsOperand(OS, MST); } }
void MIPrinter::print(const MachineInstr &MI) { const auto *MF = MI.getMF(); const auto &MRI = MF->getRegInfo(); const auto &SubTarget = MF->getSubtarget(); const auto *TRI = SubTarget.getRegisterInfo(); assert(TRI && "Expected target register info"); const auto *TII = SubTarget.getInstrInfo(); assert(TII && "Expected target instruction info"); if (MI.isCFIInstruction()) assert(MI.getNumOperands() == 1 && "Expected 1 operand in CFI instruction"); SmallBitVector PrintedTypes(8); bool ShouldPrintRegisterTies = MI.hasComplexRegisterTies(); unsigned I = 0, E = MI.getNumOperands(); for (; I < E && MI.getOperand(I).isReg() && MI.getOperand(I).isDef() && !MI.getOperand(I).isImplicit(); ++I) { if (I) OS << ", "; print(MI, I, TRI, ShouldPrintRegisterTies, MI.getTypeToPrint(I, PrintedTypes, MRI), /*PrintDef=*/false); } if (I) OS << " = "; if (MI.getFlag(MachineInstr::FrameSetup)) OS << "frame-setup "; if (MI.getFlag(MachineInstr::FrameDestroy)) OS << "frame-destroy "; if (MI.getFlag(MachineInstr::FmNoNans)) OS << "nnan "; if (MI.getFlag(MachineInstr::FmNoInfs)) OS << "ninf "; if (MI.getFlag(MachineInstr::FmNsz)) OS << "nsz "; if (MI.getFlag(MachineInstr::FmArcp)) OS << "arcp "; if (MI.getFlag(MachineInstr::FmContract)) OS << "contract "; if (MI.getFlag(MachineInstr::FmAfn)) OS << "afn "; if (MI.getFlag(MachineInstr::FmReassoc)) OS << "reassoc "; if (MI.getFlag(MachineInstr::NoUWrap)) OS << "nuw "; if (MI.getFlag(MachineInstr::NoSWrap)) OS << "nsw "; if (MI.getFlag(MachineInstr::IsExact)) OS << "exact "; OS << TII->getName(MI.getOpcode()); if (I < E) OS << ' '; bool NeedComma = false; for (; I < E; ++I) { if (NeedComma) OS << ", "; print(MI, I, TRI, ShouldPrintRegisterTies, MI.getTypeToPrint(I, PrintedTypes, MRI)); NeedComma = true; } // Print any optional symbols attached to this instruction as-if they were // operands. if (MCSymbol *PreInstrSymbol = MI.getPreInstrSymbol()) { if (NeedComma) OS << ','; OS << " pre-instr-symbol "; MachineOperand::printSymbol(OS, *PreInstrSymbol); NeedComma = true; } if (MCSymbol *PostInstrSymbol = MI.getPostInstrSymbol()) { if (NeedComma) OS << ','; OS << " post-instr-symbol "; MachineOperand::printSymbol(OS, *PostInstrSymbol); NeedComma = true; } if (const DebugLoc &DL = MI.getDebugLoc()) { if (NeedComma) OS << ','; OS << " debug-location "; DL->printAsOperand(OS, MST); } if (!MI.memoperands_empty()) { OS << " :: "; const LLVMContext &Context = MF->getFunction().getContext(); const MachineFrameInfo &MFI = MF->getFrameInfo(); bool NeedComma = false; for (const auto *Op : MI.memoperands()) { if (NeedComma) OS << ", "; Op->print(OS, MST, SSNs, Context, &MFI, TII); NeedComma = true; } } }