void prestige_state::machine_start()
{
std::string region_tag;
m_cart_rom = memregion(region_tag.assign(m_cart->tag()).append(GENERIC_ROM_REGION_TAG).c_str());
uint8_t *rom = memregion("maincpu")->base();
uint8_t *cart = nullptr;
if (m_cart_rom != nullptr)
{
cart = m_cart_rom->base();
}
else
{
cart = rom + 0x40000; // internal ROM also includes extra contents that are activated by a cartridge that works as a jumper
}
uint8_t *ram = m_ram->pointer();
memset(ram, 0x00, m_ram->size());
m_bank1->configure_entries(0, 64, rom, 0x4000);
m_bank1->configure_entries(64,32, cart, 0x4000);
m_bank2->configure_entries(0, 64, rom, 0x4000);
m_bank2->configure_entries(64,32, cart, 0x4000);
m_bank3->configure_entries(0, 64, rom, 0x4000);
m_bank3->configure_entries(64,32, cart, 0x4000);
m_bank4->configure_entries(0, 4, ram, 0x2000);
m_bank5->configure_entries(0, 4, ram, 0x2000);
m_bank1->set_entry(0);
m_bank2->set_entry(0);
m_bank3->set_entry(0);
m_bank4->set_entry(0);
m_bank5->set_entry(0);
//pointer to the videoram
m_vram = ram;
}
INPUT_PORTS_END
void cms_state::machine_start()
{
m_bank1->configure_entries(0, 16, m_rom->base(), 0x4000);
memset(&m_rtc_data, 0, sizeof(m_rtc_data));
m_rtc_reg = 0;
m_rtc_state = 0;
m_rtc_data[0xf] = 1;
m_rtc_timer = timer_alloc();
m_rtc_timer->adjust(attotime::zero, 0, attotime(1, 0));
}
INPUT_PORTS_END
void pc2000_state::machine_start()
{
std::string region_tag;
UINT8 *bios = memregion("bios")->base();
UINT8 *cart = memregion(region_tag.assign(m_cart->tag()).append(GENERIC_ROM_REGION_TAG).c_str())->base();
if (!cart)
cart = memregion("bios")->base();
m_bank0->configure_entries(0, 0x10, bios, 0x4000);
m_bank1->configure_entries(0, 0x10, bios, 0x4000);
m_bank2->configure_entries(0, 0x10, bios, 0x4000);
m_bank2->configure_entries(0x80, 0x10, cart, 0x4000);
}
void odyssey2_state::switch_banks()
{
switch ( m_cart_size )
{
case 12288:
/* 12KB cart support (for instance, KTAA as released) */
m_bank1->set_base( m_user1->base() + (m_p1 & 0x03) * 0xC00 );
m_bank2->set_base( m_user1->base() + (m_p1 & 0x03) * 0xC00 + 0x800 );
break;
case 16384:
/* 16KB cart support (for instance, full sized version KTAA) */
m_bank1->set_base( m_user1->base() + (m_p1 & 0x03) * 0x1000 + 0x400 );
m_bank2->set_base( m_user1->base() + (m_p1 & 0x03) * 0x1000 + 0xC00 );
break;
default:
m_bank1->set_base( m_user1->base() + (m_p1 & 0x03) * 0x800 );
m_bank2->set_base( m_user1->base() + (m_p1 & 0x03) * 0x800 );
break;
}
}
void sigmab52_state::machine_reset()
{
m_bank1->set_entry(1);
m_coin_start_cycles = 0;
m_hopper_start_cycles = 0;
}
void sothello_state::machine_start()
{
m_bank1->configure_entries(0, 4, memregion("maincpu")->base() + 0x8000, 0x4000);
}
void sfkick_state::sfkick_remap_banks()
{
/* 0000-3fff */
switch(m_bank_cfg&3)
{
case 0: /* bios */
{
UINT8 *mem = m_region_bios->base();
m_bank1->set_base(mem);
m_bank2->set_base(mem+0x2000);
}
break;
case 1: /* ext rom */
{
UINT8 *mem = m_region_extrom->base();
m_bank1->set_base(mem+0x4000);
m_bank2->set_base(mem+0x6000);
}
break;
case 2: /* banked */
{
UINT8 *mem = m_region_banked->base();
m_bank1->set_base(mem+0x2000*m_bank[0]);
m_bank2->set_base(mem+0x2000*m_bank[1]);
}
break;
case 3: /* unknown */
{
UINT8 *mem = m_region_banked->base();
m_bank1->set_base(mem+0x18000);
m_bank2->set_base(mem+0x18000);
}
break;
}
/* 4000-7fff */
switch((m_bank_cfg>>2)&3)
{
case 0: /* bios - upper part */
{
UINT8 *mem = m_region_bios->base();
m_bank3->set_base(mem+0x4000);
m_bank4->set_base(mem+0x6000);
}
break;
case 1: /* unknown */
case 3:
{
UINT8 *mem = m_region_banked->base();
m_bank3->set_base(mem+0x18000);
m_bank4->set_base(mem+0x18000);
}
break;
case 2: /* banked */
{
UINT8 *mem = m_region_banked->base();
m_bank3->set_base(mem+0x2000*m_bank[2]);
m_bank4->set_base(mem+0x2000*m_bank[3]);
}
break;
}
/* 8000-bfff */
switch((m_bank_cfg>>4)&3)
{
case 0: /* cartridge */
{
UINT8 *mem = m_region_cartridge->base();
m_bank5->set_base(mem+0x4000);
m_bank6->set_base(mem+0x6000);
}
break;
case 1: /* unknown */
case 3:
{
UINT8 *mem = m_region_banked->base();
m_bank5->set_base(mem+0x18000);
m_bank6->set_base(mem+0x18000);
}
break;
case 2: /* banked */
{
UINT8 *mem = m_region_banked->base();
m_bank5->set_base(mem+0x2000*m_bank[4]);
m_bank6->set_base(mem+0x2000*m_bank[5]);
}
break;
}
/* c000-ffff */
switch((m_bank_cfg>>6)&3)
{
case 0: /* unknown */
case 1:
{
UINT8 *mem = m_region_banked->base();
m_bank7->set_base(mem+0x18000);
m_bank8->set_base(mem+0x18000);
}
break;
case 2: /* banked */
{
UINT8 *mem = m_region_banked->base();
m_bank7->set_base(mem+0x2000*m_bank[6]);
m_bank8->set_base(mem+0x2000*m_bank[7]);
}
break;
case 3: /* RAM */
{
m_bank7->set_base(m_main_mem.get());
m_bank8->set_base(m_main_mem.get()+0x2000);
}
break;
}
}
void can09_state::machine_start()
{
LOG("%s()\n", FUNCNAME);
m_bank1->configure_entries(0, 8, m_ram->pointer(), 0x8000);
}
void pcat_dyn_state::machine_start()
{
m_prgbank->configure_entries(0, 256, memregion("game_prg")->base(), 0x1000);
m_nvram_bank->configure_entries(0, 2, &m_nvram_mem[0], 0x1000);
machine().device<nvram_device>("nvram")->set_base(&m_nvram_mem[0], 0x2000);
}
void iq151_state::machine_reset()
{
m_boot_bank->set_entry(0);
m_vblank_irq_state = 0;
}
void iq151_state::machine_start()
{
uint8_t *RAM = memregion("maincpu")->base();
m_boot_bank->configure_entry(0, RAM + 0xf800);
m_boot_bank->configure_entry(1, RAM + 0x0000);
}
void cms_state::machine_reset()
{
m_bank1->set_entry(0);
}
void speglsht_state::machine_start()
{
m_st0016_bank->configure_entries(0, 256, memregion("maincpu")->base(), 0x4000);
}
void acvirus_state::machine_start()
{
m_rombank->configure_entries(0, 15, memregion("maincpu")->base(), 0x8000);
m_rombank->set_entry(3);
}
void taitowlf_state::machine_reset()
{
// disable RAM access (reads go to BIOS ROM)
m_bank1->set_entry(0);
}
void can09_state::machine_reset()
{
LOG("%s()\n", FUNCNAME);
m_bank1->set_entry(0);
}
void scv_state::scv_set_banks()
{
m_cart_ram_enabled = false;
switch( m_cart_rom_size )
{
case 0:
case 0x2000:
m_bank0->set_base( m_cart_rom );
m_bank1->set_base( m_cart_rom );
m_bank2->set_base( m_cart_rom );
m_bank3->set_base( m_cart_rom );
m_bank4->set_base( m_cart_rom + 0x1000 );
break;
case 0x4000:
m_bank0->set_base( m_cart_rom );
m_bank1->set_base( m_cart_rom + 0x2000 );
m_bank2->set_base( m_cart_rom );
m_bank3->set_base( m_cart_rom + 0x2000 );
m_bank4->set_base( m_cart_rom + 0x3000 );
break;
case 0x8000:
m_bank0->set_base( m_cart_rom );
m_bank1->set_base( m_cart_rom + 0x2000 );
m_bank2->set_base( m_cart_rom + 0x4000 );
m_bank3->set_base( m_cart_rom + 0x6000 );
m_bank4->set_base( m_cart_rom + 0x7000 );
break;
case 0x10000:
m_bank0->set_base( m_cart_rom + ( ( m_portc & 0x20 ) ? 0x8000 : 0 ) );
m_bank1->set_base( m_cart_rom + ( ( m_portc & 0x20 ) ? 0xa000 : 0x2000 ) );
m_bank2->set_base( m_cart_rom + ( ( m_portc & 0x20 ) ? 0xc000 : 0x4000 ) );
m_bank3->set_base( m_cart_rom + ( ( m_portc & 0x20 ) ? 0xe000 : 0x6000 ) );
m_bank4->set_base( m_cart_rom + ( ( m_portc & 0x20 ) ? 0xf000 : 0x7000 ) );
break;
case 0x20000: /* Pole Position 2 */
int base = ( ( m_portc >> 5 ) & 0x03 ) * 0x8000 ;
m_bank0->set_base( m_cart_rom + base + 0 );
m_bank1->set_base( m_cart_rom + base + 0x2000 );
m_bank2->set_base( m_cart_rom + base + 0x4000 );
m_bank3->set_base( m_cart_rom + base + 0x6000 );
m_bank4->set_base( m_cart_rom + base + 0x7000 );
/* On-cart RAM is enabled when PC6 is high */
if ( m_cart_ram && m_portc & 0x40 )
{
m_cart_ram_enabled = true;
m_bank4->set_base( m_cart_ram );
}
break;
}
/* Check if cartridge RAM is available and should be enabled */
if ( m_cart_rom_size < 0x20000 && m_cart_ram && m_cart_ram_size && ( m_portc & 0x20 ) )
{
if ( m_cart_ram_size == 0x1000 )
{
m_bank4->set_base( m_cart_ram );
}
else
{
m_bank3->set_base( m_cart_ram );
m_bank4->set_base( m_cart_ram + 0x1000 );
}
m_cart_ram_enabled = true;
}
}
void magtouch_state::machine_start()
{
m_rombank->configure_entries(0, 0x80, memregion("game_prg")->base(), 0x8000 );
m_rombank->set_entry(0);
subdevice<nvram_device>("nvram")->set_base(memshare("nvram")->ptr(), 0x2000);
}