//--------------------------------
void esp8266::ConfigureUART(uint32_t nBps) {
SysCtlPeripheralEnable(SYSCTL_PERIPH_UART1);
GPIOPinConfigure(GPIO_PC4_U1RX);
GPIOPinConfigure(GPIO_PC5_U1TX);
GPIOPinTypeUART(GPIO_PORTC_BASE, GPIO_PIN_4 | GPIO_PIN_5);
UARTClockSourceSet(UART_BASE, UART_CLOCK_PIOSC);
SetBitrate(nBps);
MAP_UARTFIFOLevelSet(UART_BASE, UART_FIFO_TX1_8, UART_FIFO_RX1_8);
MAP_UARTIntDisable(UART_BASE, 0xFFFFFFFF);
MAP_UARTIntEnable(UART_BASE, UART_INT_RX | UART_INT_RT);
MAP_IntEnable(UART_INT);
MAP_UARTEnable(UART_BASE);
}
int main() {
#ifndef USE_TIRTOS
MAP_IntVTableBaseSet((unsigned long) &g_pfnVectors[0]);
#endif
MAP_IntEnable(FAULT_SYSTICK);
MAP_IntMasterEnable();
PRCMCC3200MCUInit();
/* Console UART init. */
MAP_PRCMPeripheralClkEnable(CONSOLE_UART_PERIPH, PRCM_RUN_MODE_CLK);
MAP_PinTypeUART(PIN_55, PIN_MODE_3); /* PIN_55 -> UART0_TX */
MAP_PinTypeUART(PIN_57, PIN_MODE_3); /* PIN_57 -> UART0_RX */
MAP_UARTConfigSetExpClk(
CONSOLE_UART, MAP_PRCMPeripheralClockGet(CONSOLE_UART_PERIPH),
CONSOLE_BAUD_RATE,
(UART_CONFIG_WLEN_8 | UART_CONFIG_STOP_ONE | UART_CONFIG_PAR_NONE));
MAP_UARTFIFOLevelSet(CONSOLE_UART, UART_FIFO_TX1_8, UART_FIFO_RX4_8);
MAP_UARTFIFOEnable(CONSOLE_UART);
setvbuf(stdout, NULL, _IOLBF, 0);
setvbuf(stderr, NULL, _IOLBF, 0);
cs_log_set_level(LL_INFO);
cs_log_set_file(stdout);
LOG(LL_INFO, ("Hello, world!"));
MAP_PinTypeI2C(PIN_01, PIN_MODE_1); /* SDA */
MAP_PinTypeI2C(PIN_02, PIN_MODE_1); /* SCL */
I2C_IF_Open(I2C_MASTER_MODE_FST);
/* Set up the red LED. Note that amber and green cannot be used as they share
* pins with I2C. */
MAP_PRCMPeripheralClkEnable(PRCM_GPIOA1, PRCM_RUN_MODE_CLK);
MAP_PinTypeGPIO(PIN_64, PIN_MODE_0, false);
MAP_GPIODirModeSet(GPIOA1_BASE, 0x2, GPIO_DIR_MODE_OUT);
GPIO_IF_LedConfigure(LED1);
GPIO_IF_LedOn(MCU_RED_LED_GPIO);
if (VStartSimpleLinkSpawnTask(8) != 0) {
LOG(LL_ERROR, ("Failed to create SL task"));
}
if (!mg_start_task(MG_TASK_PRIORITY, MG_TASK_STACK_SIZE, mg_init)) {
LOG(LL_ERROR, ("Failed to create MG task"));
}
osi_start();
return 0;
}
// assumes init parameters have been set up correctly
bool uart_init2(pyb_uart_obj_t *self) {
uint uartPerh;
switch (self->uart_id) {
case PYB_UART_0:
self->reg = UARTA0_BASE;
uartPerh = PRCM_UARTA0;
MAP_UARTIntRegister(UARTA0_BASE, UART0IntHandler);
MAP_IntPrioritySet(INT_UARTA0, INT_PRIORITY_LVL_3);
break;
case PYB_UART_1:
self->reg = UARTA1_BASE;
uartPerh = PRCM_UARTA1;
MAP_UARTIntRegister(UARTA1_BASE, UART1IntHandler);
MAP_IntPrioritySet(INT_UARTA1, INT_PRIORITY_LVL_3);
break;
default:
return false;
}
// Enable the peripheral clock
MAP_PRCMPeripheralClkEnable(uartPerh, PRCM_RUN_MODE_CLK | PRCM_SLP_MODE_CLK);
// Reset the uart
MAP_PRCMPeripheralReset(uartPerh);
// Initialize the UART
MAP_UARTConfigSetExpClk(self->reg, MAP_PRCMPeripheralClockGet(uartPerh),
self->baudrate, self->config);
// Enbale the FIFO
MAP_UARTFIFOEnable(self->reg);
// Configure the FIFO interrupt levels
MAP_UARTFIFOLevelSet(self->reg, UART_FIFO_TX4_8, UART_FIFO_RX4_8);
// Configure the flow control mode
UARTFlowControlSet(self->reg, self->flowcontrol);
// Enable the RX and RX timeout interrupts
MAP_UARTIntEnable(self->reg, UART_INT_RX | UART_INT_RT);
self->enabled = true;
return true;
}
//*****************************************************************************
//
//! Initializes the UART0 peripheral and sets up the TX and RX uDMA channels.
//! The UART is configured for loopback mode so that any data sent on TX will be
//! received on RX. The uDMA channels are configured so that the TX channel
//! will copy data from a buffer to the UART TX output. And the uDMA RX channel
//! will receive any incoming data into a pair of buffers in ping-pong mode.
//!
//! \param None
//!
//! \return None
//!
//*****************************************************************************
void
InitUART0Transfer(void)
{
unsigned int uIdx;
//
// Fill the TX buffer with a simple data pattern.
//
for(uIdx = 0; uIdx < UART_TXBUF_SIZE; uIdx++)
{
g_ucTxBuf[uIdx] = 65;
}
MAP_PRCMPeripheralReset(PRCM_UARTA0);
MAP_PRCMPeripheralClkEnable(PRCM_UARTA0,PRCM_RUN_MODE_CLK);
MAP_UARTConfigSetExpClk(CONSOLE,SYSCLK, UART_BAUD_RATE,
(UART_CONFIG_WLEN_8 | UART_CONFIG_STOP_ONE |
UART_CONFIG_PAR_NONE));
MAP_uDMAChannelAssign(UDMA_CH8_UARTA0_RX);
MAP_uDMAChannelAssign(UDMA_CH9_UARTA0_TX);
MAP_UARTIntRegister(UARTA0_BASE,UART0IntHandler);
//
// Set both the TX and RX trigger thresholds to 4. This will be used by
// the uDMA controller to signal when more data should be transferred. The
// uDMA TX and RX channels will be configured so that it can transfer 4
// bytes in a burst when the UART is ready to transfer more data.
//
MAP_UARTFIFOLevelSet(UARTA0_BASE, UART_FIFO_TX4_8, UART_FIFO_RX4_8);
//
// Enable the UART for operation, and enable the uDMA interface for both TX
// and RX channels.
//
MAP_UARTEnable(UARTA0_BASE);
//
// This register write will set the UART to operate in loopback mode. Any
// data sent on the TX output will be received on the RX input.
//
HWREG(UARTA0_BASE + UART_O_CTL) |= UART_CTL_LBE;
//
// Enable the UART peripheral interrupts. uDMA controller will cause an
// interrupt on the UART interrupt signal when a uDMA transfer is complete.
//
MAP_UARTIntEnable(UARTA0_BASE,UART_INT_DMATX);
MAP_UARTIntEnable(UARTA0_BASE,UART_INT_DMARX);
//
// Configure the control parameters for the UART TX. The uDMA UART TX
// channel is used to transfer a block of data from a buffer to the UART.
// The data size is 8 bits. The source address increment is 8-bit bytes
// since the data is coming from a buffer. The destination increment is
// none since the data is to be written to the UART data register. The
// arbitration size is set to 4, which matches the UART TX FIFO trigger
// threshold.
//
UDMASetupTransfer(UDMA_CH8_UARTA0_RX | UDMA_PRI_SELECT, UDMA_MODE_PINGPONG,
sizeof(g_ucRxBufA),UDMA_SIZE_8, UDMA_ARB_4,
(void *)(UARTA0_BASE + UART_O_DR), UDMA_SRC_INC_NONE,
g_ucRxBufA, UDMA_DST_INC_8);
UDMASetupTransfer(UDMA_CH8_UARTA0_RX | UDMA_ALT_SELECT, UDMA_MODE_PINGPONG,
sizeof(g_ucRxBufB),UDMA_SIZE_8, UDMA_ARB_4,
(void *)(UARTA0_BASE + UART_O_DR), UDMA_SRC_INC_NONE,
g_ucRxBufB, UDMA_DST_INC_8);
UDMASetupTransfer(UDMA_CH9_UARTA0_TX| UDMA_PRI_SELECT,
UDMA_MODE_BASIC,sizeof(g_ucTxBuf),UDMA_SIZE_8, UDMA_ARB_4,
g_ucTxBuf, UDMA_SRC_INC_8,(void *)(UARTA0_BASE + UART_O_DR),
UDMA_DST_INC_NONE);
MAP_UARTDMAEnable(UARTA0_BASE, UART_DMA_RX | UART_DMA_TX);
}
bool mgos_uart_hal_configure(struct mgos_uart_state *us,
const struct mgos_uart_config *cfg) {
uint32_t base = cc32xx_uart_get_base(us->uart_no);
if (us->uart_no == 0 && (cfg->tx_fc_type == MGOS_UART_FC_HW ||
cfg->rx_fc_type == MGOS_UART_FC_HW)) {
/* No FC on UART0, according to the TRM. */
return false;
}
MAP_UARTIntDisable(base, ~0);
uint32_t periph = (us->uart_no == 0 ? PRCM_UARTA0 : PRCM_UARTA1);
uint32_t data_cfg = 0;
switch (cfg->num_data_bits) {
case 5:
data_cfg |= UART_CONFIG_WLEN_5;
break;
case 6:
data_cfg |= UART_CONFIG_WLEN_6;
break;
case 7:
data_cfg |= UART_CONFIG_WLEN_7;
break;
case 8:
data_cfg |= UART_CONFIG_WLEN_8;
break;
default:
return false;
}
switch (cfg->parity) {
case MGOS_UART_PARITY_NONE:
data_cfg |= UART_CONFIG_PAR_NONE;
break;
case MGOS_UART_PARITY_EVEN:
data_cfg |= UART_CONFIG_PAR_EVEN;
break;
case MGOS_UART_PARITY_ODD:
data_cfg |= UART_CONFIG_PAR_ODD;
break;
}
switch (cfg->stop_bits) {
case MGOS_UART_STOP_BITS_1:
data_cfg |= UART_CONFIG_STOP_ONE;
break;
case MGOS_UART_STOP_BITS_1_5:
return false; /* Not supported */
case MGOS_UART_STOP_BITS_2:
data_cfg |= UART_CONFIG_STOP_TWO;
break;
}
MAP_UARTConfigSetExpClk(base, MAP_PRCMPeripheralClockGet(periph),
cfg->baud_rate, data_cfg);
if (cfg->tx_fc_type == MGOS_UART_FC_HW ||
cfg->rx_fc_type == MGOS_UART_FC_HW) {
/* Note: only UART1 */
uint32_t ctl = HWREG(base + UART_O_CTL);
if (cfg->tx_fc_type == MGOS_UART_FC_HW) {
ctl |= UART_CTL_CTSEN;
MAP_PinTypeUART(PIN_61, PIN_MODE_3); /* UART1_CTS */
}
if (cfg->rx_fc_type == MGOS_UART_FC_HW) {
ctl |= UART_CTL_RTSEN;
MAP_PinTypeUART(PIN_62, PIN_MODE_3); /* UART1_RTS */
}
HWREG(base + UART_O_CTL) = ctl;
}
MAP_UARTFIFOLevelSet(base, UART_FIFO_TX1_8, UART_FIFO_RX4_8);
MAP_UARTFIFOEnable(base);
return true;
}
int main(void) {
MAP_IntVTableBaseSet((unsigned long) &int_vectors[0]);
MAP_IntMasterEnable();
PRCMCC3200MCUInit();
/* Console UART init. */
#ifndef NO_DEBUG
MAP_PRCMPeripheralClkEnable(DEBUG_UART_PERIPH, PRCM_RUN_MODE_CLK);
#if MIOT_DEBUG_UART == 0
MAP_PinTypeUART(PIN_55, PIN_MODE_3); /* UART0_TX */
MAP_PinTypeUART(PIN_57, PIN_MODE_3); /* UART0_RX */
#else
MAP_PinTypeUART(PIN_07, PIN_MODE_5); /* UART1_TX */
MAP_PinTypeUART(PIN_08, PIN_MODE_5); /* UART1_RX */
#endif
MAP_UARTConfigSetExpClk(
DEBUG_UART_BASE, MAP_PRCMPeripheralClockGet(DEBUG_UART_PERIPH),
MIOT_DEBUG_UART_BAUD_RATE,
(UART_CONFIG_WLEN_8 | UART_CONFIG_STOP_ONE | UART_CONFIG_PAR_NONE));
MAP_UARTFIFOLevelSet(DEBUG_UART_BASE, UART_FIFO_TX1_8, UART_FIFO_RX4_8);
MAP_UARTFIFODisable(DEBUG_UART_BASE);
#endif
dbg_puts("\r\n\n");
if (sl_Start(NULL, NULL, NULL) < 0) abort();
dbg_putc('S');
int cidx = get_active_boot_cfg_idx();
if (cidx < 0) abort();
dbg_putc('0' + cidx);
struct boot_cfg cfg;
if (read_boot_cfg(cidx, &cfg) < 0) abort();
dbg_puts(cfg.app_image_file);
dbg_putc('@');
print_addr(cfg.app_load_addr);
/*
* Zero memory before loading.
* This should provide proper initialisation for BSS, wherever it is.
*/
uint32_t *pstart = (uint32_t *) 0x20000000;
uint32_t *pend = (&_text_start - 0x100 /* our stack */);
for (uint32_t *p = pstart; p < pend; p++) *p = 0;
if (load_image(cfg.app_image_file, (_u8 *) cfg.app_load_addr) != 0) {
abort();
}
dbg_putc('.');
sl_Stop(0);
print_addr(*(((uint32_t *) cfg.app_load_addr) + 1));
dbg_puts("\r\n\n");
MAP_IntMasterDisable();
MAP_IntVTableBaseSet(cfg.app_load_addr);
run(cfg.app_load_addr); /* Does not return. */
abort();
return 0; /* not reached */
}
bool initializeUartChannel(uint8_t channel,
uint8_t uartPort,
uint32_t baudRate,
uint32_t cpuSpeedHz,
uint32_t flags)
{
if (channel >= UART_NUMBER_OF_CHANNELS ||
uartPort >= UART_COUNT)
{
return false;
}
if (uart2UartChannelData[uartPort] != 0)
{
return false;
}
if (!(flags & UART_FLAGS_RECEIVE) && !(flags & UART_FLAGS_SEND))
{
return false;
}
uint32_t uartBase;
uint32_t uartInterruptId;
uint32_t uartPeripheralSysCtl;
switch (uartPort)
{
#ifdef DEBUG
case UART_0:
{
uartBase = UART0_BASE;
uartInterruptId = INT_UART0;
uartPeripheralSysCtl = SYSCTL_PERIPH_UART0;
ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA);
ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_UART0);
ROM_GPIOPinConfigure(GPIO_PA0_U0RX);
ROM_GPIOPinConfigure(GPIO_PA1_U0TX);
ROM_GPIOPinTypeUART(GPIO_PORTA_BASE, GPIO_PIN_0 | GPIO_PIN_1);
break;
}
#endif
case UART_1:
{
uartBase = UART1_BASE;
uartInterruptId = INT_UART1;
uartPeripheralSysCtl = SYSCTL_PERIPH_UART1;
ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOB);
ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_UART1);
ROM_GPIOPinConfigure(GPIO_PB0_U1RX);
ROM_GPIOPinConfigure(GPIO_PB1_U1TX);
ROM_GPIOPinTypeUART(GPIO_PORTB_BASE, GPIO_PIN_0 | GPIO_PIN_1);
break;
}
case UART_2:
{
uartBase = UART2_BASE;
uartInterruptId = INT_UART2;
uartPeripheralSysCtl = SYSCTL_PERIPH_UART2;
ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOD);
ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_UART2);
ROM_GPIOPinConfigure(GPIO_PD6_U2RX);
ROM_GPIOPinConfigure(GPIO_PD7_U2TX);
ROM_GPIOPinTypeUART(GPIO_PORTD_BASE, GPIO_PIN_6 | GPIO_PIN_7);
break;
}
case UART_3:
{
uartBase = UART3_BASE;
uartInterruptId = INT_UART3;
uartPeripheralSysCtl = SYSCTL_PERIPH_UART3;
ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOC);
ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_UART3);
ROM_GPIOPinConfigure(GPIO_PC6_U3RX);
ROM_GPIOPinConfigure(GPIO_PC7_U3TX);
ROM_GPIOPinTypeUART(GPIO_PORTC_BASE, GPIO_PIN_6 | GPIO_PIN_7);
break;
}
case UART_4:
{
uartBase = UART4_BASE;
uartInterruptId = INT_UART4;
uartPeripheralSysCtl = SYSCTL_PERIPH_UART4;
ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOC);
ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_UART4);
ROM_GPIOPinConfigure(GPIO_PC4_U4RX);
ROM_GPIOPinConfigure(GPIO_PC5_U4TX);
ROM_GPIOPinTypeUART(GPIO_PORTC_BASE, GPIO_PIN_4 | GPIO_PIN_5);
break;
}
default:
{
return false;
}
}
UARTClockSourceSet(uartBase, UART_CLOCK_PIOSC);
if(!MAP_SysCtlPeripheralPresent(uartPeripheralSysCtl))
{
return false;
}
MAP_SysCtlPeripheralEnable(uartPeripheralSysCtl);
MAP_UARTConfigSetExpClk(uartBase,
cpuSpeedHz,
baudRate,
(UART_CONFIG_PAR_NONE | UART_CONFIG_STOP_ONE | UART_CONFIG_WLEN_8));
MAP_UARTFIFOLevelSet(uartBase, UART_FIFO_TX1_8, UART_FIFO_RX1_8);
MAP_UARTIntDisable(uartBase, 0xFFFFFFFF);
if (flags & UART_FLAGS_RECEIVE)
{
MAP_UARTIntEnable(uartBase, UART_INT_RX | UART_INT_RT);
}
if (flags & UART_FLAGS_SEND)
{
MAP_UARTIntEnable(uartBase, UART_INT_TX);
}
MAP_IntEnable(uartInterruptId);
MAP_UARTEnable(uartBase);
uartChannelData[channel].base = uartBase;
uartChannelData[channel].interruptId = uartInterruptId;
uartChannelData[channel].writeBuffer.isEmpty = true;
uart2UartChannelData[uartPort] = &uartChannelData[channel];
return true;
}
//*****************************************************************************
//
// The main function sets up the peripherals for the example, then enters
// a wait loop until the DMA transfers are complete. At the end some
// information is printed for the user.
//
//*****************************************************************************
int
main(void)
{
unsigned long ulIdx;
//
// Set the clocking to run directly from the PLL at 50 MHz.
//
MAP_SysCtlClockSet(SYSCTL_SYSDIV_4 | SYSCTL_USE_PLL | SYSCTL_OSC_MAIN |
SYSCTL_XTAL_16MHZ);
//
// Initialize the console UART and write a message to the terminal.
//
MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA);
MAP_GPIOPinConfigure(GPIO_PA0_U0RX);
MAP_GPIOPinConfigure(GPIO_PA1_U0TX);
MAP_GPIOPinTypeUART(GPIO_PORTA_BASE, GPIO_PIN_0 | GPIO_PIN_1);
UARTStdioInit(0);
UARTprintf("\033[2JMemory/UART scatter-gather uDMA example\n\n");
//
// Configure UART1 to be used for the loopback peripheral
//
MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_UART1);
//
// Configure the UART communication parameters.
//
MAP_UARTConfigSetExpClk(UART1_BASE, MAP_SysCtlClockGet(), 115200,
UART_CONFIG_WLEN_8 | UART_CONFIG_STOP_ONE |
UART_CONFIG_PAR_NONE);
//
// Set both the TX and RX trigger thresholds to one-half (8 bytes). This
// will be used by the uDMA controller to signal when more data should be
// transferred. The uDMA TX and RX channels will be configured so that it
// can transfer 8 bytes in a burst when the UART is ready to transfer more
// data.
//
MAP_UARTFIFOLevelSet(UART1_BASE, UART_FIFO_TX4_8, UART_FIFO_RX4_8);
//
// Enable the UART for operation, and enable the uDMA interface for both TX
// and RX channels.
//
MAP_UARTEnable(UART1_BASE);
MAP_UARTDMAEnable(UART1_BASE, UART_DMA_RX | UART_DMA_TX);
//
// This register write will set the UART to operate in loopback mode. Any
// data sent on the TX output will be received on the RX input.
//
HWREG(UART1_BASE + UART_O_CTL) |= UART_CTL_LBE;
//
// Enable the UART peripheral interrupts. Note that no UART interrupts
// were enabled, but the uDMA controller will cause an interrupt on the
// UART interrupt signal when a uDMA transfer is complete.
//
MAP_IntEnable(INT_UART1);
//
// Enable the uDMA peripheral clocking.
//
MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_UDMA);
//
// Enable the uDMA controller.
//
MAP_uDMAEnable();
//
// Point at the control table to use for channel control structures.
//
MAP_uDMAControlBaseSet(sControlTable);
//
// Configure the UART TX channel for scatter-gather
// Peripheral scatter-gather is used because transfers are gated by
// requests from the peripheral
//
UARTprintf("Configuring UART TX uDMA channel for scatter-gather\n");
#ifndef USE_SGSET_API
//
// Use the original method for configuring the scatter-gather transfer
//
uDMAChannelControlSet(UDMA_CHANNEL_UART1TX, UDMA_SIZE_32 |
UDMA_SRC_INC_32 | UDMA_DST_INC_32 | UDMA_ARB_4);
uDMAChannelTransferSet(UDMA_CHANNEL_UART1TX, UDMA_MODE_PER_SCATTER_GATHER,
g_TaskTableSrc,
&sControlTable[UDMA_CHANNEL_UART1TX], 6 * 4);
#else
//
// Use the simplified API for configuring the scatter-gather transfer
//
uDMAChannelScatterGatherSet(UDMA_CHANNEL_UART1TX, 6, g_TaskTableSrc, 1);
#endif
//
// Configure the UART RX channel for scatter-gather task list.
// This is set to peripheral s-g because it starts by receiving data
// from the UART
//
UARTprintf("Configuring UART RX uDMA channel for scatter-gather\n");
#ifndef USE_SGSET_API
//
// Use the original method for configuring the scatter-gather transfer
//
uDMAChannelControlSet(UDMA_CHANNEL_UART1RX, UDMA_SIZE_32 |
UDMA_SRC_INC_32 | UDMA_DST_INC_32 | UDMA_ARB_4);
uDMAChannelTransferSet(UDMA_CHANNEL_UART1RX, UDMA_MODE_PER_SCATTER_GATHER,
g_TaskTableDst,
&sControlTable[UDMA_CHANNEL_UART1RX], 7 * 4);
#else
//
// Use the simplified API for configuring the scatter-gather transfer
//
uDMAChannelScatterGatherSet(UDMA_CHANNEL_UART1RX, 7, g_TaskTableDst, 1);
#endif
//
// Fill the source buffer with a pattern
//
for(ulIdx = 0; ulIdx < 1024; ulIdx++)
{
g_ucSrcBuf[ulIdx] = ulIdx + (ulIdx / 256);
}
//
// Enable the uDMA controller error interrupt. This interrupt will occur
// if there is a bus error during a transfer.
//
IntEnable(INT_UDMAERR);
//
// Enable the UART RX DMA channel. It will wait for data to be available
// from the UART.
//
UARTprintf("Enabling uDMA channel for UART RX\n");
MAP_uDMAChannelEnable(UDMA_CHANNEL_UART1RX);
//
// Enable the UART TX DMA channel. Since the UART TX will be asserting
// a DMA request (since the TX FIFO is empty), this will cause this
// DMA channel to start running.
//
UARTprintf("Enabling uDMA channel for UART TX\n");
MAP_uDMAChannelEnable(UDMA_CHANNEL_UART1TX);
//
// Wait for the TX task list to be finished
//
UARTprintf("Waiting for TX task list to finish ... ");
while(!g_bTXdone)
{
}
UARTprintf("done\n");
//
// Wait for the RX task list to be finished
//
UARTprintf("Waiting for RX task list to finish ... ");
while(!g_bRXdone)
{
}
UARTprintf("done\n");
//
// Verify that all the counters are in the expected state
//
UARTprintf("Verifying counters\n");
if(g_ulDMAIntCount != 2)
{
UARTprintf("ERROR in interrupt count, found %d, expected 2\n",
g_ulDMAIntCount);
}
if(g_uluDMAErrCount != 0)
{
UARTprintf("ERROR in error counter, found %d, expected 0\n",
g_uluDMAErrCount);
}
//
// Now verify the contents of the final destination buffer. Compare it
// to the original source buffer.
//
UARTprintf("Verifying buffer contents ... ");
for(ulIdx = 0; ulIdx < 1024; ulIdx++)
{
if(g_ucDstBuf[ulIdx] != g_ucSrcBuf[ulIdx])
{
UARTprintf("ERROR\n @ index %d: expected 0x%02X, found 0x%02X\n",
ulIdx, g_ucSrcBuf[ulIdx], g_ucDstBuf[ulIdx]);
UARTprintf("Checking stopped. There may be additional errors\n");
break;
}
}
if(ulIdx == 1024)
{
UARTprintf("OK\n");
}
//
// End of program, loop forever
//
for(;;)
{
}
}
