/*
* this puts the device in an inactive state
*/
static void smc_shutdown(struct net_device *dev)
{
struct smc_local *lp = netdev_priv(dev);
void __iomem *ioaddr = lp->base;
struct sk_buff *pending_skb;
DBG(2, "%s: %s\n", CARDNAME, __func__);
/* no more interrupts for me */
spin_lock_irq(&lp->lock);
SMC_SELECT_BANK(lp, 2);
SMC_SET_INT_MASK(lp, 0);
pending_skb = lp->pending_tx_skb;
lp->pending_tx_skb = NULL;
spin_unlock_irq(&lp->lock);
if (pending_skb)
dev_kfree_skb(pending_skb);
/* and tell the card to stay away from that nasty outside world */
SMC_SELECT_BANK(lp, 0);
SMC_SET_RCR(lp, RCR_CLEAR);
SMC_SET_TCR(lp, TCR_CLEAR);
#ifdef POWER_DOWN
/* finally, shut the chip down */
SMC_SELECT_BANK(lp, 1);
SMC_SET_CONFIG(lp, SMC_GET_CONFIG(lp) & ~CONFIG_EPH_POWER_EN);
#endif
}
static void smc_shutdown(struct net_device *dev)
{
struct smc_local *lp = netdev_priv(dev);
void __iomem *ioaddr = lp->base;
struct sk_buff *pending_skb;
DBG(2, "%s: %s\n", CARDNAME, __func__);
spin_lock_irq(&lp->lock);
SMC_SELECT_BANK(lp, 2);
SMC_SET_INT_MASK(lp, 0);
pending_skb = lp->pending_tx_skb;
lp->pending_tx_skb = NULL;
spin_unlock_irq(&lp->lock);
if (pending_skb)
dev_kfree_skb(pending_skb);
SMC_SELECT_BANK(lp, 0);
SMC_SET_RCR(lp, RCR_CLEAR);
SMC_SET_TCR(lp, TCR_CLEAR);
#ifdef POWER_DOWN
SMC_SELECT_BANK(lp, 1);
SMC_SET_CONFIG(lp, SMC_GET_CONFIG(lp) & ~CONFIG_EPH_POWER_EN);
#endif
}
static void smc_enable(struct net_device *dev)
{
struct smc_local *lp = netdev_priv(dev);
void __iomem *ioaddr = lp->base;
int mask;
DBG(2, "%s: %s\n", dev->name, __func__);
SMC_SELECT_BANK(lp, 0);
SMC_SET_TCR(lp, lp->tcr_cur_mode);
SMC_SET_RCR(lp, lp->rcr_cur_mode);
SMC_SELECT_BANK(lp, 1);
SMC_SET_MAC_ADDR(lp, dev->dev_addr);
mask = IM_EPH_INT|IM_RX_OVRN_INT|IM_RCV_INT;
if (lp->version >= (CHIP_91100 << 4))
mask |= IM_MDINT;
SMC_SELECT_BANK(lp, 2);
SMC_SET_INT_MASK(lp, mask);
}
static int smc_phy_read(struct net_device *dev, int phyaddr, int phyreg)
{
struct smc_local *lp = netdev_priv(dev);
void __iomem *ioaddr = lp->base;
unsigned int phydata;
SMC_SELECT_BANK(lp, 3);
smc_mii_out(dev, 0xffffffff, 32);
smc_mii_out(dev, 6 << 10 | phyaddr << 5 | phyreg, 14);
phydata = smc_mii_in(dev, 18);
SMC_SET_MII(lp, SMC_GET_MII(lp) & ~(MII_MCLK|MII_MDOE|MII_MDO));
DBG(3, "%s: phyaddr=0x%x, phyreg=0x%x, phydata=0x%x\n",
__func__, phyaddr, phyreg, phydata);
SMC_SELECT_BANK(lp, 2);
return phydata;
}
static int smc_phy_fixed(struct net_device *dev)
{
struct smc_local *lp = netdev_priv(dev);
void __iomem *ioaddr = lp->base;
int phyaddr = lp->mii.phy_id;
int bmcr, cfg1;
DBG(3, "%s: %s\n", dev->name, __func__);
cfg1 = smc_phy_read(dev, phyaddr, PHY_CFG1_REG);
cfg1 |= PHY_CFG1_LNKDIS;
smc_phy_write(dev, phyaddr, PHY_CFG1_REG, cfg1);
bmcr = 0;
if (lp->ctl_rfduplx)
bmcr |= BMCR_FULLDPLX;
if (lp->ctl_rspeed == 100)
bmcr |= BMCR_SPEED100;
smc_phy_write(dev, phyaddr, MII_BMCR, bmcr);
SMC_SELECT_BANK(lp, 0);
SMC_SET_RPC(lp, lp->rpc_cur_mode);
SMC_SELECT_BANK(lp, 2);
return 1;
}
/*
* Reads a register from the MII Management serial interface
*/
static int smc_phy_read(struct net_device *dev, int phyaddr, int phyreg)
{
struct smc_local *lp = netdev_priv(dev);
void __iomem *ioaddr = lp->base;
unsigned int phydata;
SMC_SELECT_BANK(lp, 3);
/* Idle - 32 ones */
smc_mii_out(dev, 0xffffffff, 32);
/* Start code (01) + read (10) + phyaddr + phyreg */
smc_mii_out(dev, 6 << 10 | phyaddr << 5 | phyreg, 14);
/* Turnaround (2bits) + phydata */
phydata = smc_mii_in(dev, 18);
/* Return to idle state */
SMC_SET_MII(lp, SMC_GET_MII(lp) & ~(MII_MCLK|MII_MDOE|MII_MDO));
DBG(3, "%s: phyaddr=0x%x, phyreg=0x%x, phydata=0x%x\n",
__func__, phyaddr, phyreg, phydata);
SMC_SELECT_BANK(lp, 2);
return phydata;
}
/*
* Enable Interrupts, Receive, and Transmit
*/
static void smc_enable(struct net_device *dev)
{
struct smc_local *lp = netdev_priv(dev);
void __iomem *ioaddr = lp->base;
int mask;
DBG(2, "%s: %s\n", dev->name, __func__);
/* see the header file for options in TCR/RCR DEFAULT */
SMC_SELECT_BANK(lp, 0);
SMC_SET_TCR(lp, lp->tcr_cur_mode);
SMC_SET_RCR(lp, lp->rcr_cur_mode);
SMC_SELECT_BANK(lp, 1);
SMC_SET_MAC_ADDR(lp, dev->dev_addr);
/* now, enable interrupts */
mask = IM_EPH_INT|IM_RX_OVRN_INT|IM_RCV_INT;
if (lp->version >= (CHIP_91100 << 4))
mask |= IM_MDINT;
SMC_SELECT_BANK(lp, 2);
SMC_SET_INT_MASK(lp, mask);
/*
* From this point the register bank must _NOT_ be switched away
* to something else than bank 2 without proper locking against
* races with any tasklet or interrupt handlers until smc_shutdown()
* or smc_reset() is called.
*/
}
static void smc_tx(struct net_device *dev)
{
struct smc_local *lp = netdev_priv(dev);
void __iomem *ioaddr = lp->base;
unsigned int saved_packet, packet_no, tx_status, pkt_len;
DBG(3, "%s: %s\n", dev->name, __func__);
packet_no = SMC_GET_TXFIFO(lp);
if (unlikely(packet_no & TXFIFO_TEMPTY)) {
PRINTK("%s: smc_tx with nothing on FIFO.\n", dev->name);
return;
}
saved_packet = SMC_GET_PN(lp);
SMC_SET_PN(lp, packet_no);
SMC_SET_PTR(lp, PTR_AUTOINC | PTR_READ);
SMC_GET_PKT_HDR(lp, tx_status, pkt_len);
DBG(2, "%s: TX STATUS 0x%04x PNR 0x%02x\n",
dev->name, tx_status, packet_no);
if (!(tx_status & ES_TX_SUC))
dev->stats.tx_errors++;
if (tx_status & ES_LOSTCARR)
dev->stats.tx_carrier_errors++;
if (tx_status & (ES_LATCOL | ES_16COL)) {
PRINTK("%s: %s occurred on last xmit\n", dev->name,
(tx_status & ES_LATCOL) ?
"late collision" : "too many collisions");
dev->stats.tx_window_errors++;
if (!(dev->stats.tx_window_errors & 63) && net_ratelimit()) {
printk(KERN_INFO "%s: unexpectedly large number of "
"bad collisions. Please check duplex "
"setting.\n", dev->name);
}
}
SMC_WAIT_MMU_BUSY(lp);
SMC_SET_MMU_CMD(lp, MC_FREEPKT);
SMC_WAIT_MMU_BUSY(lp);
SMC_SET_PN(lp, saved_packet);
SMC_SELECT_BANK(lp, 0);
SMC_SET_TCR(lp, lp->tcr_cur_mode);
SMC_SELECT_BANK(lp, 2);
}
/*
. Function: smc_reset( void )
. Purpose:
. This sets the SMC91111 chip to its normal state, hopefully from whatever
. mess that any other DOS driver has put it in.
.
. Maybe I should reset more registers to defaults in here? SOFTRST should
. do that for me.
.
. Method:
. 1. send a SOFT RESET
. 2. wait for it to finish
. 3. enable autorelease mode
. 4. reset the memory management unit
. 5. clear all interrupts
.
*/
static void smc_reset (struct eth_device *dev)
{
PRINTK2 ("%s: smc_reset\n", SMC_DEV_NAME);
/* This resets the registers mostly to defaults, but doesn't
affect EEPROM. That seems unnecessary */
SMC_SELECT_BANK (dev, 0);
SMC_outw (dev, RCR_SOFTRST, RCR_REG);
/* Setup the Configuration Register */
/* This is necessary because the CONFIG_REG is not affected */
/* by a soft reset */
SMC_SELECT_BANK (dev, 1);
#if defined(CONFIG_SMC91111_EXT_PHY)
SMC_outw (dev, CONFIG_DEFAULT | CONFIG_EXT_PHY, CONFIG_REG);
#else
SMC_outw (dev, CONFIG_DEFAULT, CONFIG_REG);
#endif
/* Release from possible power-down state */
/* Configuration register is not affected by Soft Reset */
SMC_outw (dev, SMC_inw (dev, CONFIG_REG) | CONFIG_EPH_POWER_EN,
CONFIG_REG);
SMC_SELECT_BANK (dev, 0);
/* this should pause enough for the chip to be happy */
udelay (10);
/* Disable transmit and receive functionality */
SMC_outw (dev, RCR_CLEAR, RCR_REG);
SMC_outw (dev, TCR_CLEAR, TCR_REG);
/* set the control register */
SMC_SELECT_BANK (dev, 1);
SMC_outw (dev, CTL_DEFAULT, CTL_REG);
/* Reset the MMU */
SMC_SELECT_BANK (dev, 2);
smc_wait_mmu_release_complete (dev);
SMC_outw (dev, MC_RESET, MMU_CMD_REG);
while (SMC_inw (dev, MMU_CMD_REG) & MC_BUSY)
udelay (1); /* Wait until not busy */
/* Note: It doesn't seem that waiting for the MMU busy is needed here,
but this is a place where future chipsets _COULD_ break. Be wary
of issuing another MMU command right after this */
/* Disable all interrupts */
SMC_outb (dev, 0, IM_REG);
}
/***********************************************
* Show available memory *
***********************************************/
void dump_memory_info(void)
{
word mem_info;
word old_bank;
old_bank = SMC_inw(BANK_SELECT)&0xF;
SMC_SELECT_BANK(0);
mem_info = SMC_inw( MIR_REG );
PRINTK2("Memory: %4d available\n", (mem_info >> 8)*2048);
SMC_SELECT_BANK(old_bank);
}
static void smc_eph_interrupt(struct net_device *dev)
{
struct smc_local *lp = netdev_priv(dev);
void __iomem *ioaddr = lp->base;
unsigned int ctl;
smc_10bt_check_media(dev, 0);
SMC_SELECT_BANK(lp, 1);
ctl = SMC_GET_CTL(lp);
SMC_SET_CTL(lp, ctl & ~CTL_LE_ENABLE);
SMC_SET_CTL(lp, ctl);
SMC_SELECT_BANK(lp, 2);
}
/*
. Function: smc_halt
. Purpose: closes down the SMC91xxx chip.
. Method:
. 1. zero the interrupt mask
. 2. clear the enable receive flag
. 3. clear the enable xmit flags
.
. TODO:
. (1) maybe utilize power down mode.
. Why not yet? Because while the chip will go into power down mode,
. the manual says that it will wake up in response to any I/O requests
. in the register space. Empirical results do not show this working.
*/
static void smc_halt(struct eth_device *dev)
{
PRINTK2("%s: smc_halt\n", SMC_DEV_NAME);
/* no more interrupts for me */
SMC_SELECT_BANK( dev, 2 );
SMC_outb( dev, 0, IM_REG );
/* and tell the card to stay away from that nasty outside world */
SMC_SELECT_BANK( dev, 0 );
SMC_outb( dev, RCR_CLEAR, RCR_REG );
SMC_outb( dev, TCR_CLEAR, TCR_REG );
swap_to(FLASH);
}
/*
. Function: smc_shutdown
. Purpose: closes down the SMC91xxx chip.
. Method:
. 1. zero the interrupt mask
. 2. clear the enable receive flag
. 3. clear the enable xmit flags
.
. TODO:
. (1) maybe utilize power down mode.
. Why not yet? Because while the chip will go into power down mode,
. the manual says that it will wake up in response to any I/O requests
. in the register space. Empirical results do not show this working.
*/
static void smc_shutdown()
{
PRINTK2(CARDNAME ": smc_shutdown\n");
/* no more interrupts for me */
SMC_SELECT_BANK( 2 );
SMC_outb( 0, IM_REG );
/* and tell the card to stay away from that nasty outside world */
SMC_SELECT_BANK( 0 );
SMC_outb( RCR_CLEAR, RCR_REG );
SMC_outb( TCR_CLEAR, TCR_REG );
#ifdef SHARED_RESOURCES
swap_to(FLASH);
#endif
}
static int write_eeprom_reg(struct eth_device *dev, u16 value, u16 reg)
{
int timeout;
SMC_SELECT_BANK(dev, 2);
SMC_outw(dev, reg, PTR_REG);
SMC_SELECT_BANK(dev, 1);
SMC_outw(dev, value, GP_REG);
SMC_outw(dev, SMC_inw (dev, CTL_REG) | CTL_EEPROM_SELECT | CTL_STORE, CTL_REG);
timeout = 100;
while ((SMC_inw(dev, CTL_REG) & CTL_STORE) && --timeout)
udelay (100);
if (timeout == 0) {
printf("Timeout Writing EEPROM register %02x\n", reg);
return 0;
}
return 1;
}
static u16 read_eeprom_reg(struct eth_device *dev, u16 reg)
{
int timeout;
SMC_SELECT_BANK(dev, 2);
SMC_outw(dev, reg, PTR_REG);
SMC_SELECT_BANK(dev, 1);
SMC_outw(dev, SMC_inw (dev, CTL_REG) | CTL_EEPROM_SELECT | CTL_RELOAD,
CTL_REG);
timeout = 100;
while((SMC_inw (dev, CTL_REG) & CTL_RELOAD) && --timeout)
udelay(100);
if (timeout == 0) {
printf("Timeout Reading EEPROM register %02x\n", reg);
return 0;
}
return SMC_inw (dev, GP_REG);
}
/*
. Function: smc_enable
. Purpose: let the chip talk to the outside work
. Method:
. 1. Enable the transmitter
. 2. Enable the receiver
. 3. Enable interrupts
*/
static void smc_enable(struct eth_device *dev)
{
PRINTK2("%s: smc_enable\n", SMC_DEV_NAME);
SMC_SELECT_BANK( dev, 0 );
/* see the header file for options in TCR/RCR DEFAULT*/
SMC_outw( dev, TCR_DEFAULT, TCR_REG );
SMC_outw( dev, RCR_DEFAULT, RCR_REG );
/* clear MII_DIS */
/* smc_write_phy_register(PHY_CNTL_REG, 0x0000); */
}
static void smc_reset(struct net_device *dev)
{
struct smc_local *lp = netdev_priv(dev);
void __iomem *ioaddr = lp->base;
unsigned int ctl, cfg;
struct sk_buff *pending_skb;
DBG(2, "%s: %s\n", dev->name, __func__);
spin_lock_irq(&lp->lock);
SMC_SELECT_BANK(lp, 2);
SMC_SET_INT_MASK(lp, 0);
pending_skb = lp->pending_tx_skb;
lp->pending_tx_skb = NULL;
spin_unlock_irq(&lp->lock);
if (pending_skb) {
dev_kfree_skb(pending_skb);
dev->stats.tx_errors++;
dev->stats.tx_aborted_errors++;
}
SMC_SELECT_BANK(lp, 0);
SMC_SET_RCR(lp, RCR_SOFTRST);
SMC_SELECT_BANK(lp, 1);
cfg = CONFIG_DEFAULT;
if (lp->cfg.flags & SMC91X_NOWAIT)
cfg |= CONFIG_NO_WAIT;
cfg |= CONFIG_EPH_POWER_EN;
SMC_SET_CONFIG(lp, cfg);
udelay(1);
SMC_SELECT_BANK(lp, 0);
SMC_SET_RCR(lp, RCR_CLEAR);
SMC_SET_TCR(lp, TCR_CLEAR);
SMC_SELECT_BANK(lp, 1);
ctl = SMC_GET_CTL(lp) | CTL_LE_ENABLE;
if(!THROTTLE_TX_PKTS)
ctl |= CTL_AUTO_RELEASE;
else
ctl &= ~CTL_AUTO_RELEASE;
SMC_SET_CTL(lp, ctl);
SMC_SELECT_BANK(lp, 2);
SMC_SET_MMU_CMD(lp, MC_RESET);
SMC_WAIT_MMU_BUSY(lp);
}
/*
* Writes a register to the MII Management serial interface
*/
static void smc_phy_write(struct net_device *dev, int phyaddr, int phyreg,
int phydata)
{
struct smc_local *lp = netdev_priv(dev);
void __iomem *ioaddr = lp->base;
SMC_SELECT_BANK(lp, 3);
/* Idle - 32 ones */
smc_mii_out(dev, 0xffffffff, 32);
/* Start code (01) + write (01) + phyaddr + phyreg + turnaround + phydata */
smc_mii_out(dev, 5 << 28 | phyaddr << 23 | phyreg << 18 | 2 << 16 | phydata, 32);
/* Return to idle state */
SMC_SET_MII(lp, SMC_GET_MII(lp) & ~(MII_MCLK|MII_MDOE|MII_MDO));
DBG(3, "%s: phyaddr=0x%x, phyreg=0x%x, phydata=0x%x\n",
__func__, phyaddr, phyreg, phydata);
SMC_SELECT_BANK(lp, 2);
}
static void smc_phy_write(struct net_device *dev, int phyaddr, int phyreg,
int phydata)
{
struct smc_local *lp = netdev_priv(dev);
void __iomem *ioaddr = lp->base;
SMC_SELECT_BANK(lp, 3);
smc_mii_out(dev, 0xffffffff, 32);
smc_mii_out(dev, 5 << 28 | phyaddr << 23 | phyreg << 18 | 2 << 16 | phydata, 32);
SMC_SET_MII(lp, SMC_GET_MII(lp) & ~(MII_MCLK|MII_MDOE|MII_MDO));
DBG(3, "%s: phyaddr=0x%x, phyreg=0x%x, phydata=0x%x\n",
__func__, phyaddr, phyreg, phydata);
SMC_SELECT_BANK(lp, 2);
}
static void smc_10bt_check_media(struct net_device *dev, int init)
{
struct smc_local *lp = netdev_priv(dev);
void __iomem *ioaddr = lp->base;
unsigned int old_carrier, new_carrier;
old_carrier = netif_carrier_ok(dev) ? 1 : 0;
SMC_SELECT_BANK(lp, 0);
new_carrier = (SMC_GET_EPH_STATUS(lp) & ES_LINK_OK) ? 1 : 0;
SMC_SELECT_BANK(lp, 2);
if (init || (old_carrier != new_carrier)) {
if (!new_carrier) {
netif_carrier_off(dev);
} else {
netif_carrier_on(dev);
}
if (netif_msg_link(lp))
printk(KERN_INFO "%s: link %s\n", dev->name,
new_carrier ? "up" : "down");
}
}
static int poll4int (byte mask, int timeout)
{
int tmo = get_timer (0) + timeout * CFG_HZ;
int is_timeout = 0;
word old_bank = SMC_inw (BSR_REG);
PRINTK2 ("Polling...\n");
SMC_SELECT_BANK (2);
while ((SMC_inw (SMC91111_INT_REG) & mask) == 0) {
if (get_timer (0) >= tmo) {
is_timeout = 1;
break;
}
}
/* restore old bank selection */
SMC_SELECT_BANK (old_bank);
if (is_timeout)
return 1;
else
return 0;
}
static int poll4int (struct eth_device *dev, byte mask, int timeout)
{
int tmo = get_timer (0) + timeout * CONFIG_SYS_HZ;
int is_timeout = 0;
word old_bank = SMC_inw (dev, BSR_REG);
PRINTK2 ("Polling...\n");
SMC_SELECT_BANK (dev, 2);
while ((SMC_inw (dev, SMC91111_INT_REG) & mask) == 0) {
if (get_timer (0) >= tmo) {
is_timeout = 1;
break;
}
}
/* restore old bank selection */
SMC_SELECT_BANK (dev, old_bank);
if (is_timeout)
return 1;
else
return 0;
}
/*
* Sets the PHY to a configuration as determined by the user
*/
static int smc_phy_fixed(struct net_device *dev)
{
struct smc_local *lp = netdev_priv(dev);
void __iomem *ioaddr = lp->base;
int phyaddr = lp->mii.phy_id;
int bmcr, cfg1;
DBG(3, "%s: %s\n", dev->name, __func__);
/* Enter Link Disable state */
cfg1 = smc_phy_read(dev, phyaddr, PHY_CFG1_REG);
cfg1 |= PHY_CFG1_LNKDIS;
smc_phy_write(dev, phyaddr, PHY_CFG1_REG, cfg1);
/*
* Set our fixed capabilities
* Disable auto-negotiation
*/
bmcr = 0;
if (lp->ctl_rfduplx)
bmcr |= BMCR_FULLDPLX;
if (lp->ctl_rspeed == 100)
bmcr |= BMCR_SPEED100;
/* Write our capabilities to the phy control register */
smc_phy_write(dev, phyaddr, MII_BMCR, bmcr);
/* Re-Configure the Receive/Phy Control register */
SMC_SELECT_BANK(lp, 0);
SMC_SET_RPC(lp, lp->rpc_cur_mode);
SMC_SELECT_BANK(lp, 2);
return 1;
}
static void smc_phy_check_media(struct net_device *dev, int init)
{
struct smc_local *lp = netdev_priv(dev);
void __iomem *ioaddr = lp->base;
if (mii_check_media(&lp->mii, netif_msg_link(lp), init)) {
if (lp->mii.full_duplex) {
lp->tcr_cur_mode |= TCR_SWFDUP;
} else {
lp->tcr_cur_mode &= ~TCR_SWFDUP;
}
SMC_SELECT_BANK(lp, 0);
SMC_SET_TCR(lp, lp->tcr_cur_mode);
}
}
static void smc_phy_configure(struct work_struct *work)
{
struct smc_local *lp =
container_of(work, struct smc_local, phy_configure);
struct net_device *dev = lp->dev;
void __iomem *ioaddr = lp->base;
int phyaddr = lp->mii.phy_id;
int my_phy_caps;
int my_ad_caps;
int status;
DBG(3, "%s:smc_program_phy()\n", dev->name);
spin_lock_irq(&lp->lock);
if (lp->phy_type == 0)
goto smc_phy_configure_exit;
if (smc_phy_reset(dev, phyaddr)) {
printk("%s: PHY reset timed out\n", dev->name);
goto smc_phy_configure_exit;
}
smc_phy_write(dev, phyaddr, PHY_MASK_REG,
PHY_INT_LOSSSYNC | PHY_INT_CWRD | PHY_INT_SSD |
PHY_INT_ESD | PHY_INT_RPOL | PHY_INT_JAB |
PHY_INT_SPDDET | PHY_INT_DPLXDET);
SMC_SELECT_BANK(lp, 0);
SMC_SET_RPC(lp, lp->rpc_cur_mode);
if (lp->mii.force_media) {
smc_phy_fixed(dev);
goto smc_phy_configure_exit;
}
my_phy_caps = smc_phy_read(dev, phyaddr, MII_BMSR);
if (!(my_phy_caps & BMSR_ANEGCAPABLE)) {
printk(KERN_INFO "Auto negotiation NOT supported\n");
smc_phy_fixed(dev);
goto smc_phy_configure_exit;
}
my_ad_caps = ADVERTISE_CSMA;
if (my_phy_caps & BMSR_100BASE4)
my_ad_caps |= ADVERTISE_100BASE4;
if (my_phy_caps & BMSR_100FULL)
my_ad_caps |= ADVERTISE_100FULL;
if (my_phy_caps & BMSR_100HALF)
my_ad_caps |= ADVERTISE_100HALF;
if (my_phy_caps & BMSR_10FULL)
my_ad_caps |= ADVERTISE_10FULL;
if (my_phy_caps & BMSR_10HALF)
my_ad_caps |= ADVERTISE_10HALF;
if (lp->ctl_rspeed != 100)
my_ad_caps &= ~(ADVERTISE_100BASE4|ADVERTISE_100FULL|ADVERTISE_100HALF);
if (!lp->ctl_rfduplx)
my_ad_caps &= ~(ADVERTISE_100FULL|ADVERTISE_10FULL);
smc_phy_write(dev, phyaddr, MII_ADVERTISE, my_ad_caps);
lp->mii.advertising = my_ad_caps;
status = smc_phy_read(dev, phyaddr, MII_ADVERTISE);
DBG(2, "%s: phy caps=%x\n", dev->name, my_phy_caps);
DBG(2, "%s: phy advertised caps=%x\n", dev->name, my_ad_caps);
smc_phy_write(dev, phyaddr, MII_BMCR, BMCR_ANENABLE | BMCR_ANRESTART);
smc_phy_check_media(dev, 1);
smc_phy_configure_exit:
SMC_SELECT_BANK(lp, 2);
spin_unlock_irq(&lp->lock);
}
void
snstart(struct ifnet *ifp, struct ifaltq_subque *ifsq)
{
struct sn_softc *sc = ifp->if_softc;
u_int len;
struct mbuf *m;
struct mbuf *top;
int pad;
int mask;
u_short length;
u_short numPages;
u_char packet_no;
int time_out;
ASSERT_ALTQ_SQ_DEFAULT(ifp, ifsq);
if ((ifp->if_flags & IFF_RUNNING) == 0 || ifq_is_oactive(&ifp->if_snd))
return;
if (sc->pages_wanted != -1) {
/* XXX should never happen */
kprintf("%s: snstart() while memory allocation pending\n",
ifp->if_xname);
ifq_set_oactive(&ifp->if_snd);
return;
}
startagain:
/*
* Sneak a peek at the next packet
*/
m = ifq_dequeue(&ifp->if_snd);
if (m == NULL)
return;
/*
* Compute the frame length and set pad to give an overall even
* number of bytes. Below we assume that the packet length is even.
*/
for (len = 0, top = m; m; m = m->m_next)
len += m->m_len;
pad = (len & 1);
/*
* We drop packets that are too large. Perhaps we should truncate
* them instead?
*/
if (len + pad > ETHER_MAX_LEN - ETHER_CRC_LEN) {
kprintf("%s: large packet discarded (A)\n", ifp->if_xname);
IFNET_STAT_INC(&sc->arpcom.ac_if, oerrors, 1);
m_freem(top);
goto readcheck;
}
#ifdef SW_PAD
/*
* If HW padding is not turned on, then pad to ETHER_MIN_LEN.
*/
if (len < ETHER_MIN_LEN - ETHER_CRC_LEN)
pad = ETHER_MIN_LEN - ETHER_CRC_LEN - len;
#endif /* SW_PAD */
length = pad + len;
/*
* The MMU wants the number of pages to be the number of 256 byte
* 'pages', minus 1 (A packet can't ever have 0 pages. We also
* include space for the status word, byte count and control bytes in
* the allocation request.
*/
numPages = (length + 6) >> 8;
/*
* Now, try to allocate the memory
*/
SMC_SELECT_BANK(2);
outw(BASE + MMU_CMD_REG_W, MMUCR_ALLOC | numPages);
/*
* Wait a short amount of time to see if the allocation request
* completes. Otherwise, I enable the interrupt and wait for
* completion asyncronously.
*/
time_out = MEMORY_WAIT_TIME;
do {
if (inb(BASE + INTR_STAT_REG_B) & IM_ALLOC_INT)
break;
} while (--time_out);
if (!time_out) {
/*
* No memory now. Oh well, wait until the chip finds memory
* later. Remember how many pages we were asking for and
* enable the allocation completion interrupt. Also set a
* watchdog in case we miss the interrupt. We mark the
* interface active since there is no point in attempting an
* snstart() until after the memory is available.
*/
mask = inb(BASE + INTR_MASK_REG_B) | IM_ALLOC_INT;
outb(BASE + INTR_MASK_REG_B, mask);
sc->intr_mask = mask;
ifp->if_timer = 1;
ifq_set_oactive(&ifp->if_snd);
sc->pages_wanted = numPages;
ifq_prepend(&ifp->if_snd, top);
return;
}
/*
* The memory allocation completed. Check the results.
*/
packet_no = inb(BASE + ALLOC_RESULT_REG_B);
if (packet_no & ARR_FAILED) {
kprintf("%s: Memory allocation failed\n", ifp->if_xname);
ifq_prepend(&ifp->if_snd, top);
goto startagain;
}
/*
* We have a packet number, so tell the card to use it.
*/
outb(BASE + PACKET_NUM_REG_B, packet_no);
/*
* Point to the beginning of the packet
*/
outw(BASE + POINTER_REG_W, PTR_AUTOINC | 0x0000);
/*
* Send the packet length (+6 for status, length and control byte)
* and the status word (set to zeros)
*/
outw(BASE + DATA_REG_W, 0);
outb(BASE + DATA_REG_B, (length + 6) & 0xFF);
outb(BASE + DATA_REG_B, (length + 6) >> 8);
/*
* Push out the data to the card.
*/
for (m = top; m != NULL; m = m->m_next) {
/*
* Push out words.
*/
outsw(BASE + DATA_REG_W, mtod(m, caddr_t), m->m_len / 2);
/*
* Push out remaining byte.
*/
if (m->m_len & 1)
outb(BASE + DATA_REG_B, *(mtod(m, caddr_t) + m->m_len - 1));
}
/*
* Push out padding.
*/
while (pad > 1) {
outw(BASE + DATA_REG_W, 0);
pad -= 2;
}
if (pad)
outb(BASE + DATA_REG_B, 0);
/*
* Push out control byte and unused packet byte The control byte is 0
* meaning the packet is even lengthed and no special CRC handling is
* desired.
*/
outw(BASE + DATA_REG_W, 0);
/*
* Enable the interrupts and let the chipset deal with it Also set a
* watchdog in case we miss the interrupt.
*/
mask = inb(BASE + INTR_MASK_REG_B) | (IM_TX_INT | IM_TX_EMPTY_INT);
outb(BASE + INTR_MASK_REG_B, mask);
sc->intr_mask = mask;
outw(BASE + MMU_CMD_REG_W, MMUCR_ENQUEUE);
ifq_set_oactive(&ifp->if_snd);
ifp->if_timer = 1;
BPF_MTAP(ifp, top);
IFNET_STAT_INC(ifp, opackets, 1);
m_freem(top);
readcheck:
/*
* Is another packet coming in? We don't want to overflow the tiny
* RX FIFO. If nothing has arrived then attempt to queue another
* transmit packet.
*/
if (inw(BASE + FIFO_PORTS_REG_W) & FIFO_REMPTY)
goto startagain;
}
/* Resume a packet transmit operation after a memory allocation
* has completed.
*
* This is basically a hacked up copy of snstart() which handles
* a completed memory allocation the same way snstart() does.
* It then passes control to snstart to handle any other queued
* packets.
*/
static void
snresume(struct ifnet *ifp)
{
struct sn_softc *sc = ifp->if_softc;
u_int len;
struct mbuf *m;
struct mbuf *top;
int pad;
int mask;
u_short length;
u_short numPages;
u_short pages_wanted;
u_char packet_no;
if (sc->pages_wanted < 0)
return;
pages_wanted = sc->pages_wanted;
sc->pages_wanted = -1;
/*
* Sneak a peek at the next packet
*/
m = ifq_dequeue(&ifp->if_snd);
if (m == NULL) {
kprintf("%s: snresume() with nothing to send\n",
ifp->if_xname);
return;
}
/*
* Compute the frame length and set pad to give an overall even
* number of bytes. Below we assume that the packet length is even.
*/
for (len = 0, top = m; m; m = m->m_next)
len += m->m_len;
pad = (len & 1);
/*
* We drop packets that are too large. Perhaps we should truncate
* them instead?
*/
if (len + pad > ETHER_MAX_LEN - ETHER_CRC_LEN) {
kprintf("%s: large packet discarded (B)\n", ifp->if_xname);
IFNET_STAT_INC(ifp, oerrors, 1);
m_freem(top);
return;
}
#ifdef SW_PAD
/*
* If HW padding is not turned on, then pad to ETHER_MIN_LEN.
*/
if (len < ETHER_MIN_LEN - ETHER_CRC_LEN)
pad = ETHER_MIN_LEN - ETHER_CRC_LEN - len;
#endif /* SW_PAD */
length = pad + len;
/*
* The MMU wants the number of pages to be the number of 256 byte
* 'pages', minus 1 (A packet can't ever have 0 pages. We also
* include space for the status word, byte count and control bytes in
* the allocation request.
*/
numPages = (length + 6) >> 8;
SMC_SELECT_BANK(2);
/*
* The memory allocation completed. Check the results. If it failed,
* we simply set a watchdog timer and hope for the best.
*/
packet_no = inb(BASE + ALLOC_RESULT_REG_B);
if (packet_no & ARR_FAILED) {
kprintf("%s: Memory allocation failed. Weird.\n", ifp->if_xname);
ifp->if_timer = 1;
ifq_prepend(&ifp->if_snd, top);
goto try_start;
}
/*
* We have a packet number, so tell the card to use it.
*/
outb(BASE + PACKET_NUM_REG_B, packet_no);
/*
* Now, numPages should match the pages_wanted recorded when the
* memory allocation was initiated.
*/
if (pages_wanted != numPages) {
kprintf("%s: memory allocation wrong size. Weird.\n", ifp->if_xname);
/*
* If the allocation was the wrong size we simply release the
* memory once it is granted. Wait for the MMU to be un-busy.
*/
while (inw(BASE + MMU_CMD_REG_W) & MMUCR_BUSY) /* NOTHING */
;
outw(BASE + MMU_CMD_REG_W, MMUCR_FREEPKT);
ifq_prepend(&ifp->if_snd, top);
return;
}
/*
* Point to the beginning of the packet
*/
outw(BASE + POINTER_REG_W, PTR_AUTOINC | 0x0000);
/*
* Send the packet length (+6 for status, length and control byte)
* and the status word (set to zeros)
*/
outw(BASE + DATA_REG_W, 0);
outb(BASE + DATA_REG_B, (length + 6) & 0xFF);
outb(BASE + DATA_REG_B, (length + 6) >> 8);
/*
* Push out the data to the card.
*/
for (m = top; m != NULL; m = m->m_next) {
/*
* Push out words.
*/
outsw(BASE + DATA_REG_W, mtod(m, caddr_t), m->m_len / 2);
/*
* Push out remaining byte.
*/
if (m->m_len & 1)
outb(BASE + DATA_REG_B, *(mtod(m, caddr_t) + m->m_len - 1));
}
/*
* Push out padding.
*/
while (pad > 1) {
outw(BASE + DATA_REG_W, 0);
pad -= 2;
}
if (pad)
outb(BASE + DATA_REG_B, 0);
/*
* Push out control byte and unused packet byte The control byte is 0
* meaning the packet is even lengthed and no special CRC handling is
* desired.
*/
outw(BASE + DATA_REG_W, 0);
/*
* Enable the interrupts and let the chipset deal with it Also set a
* watchdog in case we miss the interrupt.
*/
mask = inb(BASE + INTR_MASK_REG_B) | (IM_TX_INT | IM_TX_EMPTY_INT);
outb(BASE + INTR_MASK_REG_B, mask);
sc->intr_mask = mask;
outw(BASE + MMU_CMD_REG_W, MMUCR_ENQUEUE);
BPF_MTAP(ifp, top);
IFNET_STAT_INC(ifp, opackets, 1);
m_freem(top);
try_start:
/*
* Now pass control to snstart() to queue any additional packets
*/
ifq_clr_oactive(&ifp->if_snd);
if_devstart(ifp);
/*
* We've sent something, so we're active. Set a watchdog in case the
* TX_EMPTY interrupt is lost.
*/
ifq_set_oactive(&ifp->if_snd);
ifp->if_timer = 1;
}
void
sn_intr(void *arg)
{
int status, interrupts;
struct sn_softc *sc = (struct sn_softc *) arg;
struct ifnet *ifp = &sc->arpcom.ac_if;
/*
* Chip state registers
*/
u_char mask;
u_char packet_no;
u_short tx_status;
u_short card_stats;
/*
* Clear the watchdog.
*/
ifp->if_timer = 0;
SMC_SELECT_BANK(2);
/*
* Obtain the current interrupt mask and clear the hardware mask
* while servicing interrupts.
*/
mask = inb(BASE + INTR_MASK_REG_B);
outb(BASE + INTR_MASK_REG_B, 0x00);
/*
* Get the set of interrupts which occurred and eliminate any which
* are masked.
*/
interrupts = inb(BASE + INTR_STAT_REG_B);
status = interrupts & mask;
/*
* Now, process each of the interrupt types.
*/
/*
* Receive Overrun.
*/
if (status & IM_RX_OVRN_INT) {
/*
* Acknowlege Interrupt
*/
SMC_SELECT_BANK(2);
outb(BASE + INTR_ACK_REG_B, IM_RX_OVRN_INT);
IFNET_STAT_INC(&sc->arpcom.ac_if, ierrors, 1);
}
/*
* Got a packet.
*/
if (status & IM_RCV_INT) {
#if 1
int packet_number;
SMC_SELECT_BANK(2);
packet_number = inw(BASE + FIFO_PORTS_REG_W);
if (packet_number & FIFO_REMPTY) {
/*
* we got called , but nothing was on the FIFO
*/
kprintf("sn: Receive interrupt with nothing on FIFO\n");
goto out;
}
#endif
snread(ifp);
}
/*
* An on-card memory allocation came through.
*/
if (status & IM_ALLOC_INT) {
/*
* Disable this interrupt.
*/
mask &= ~IM_ALLOC_INT;
ifq_clr_oactive(&sc->arpcom.ac_if.if_snd);
snresume(&sc->arpcom.ac_if);
}
/*
* TX Completion. Handle a transmit error message. This will only be
* called when there is an error, because of the AUTO_RELEASE mode.
*/
if (status & IM_TX_INT) {
/*
* Acknowlege Interrupt
*/
SMC_SELECT_BANK(2);
outb(BASE + INTR_ACK_REG_B, IM_TX_INT);
packet_no = inw(BASE + FIFO_PORTS_REG_W);
packet_no &= FIFO_TX_MASK;
/*
* select this as the packet to read from
*/
outb(BASE + PACKET_NUM_REG_B, packet_no);
/*
* Position the pointer to the first word from this packet
*/
outw(BASE + POINTER_REG_W, PTR_AUTOINC | PTR_READ | 0x0000);
/*
* Fetch the TX status word. The value found here will be a
* copy of the EPH_STATUS_REG_W at the time the transmit
* failed.
*/
tx_status = inw(BASE + DATA_REG_W);
if (tx_status & EPHSR_TX_SUC) {
device_printf(sc->dev,
"Successful packet caused interrupt\n");
} else {
IFNET_STAT_INC(&sc->arpcom.ac_if, oerrors, 1);
}
if (tx_status & EPHSR_LATCOL)
IFNET_STAT_INC(&sc->arpcom.ac_if, collisions, 1);
/*
* Some of these errors will have disabled transmit.
* Re-enable transmit now.
*/
SMC_SELECT_BANK(0);
#ifdef SW_PAD
outw(BASE + TXMIT_CONTROL_REG_W, TCR_ENABLE);
#else
outw(BASE + TXMIT_CONTROL_REG_W, TCR_ENABLE | TCR_PAD_ENABLE);
#endif /* SW_PAD */
/*
* kill the failed packet. Wait for the MMU to be un-busy.
*/
SMC_SELECT_BANK(2);
while (inw(BASE + MMU_CMD_REG_W) & MMUCR_BUSY) /* NOTHING */
;
outw(BASE + MMU_CMD_REG_W, MMUCR_FREEPKT);
/*
* Attempt to queue more transmits.
*/
ifq_clr_oactive(&sc->arpcom.ac_if.if_snd);
if_devstart(&sc->arpcom.ac_if);
}
/*
* Transmit underrun. We use this opportunity to update transmit
* statistics from the card.
*/
if (status & IM_TX_EMPTY_INT) {
/*
* Acknowlege Interrupt
*/
SMC_SELECT_BANK(2);
outb(BASE + INTR_ACK_REG_B, IM_TX_EMPTY_INT);
/*
* Disable this interrupt.
*/
mask &= ~IM_TX_EMPTY_INT;
SMC_SELECT_BANK(0);
card_stats = inw(BASE + COUNTER_REG_W);
/*
* Single collisions
*/
IFNET_STAT_INC(&sc->arpcom.ac_if, collisions,
card_stats & ECR_COLN_MASK);
/*
* Multiple collisions
*/
IFNET_STAT_INC(&sc->arpcom.ac_if, collisions,
(card_stats & ECR_MCOLN_MASK) >> 4);
SMC_SELECT_BANK(2);
/*
* Attempt to enqueue some more stuff.
*/
ifq_clr_oactive(&sc->arpcom.ac_if.if_snd);
if_devstart(&sc->arpcom.ac_if);
}
static irqreturn_t smc_interrupt(int irq, void *dev_id)
{
struct net_device *dev = dev_id;
struct smc_local *lp = netdev_priv(dev);
void __iomem *ioaddr = lp->base;
int status, mask, timeout, card_stats;
int saved_pointer;
DBG(3, "%s: %s\n", dev->name, __func__);
spin_lock(&lp->lock);
SMC_INTERRUPT_PREAMBLE;
saved_pointer = SMC_GET_PTR(lp);
mask = SMC_GET_INT_MASK(lp);
SMC_SET_INT_MASK(lp, 0);
timeout = MAX_IRQ_LOOPS;
do {
status = SMC_GET_INT(lp);
DBG(2, "%s: INT 0x%02x MASK 0x%02x MEM 0x%04x FIFO 0x%04x\n",
dev->name, status, mask,
({ int meminfo; SMC_SELECT_BANK(lp, 0);
meminfo = SMC_GET_MIR(lp);
SMC_SELECT_BANK(lp, 2); meminfo; }),
SMC_GET_FIFO(lp));
status &= mask;
if (!status)
break;
if (status & IM_TX_INT) {
DBG(3, "%s: TX int\n", dev->name);
smc_tx(dev);
SMC_ACK_INT(lp, IM_TX_INT);
if (THROTTLE_TX_PKTS)
netif_wake_queue(dev);
} else if (status & IM_RCV_INT) {
DBG(3, "%s: RX irq\n", dev->name);
smc_rcv(dev);
} else if (status & IM_ALLOC_INT) {
DBG(3, "%s: Allocation irq\n", dev->name);
tasklet_hi_schedule(&lp->tx_task);
mask &= ~IM_ALLOC_INT;
} else if (status & IM_TX_EMPTY_INT) {
DBG(3, "%s: TX empty\n", dev->name);
mask &= ~IM_TX_EMPTY_INT;
SMC_SELECT_BANK(lp, 0);
card_stats = SMC_GET_COUNTER(lp);
SMC_SELECT_BANK(lp, 2);
dev->stats.collisions += card_stats & 0xF;
card_stats >>= 4;
dev->stats.collisions += card_stats & 0xF;
} else if (status & IM_RX_OVRN_INT) {
/*
. Function: smc_send(struct net_device * )
. Purpose:
. This sends the actual packet to the SMC9xxx chip.
.
. Algorithm:
. First, see if a saved_skb is available.
. ( this should NOT be called if there is no 'saved_skb'
. Now, find the packet number that the chip allocated
. Point the data pointers at it in memory
. Set the length word in the chip's memory
. Dump the packet to chip memory
. Check if a last byte is needed ( odd length packet )
. if so, set the control flag right
. Tell the card to send it
. Enable the transmit interrupt, so I know if it failed
. Free the kernel data if I actually sent it.
*/
static int smc_send(struct eth_device *dev, void *packet, int packet_length)
{
byte packet_no;
byte *buf;
int length;
int numPages;
int try = 0;
int time_out;
byte status;
byte saved_pnr;
word saved_ptr;
/* save PTR and PNR registers before manipulation */
SMC_SELECT_BANK (dev, 2);
saved_pnr = SMC_inb( dev, PN_REG );
saved_ptr = SMC_inw( dev, PTR_REG );
PRINTK3 ("%s: smc_hardware_send_packet\n", SMC_DEV_NAME);
length = ETH_ZLEN < packet_length ? packet_length : ETH_ZLEN;
/* allocate memory
** The MMU wants the number of pages to be the number of 256 bytes
** 'pages', minus 1 ( since a packet can't ever have 0 pages :) )
**
** The 91C111 ignores the size bits, but the code is left intact
** for backwards and future compatibility.
**
** Pkt size for allocating is data length +6 (for additional status
** words, length and ctl!)
**
** If odd size then last byte is included in this header.
*/
numPages = ((length & 0xfffe) + 6);
numPages >>= 8; /* Divide by 256 */
if (numPages > 7) {
printf ("%s: Far too big packet error. \n", SMC_DEV_NAME);
return 0;
}
/* now, try to allocate the memory */
SMC_SELECT_BANK (dev, 2);
SMC_outw (dev, MC_ALLOC | numPages, MMU_CMD_REG);
/* FIXME: the ALLOC_INT bit never gets set *
* so the following will always give a *
* memory allocation error. *
* same code works in armboot though *
* -ro
*/
again:
try++;
time_out = MEMORY_WAIT_TIME;
do {
status = SMC_inb (dev, SMC91111_INT_REG);
if (status & IM_ALLOC_INT) {
/* acknowledge the interrupt */
SMC_outb (dev, IM_ALLOC_INT, SMC91111_INT_REG);
break;
}
} while (--time_out);
if (!time_out) {
PRINTK2 ("%s: memory allocation, try %d failed ...\n",
SMC_DEV_NAME, try);
if (try < SMC_ALLOC_MAX_TRY)
goto again;
else
return 0;
}
