bool
isl_has_matching_typed_storage_image_format(const struct gen_device_info *devinfo,
enum isl_format fmt)
{
if (devinfo->gen >= 9) {
return true;
} else if (devinfo->gen >= 8 || devinfo->is_haswell) {
return isl_format_get_layout(fmt)->bpb <= 64;
} else {
return isl_format_get_layout(fmt)->bpb <= 32;
}
}
void
blorp_ccs_resolve(struct blorp_batch *batch,
struct blorp_surf *surf, enum isl_format format)
{
struct blorp_params params;
blorp_params_init(¶ms);
brw_blorp_surface_info_init(batch->blorp, ¶ms.dst, surf,
0 /* level */, 0 /* layer */, format, true);
/* From the Ivy Bridge PRM, Vol2 Part1 11.9 "Render Target Resolve":
*
* A rectangle primitive must be scaled down by the following factors
* with respect to render target being resolved.
*
* The scaledown factors in the table that follows are related to the block
* size of the CCS format. For IVB and HSW, we divide by two, for BDW we
* multiply by 8 and 16. On Sky Lake, we multiply by 8.
*/
const struct isl_format_layout *aux_fmtl =
isl_format_get_layout(params.dst.aux_surf.format);
assert(aux_fmtl->txc == ISL_TXC_CCS);
unsigned x_scaledown, y_scaledown;
if (ISL_DEV_GEN(batch->blorp->isl_dev) >= 9) {
x_scaledown = aux_fmtl->bw * 8;
y_scaledown = aux_fmtl->bh * 8;
} else if (ISL_DEV_GEN(batch->blorp->isl_dev) >= 8) {
x_scaledown = aux_fmtl->bw * 8;
y_scaledown = aux_fmtl->bh * 16;
} else {
x_scaledown = aux_fmtl->bw / 2;
y_scaledown = aux_fmtl->bh / 2;
}
params.x0 = params.y0 = 0;
params.x1 = params.dst.aux_surf.logical_level0_px.width;
params.y1 = params.dst.aux_surf.logical_level0_px.height;
params.x1 = ALIGN(params.x1, x_scaledown) / x_scaledown;
params.y1 = ALIGN(params.y1, y_scaledown) / y_scaledown;
if (batch->blorp->isl_dev->info->gen >= 9) {
if (params.dst.aux_usage == ISL_AUX_USAGE_CCS_E)
params.fast_clear_op = BLORP_FAST_CLEAR_OP_RESOLVE_FULL;
else
params.fast_clear_op = BLORP_FAST_CLEAR_OP_RESOLVE_PARTIAL;
} else {
/* Broadwell and earlier do not have a partial resolve */
params.fast_clear_op = BLORP_FAST_CLEAR_OP_RESOLVE_FULL;
}
/* Note: there is no need to initialize push constants because it doesn't
* matter what data gets dispatched to the render target. However, we must
* ensure that the fragment shader delivers the data using the "replicated
* color" message.
*/
blorp_params_get_clear_kernel(batch->blorp, ¶ms, true);
batch->blorp->exec(batch, ¶ms);
}
/* The x0, y0, x1, and y1 parameters must already be populated with the render
* area of the framebuffer to be cleared.
*/
static void
get_fast_clear_rect(const struct isl_device *dev,
const struct isl_surf *aux_surf,
unsigned *x0, unsigned *y0,
unsigned *x1, unsigned *y1)
{
unsigned int x_align, y_align;
unsigned int x_scaledown, y_scaledown;
/* Only single sampled surfaces need to (and actually can) be resolved. */
if (aux_surf->usage == ISL_SURF_USAGE_CCS_BIT) {
/* From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render
* Target(s)", beneath the "Fast Color Clear" bullet (p327):
*
* Clear pass must have a clear rectangle that must follow
* alignment rules in terms of pixels and lines as shown in the
* table below. Further, the clear-rectangle height and width
* must be multiple of the following dimensions. If the height
* and width of the render target being cleared do not meet these
* requirements, an MCS buffer can be created such that it
* follows the requirement and covers the RT.
*
* The alignment size in the table that follows is related to the
* alignment size that is baked into the CCS surface format but with X
* alignment multiplied by 16 and Y alignment multiplied by 32.
*/
x_align = isl_format_get_layout(aux_surf->format)->bw;
y_align = isl_format_get_layout(aux_surf->format)->bh;
x_align *= 16;
/* SKL+ line alignment requirement for Y-tiled are half those of the prior
* generations.
*/
if (dev->info->gen >= 9)
y_align *= 16;
else
y_align *= 32;
/* From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render
* Target(s)", beneath the "Fast Color Clear" bullet (p327):
*
* In order to optimize the performance MCS buffer (when bound to
* 1X RT) clear similarly to MCS buffer clear for MSRT case,
* clear rect is required to be scaled by the following factors
* in the horizontal and vertical directions:
*
* The X and Y scale down factors in the table that follows are each
* equal to half the alignment value computed above.
*/
x_scaledown = x_align / 2;
y_scaledown = y_align / 2;
/* From BSpec: 3D-Media-GPGPU Engine > 3D Pipeline > Pixel > Pixel
* Backend > MCS Buffer for Render Target(s) [DevIVB+] > Table "Color
* Clear of Non-MultiSampled Render Target Restrictions":
*
* Clear rectangle must be aligned to two times the number of
* pixels in the table shown below due to 16x16 hashing across the
* slice.
*/
x_align *= 2;
y_align *= 2;
} else {
assert(aux_surf->usage == ISL_SURF_USAGE_MCS_BIT);
/* From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render
* Target(s)", beneath the "MSAA Compression" bullet (p326):
*
* Clear pass for this case requires that scaled down primitive
* is sent down with upper left co-ordinate to coincide with
* actual rectangle being cleared. For MSAA, clear rectangle’s
* height and width need to as show in the following table in
* terms of (width,height) of the RT.
*
* MSAA Width of Clear Rect Height of Clear Rect
* 2X Ceil(1/8*width) Ceil(1/2*height)
* 4X Ceil(1/8*width) Ceil(1/2*height)
* 8X Ceil(1/2*width) Ceil(1/2*height)
* 16X width Ceil(1/2*height)
*
* The text "with upper left co-ordinate to coincide with actual
* rectangle being cleared" is a little confusing--it seems to imply
* that to clear a rectangle from (x,y) to (x+w,y+h), one needs to
* feed the pipeline using the rectangle (x,y) to
* (x+Ceil(w/N),y+Ceil(h/2)), where N is either 2 or 8 depending on
* the number of samples. Experiments indicate that this is not
* quite correct; actually, what the hardware appears to do is to
* align whatever rectangle is sent down the pipeline to the nearest
* multiple of 2x2 blocks, and then scale it up by a factor of N
* horizontally and 2 vertically. So the resulting alignment is 4
* vertically and either 4 or 16 horizontally, and the scaledown
* factor is 2 vertically and either 2 or 8 horizontally.
*/
switch (aux_surf->format) {
case ISL_FORMAT_MCS_2X:
case ISL_FORMAT_MCS_4X:
x_scaledown = 8;
break;
case ISL_FORMAT_MCS_8X:
x_scaledown = 2;
break;
case ISL_FORMAT_MCS_16X:
x_scaledown = 1;
break;
default:
unreachable("Unexpected MCS format for fast clear");
}
y_scaledown = 2;
x_align = x_scaledown * 2;
y_align = y_scaledown * 2;
}
*x0 = ROUND_DOWN_TO(*x0, x_align) / x_scaledown;
*y0 = ROUND_DOWN_TO(*y0, y_align) / y_scaledown;
*x1 = ALIGN(*x1, x_align) / x_scaledown;
*y1 = ALIGN(*y1, y_align) / y_scaledown;
}
void
isl_surf_fill_image_param(const struct isl_device *dev,
struct brw_image_param *param,
const struct isl_surf *surf,
const struct isl_view *view)
{
*param = image_param_defaults;
param->size[0] = isl_minify(surf->logical_level0_px.w, view->base_level);
param->size[1] = isl_minify(surf->logical_level0_px.h, view->base_level);
if (surf->dim == ISL_SURF_DIM_3D) {
param->size[2] = isl_minify(surf->logical_level0_px.d, view->base_level);
} else {
param->size[2] = surf->logical_level0_px.array_len -
view->base_array_layer;
}
isl_surf_get_image_offset_el(surf, view->base_level,
surf->dim == ISL_SURF_DIM_3D ?
0 : view->base_array_layer,
surf->dim == ISL_SURF_DIM_3D ?
view->base_array_layer : 0,
¶m->offset[0], ¶m->offset[1]);
const int cpp = isl_format_get_layout(surf->format)->bpb / 8;
param->stride[0] = cpp;
param->stride[1] = surf->row_pitch / cpp;
const struct isl_extent3d image_align_sa =
isl_surf_get_image_alignment_sa(surf);
if (ISL_DEV_GEN(dev) < 9 && surf->dim == ISL_SURF_DIM_3D) {
param->stride[2] = isl_align_npot(param->size[0], image_align_sa.w);
param->stride[3] = isl_align_npot(param->size[1], image_align_sa.h);
} else {
param->stride[2] = 0;
param->stride[3] = isl_surf_get_array_pitch_el_rows(surf);
}
switch (surf->tiling) {
case ISL_TILING_LINEAR:
/* image_param_defaults is good enough */
break;
case ISL_TILING_X:
/* An X tile is a rectangular block of 512x8 bytes. */
param->tiling[0] = isl_log2u(512 / cpp);
param->tiling[1] = isl_log2u(8);
if (dev->has_bit6_swizzling) {
/* Right shifts required to swizzle bits 9 and 10 of the memory
* address with bit 6.
*/
param->swizzling[0] = 3;
param->swizzling[1] = 4;
}
break;
case ISL_TILING_Y0:
/* The layout of a Y-tiled surface in memory isn't really fundamentally
* different to the layout of an X-tiled surface, we simply pretend that
* the surface is broken up in a number of smaller 16Bx32 tiles, each
* one arranged in X-major order just like is the case for X-tiling.
*/
param->tiling[0] = isl_log2u(16 / cpp);
param->tiling[1] = isl_log2u(32);
if (dev->has_bit6_swizzling) {
/* Right shift required to swizzle bit 9 of the memory address with
* bit 6.
*/
param->swizzling[0] = 3;
param->swizzling[1] = 0xff;
}
break;
default:
assert(!"Unhandled storage image tiling");
}
/* 3D textures are arranged in 2D in memory with 2^lod slices per row. The
* address calculation algorithm (emit_address_calculation() in
* brw_fs_surface_builder.cpp) handles this as a sort of tiling with
* modulus equal to the LOD.
*/
param->tiling[2] = (ISL_DEV_GEN(dev) < 9 && surf->dim == ISL_SURF_DIM_3D ?
view->base_level : 0);
}
