int callMonitor(int mon, int ctrlbyt, int accu, int faddr, int laddr) {
int SP;
image[ CTRLBYT ] = ctrlbyt; // CTRLBYT BIT 6 = 1 = > mass erase
image[ CPUSPD ] = CPUSPEED; // CPUSPD = 16 MHz ext clock = > 4 MHz Fbus speed = > 8
if (verbose>3)
flsprintf(stdout,"CPUSPEED=%02X\n",CPUSPEED);
image[ LADDR ] = laddr>>8;
image[ LADDR+1 ] = laddr&0xFF;
writeMemory(MONDATA, 4, 0);
if (WORKRAM>0xFF) {
flsprintf(stderr,"Work RAM must be on zero page\n");
abort();
}
if (lastMon!=mon) {
// construct small HC908 code fragment to call the monitor function and return results
int i = WORKRAM;
image[ i++ ] = 0xCD; // JSR mon ; calls the monitor routine
image[ i++ ] = mon>>8;
image[ i++ ] = mon&0xFF;
image[ i++ ] = 0x83; // SWI ; return to monitor
if (WORKRAM>=WORKTOP) { // leave some stack space for monitor routines
flsprintf(stderr,"Not enough WORKRAM on target\n");
abort();
}
writeMemory(WORKRAM , i-WORKRAM , 0);
lastMon=mon;
}
void TED7360::reset(bool cold_reset)
{
if (cold_reset) {
// reset TED registers
this->initRegisters();
// make sure that RAM size is detected correctly
for (uint8_t j = 0xC0; j < 0xFF; j++) {
if ((j & uint8_t(0x02)) != uint8_t(0) &&
!(j == uint8_t(0xFE) && segmentTable[0xFC] == (uint8_t *) 0))
continue;
if (segmentTable[j] != (uint8_t *) 0) {
for (uint16_t i = 0x3FFD; i > 0x3FF5; i--) {
if (segmentTable[j][i] != readMemory(i | 0xC000))
break;
if (i == 0x3FF6) {
segmentTable[j][i] =
(segmentTable[j][i] + uint8_t(1)) & uint8_t(0xFF);
}
}
}
}
// force RAM testing
writeMemory(0x0508, 0x00);
}
// reset ROM banking
writeMemory(0xFDD0, 0x00);
// reset CPU
writeMemory(0x0000, 0x00);
writeMemory(0x0001, 0x00);
M7501::reset(cold_reset);
}
//
// Execute will execute the code in the target process/thread,
// the techinique for PTRACE is to read CPU state, rewrite the
// code portion pointed by PC with the code, resuming the process/thread,
// wait for the completion, read the CPU state back to grab return
// values, then restoring the previous code.
//
ErrorCode PTrace::execute(ProcessThreadId const &ptid, ProcessInfo const &pinfo,
void const *code, size_t length, uint64_t &result) {
Architecture::CPUState savedState, resultState;
std::string savedCode;
if (!ptid.valid() || code == nullptr || length == 0)
return kErrorInvalidArgument;
// 1. Read and save the CPU state
ErrorCode error = readCPUState(ptid, pinfo, savedState);
if (error != kSuccess)
return error;
// 2. Copy the code at PC
savedCode.resize(length);
error = readMemory(ptid, savedState.pc(), &savedCode[0], length);
if (error != kSuccess)
return error;
// 3. Write the code to execute at PC
error = writeMemory(ptid, savedState.pc(), code, length);
if (error != kSuccess)
goto fail;
// 3. Resume and wait
error = resume(ptid, pinfo);
if (error == kSuccess) {
error = wait(ptid);
}
if (error == kSuccess) {
// 4. Read back the CPU state
error = readCPUState(ptid, pinfo, resultState);
if (error == kSuccess) {
// 5. Save the result
result = resultState.retval();
}
}
// 6. Write back the old code
error = writeMemory(ptid, savedState.pc(), &savedCode[0], length);
if (error != kSuccess)
goto fail;
// 7. Restore CPU state
error = writeCPUState(ptid, pinfo, savedState);
if (error != kSuccess)
goto fail;
// Success!! We injected and executed code!
return kSuccess;
fail:
return kill(ptid, SIGKILL); // we can't really do much at this point :(
}
void LMVCache::displaceLine(CacheLine *cl)
{
if (cl->isInvalid())
return;
wrLVIDEnergy->inc();
if (cl->accessLine()) {
// The cache may be killed or restarted. The cache line state must be
// updated accordingly
I(cl->isInvalid());
return;
}
if (!cl->isSafe()) {
#ifdef TS_TIMELINE
TraceGen::add(cl->getVersionRef()->getId(),"Disp=%lld",globalClock);
#endif
taskHandler->restart(cl->getVersionRef());
nRestartDisp.inc();
cl->invalidate();
return;
}
if (cl->isRestarted() || !cl->hasState()) {
// Note: It is possible to send (cl->isSafe() && !cl->isDirty()), but then
// the locality is much worse.
cl->invalidate();
return;
}
#ifndef TS_VICTIM_DISPLACE_CLEAN
if (!cl->isDirty()) {
I(cl->isSafe());
cl->invalidate();
return;
}
#endif
PAddr paddr = cl->getPAddr();
I(!isCombining(paddr));
#ifdef TS_VICTIM_DISPLACE_CLEAN
writeMemory(paddr);
#else
if (cl->isDirty())
writeMemory(paddr);
#endif
cl->invalidate();
I(cl->isInvalid());
return;
}
int main(int argc, char** argv)
{
if(argc < 3)
usage();
long rsaptr = getRSAPointer(argv[1]);
long hostptr = getHostPointer(argv[1]);
printf("%lo %lo", rsaptr, hostptr);
int childpid = fork();
if(childpid == -1)
fatal("Unable to fork.");
if(childpid == 0)
{
printf("I'm the child");
//chdir(TIBIA_ENV);
execl(TIBIA_PATH, (const char*) NULL, (char*) NULL);
exit(0);
}
sleep(2);
pid_t pid = findPid("Tibia");
//write RSA key
char data[310] = "";
strcpy(data, RSA_KEY);
writeMemory(pid, rsaptr, data, RSALEN);
//DEBUG
readMemory(pid, rsaptr, data, RSALEN);
printf("rsa: %s\n", data);
//DEBUG
//read pointer to Hostname struct
unsigned char ptrdata[4] = "";
readMemory(pid, hostptr, ptrdata, 4);
//read offset+4 on Hostname struct
readMemory(pid, chartohex(ptrdata)+4, ptrdata, 4);
char loc[26] = "";
strcpy(loc,argv[2]);
int len = 26;
writeMemory(pid, chartohex(ptrdata), loc, len);
readMemory(pid,chartohex(ptrdata), data, 30);
printf("IP changed to: %s\n", data);
return 1;
}
void LMVCache::combineInit(CacheLine *cl)
{
I(cl);
I(cl->isSafe());
#ifndef TS_VICTIM_DISPLACE_CLEAN
I(cl->isDirty());
#endif
PAddr paddr = cl->getPAddr();
wrLVIDEnergy->inc();
combWriteEnergy->inc();
I(!isCombining(paddr));
if (cl->isLeastSpecLine()) {
#ifndef TS_VICTIM_DISPLACE_CLEAN
I(cl->isDirty());
#endif
writeMemory(paddr);
combineHalfMiss.inc();
cl->invalidate();
return;
}
combineInit(paddr, cl->getVersionDuplicate(), cl);
I(cl->isInvalid());
}
int BeeServer::main(const std::vector<std::string>& args)
{
if (_serverState == SERVER_IDLE)
{
//create shared memory if start with non params
readMemory();
_serverFlag = true;
setServerState(SERVER_RUNNING);
writeMemory(_serverState);
ServerArgv* exRun = new ServerArgv(*this);
_exThread.start(*exRun);
//BeeTask* pTask = new BeeTask();
//string rule = Application::instance().config().getString("rule");
//pTask->setRule(rule);
//TaskManager tm;
//tm.start(pTask);
task();
waitForTerminationRequest();
//tm.cancelAll();
//tm.joinAll();
}
return Application::EXIT_OK;
}
void Recompiler::stwx(Instruction code)
{
llvm::Value* addr;
llvm::Value* rs = getGPR(code.rs);
addr = builder.CreateAdd(getGPR(code.ra), getGPR(code.rb));
writeMemory(addr, rs);
}
///////////////////////////////////////////////////////////////////////////////
//////////////////////////////////STA opcodes//////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
void opcode0x85(uint8_t* data)
{
printf("%s%s%s", opcodeEncStart, opcode0x85Encountered, opcodeEncEnd);
printf("OP_PARSE: Operand is 0x%02X\n", data[1]);
writeMemory(data[1], accu); // Load the value at memory address [OPERAND] into accumulator
pcnt += 2;
return;
}
void Recompiler::stfdx(Instruction code)
{
llvm::Value* addr;
llvm::Value* frs = getFPR(code.frs);
addr = builder.CreateAdd(getGPR(code.ra), getGPR(code.rb));
frs = builder.CreateBitCast(frs, builder.getInt64Ty());
writeMemory(addr, frs);
}
void opcode0x91(uint8_t* data)
{
printf("%s%s%s", opcodeEncStart, opcode0x91Encountered, opcodeEncEnd);
printf("OP_PARSE: Operand is 0x%02X\n", data[1]);
writeMemory((data[1]) + yreg, accu);
pcnt += 2;
return;
}
void opcode0x99(uint8_t* data)
{
printf("%s%s%s", opcodeEncStart, opcode0x99Encountered, opcodeEncEnd);
uint16_t memoryAddress = (data[1] << 8) | data[2];
printf("OP_PARSE: Operand is 0x%04X\n", memoryAddress);
writeMemory(memoryAddress + yreg, accu);
pcnt += 3;
return;
}
void Recompiler::stwu(Instruction code)
{
llvm::Value* addr = builder.getInt64(code.ds << 2);
llvm::Value* rs = getGPR(code.rs);
addr = builder.CreateAdd(addr, getGPR(code.ra));
writeMemory(addr, rs);
setGPR(code.ra, addr);
}
ErrorCode ProcessBase::writeMemoryBuffer(Address const &address,
std::string const &buffer,
size_t *nwritten) {
if (_pid == kAnyProcessId)
return kErrorProcessNotFound;
else if (!address.valid())
return kErrorInvalidArgument;
return writeMemory(address, &buffer[0], buffer.length(), nwritten);
}
void ResetCommArea( void )
{
if( CommonAddr.segment != 0 ) { /* reset common variables */
Comm.pop_no = 0;
Comm.push_no = 0;
CommonAddr.offset += 9;
writeMemory( &CommonAddr, 4, (char *)&Comm.pop_no );
CommonAddr.offset -= 9;
}
}
void BeeServer::stop(const std::string& name, const std::string& value)
{
readMemory();
if (_serverState != SERVER_RUNNING)
{
std::cout<<"System is not in running!"<<std::endl;
}
setServerState(SERVER_FINISHED);
writeMemory(_serverState);
}
void Recompiler::stw(Instruction code)
{
llvm::Value* addr = builder.getInt64(code.d);
llvm::Value* rs = getGPR(code.rs);
if (code.ra) {
addr = builder.CreateAdd(addr, getGPR(code.ra));
}
writeMemory(addr, rs);
}
void Recompiler::stfd(Instruction code)
{
llvm::Value* addr = builder.getInt64(code.d);
llvm::Value* frs = getFPR(code.frs);
if (code.ra) {
addr = builder.CreateAdd(addr, getGPR(code.ra));
}
frs = builder.CreateBitCast(frs, builder.getInt64Ty());
writeMemory(addr, frs);
}
void Recompiler::stfsux(Instruction code)
{
llvm::Value* addr;
llvm::Value* frs = getFPR(code.frs);
addr = builder.CreateAdd(getGPR(code.ra), getGPR(code.rb));
frs = builder.CreateFPTrunc(frs, builder.getFloatTy());
frs = builder.CreateBitCast(frs, builder.getInt32Ty());
writeMemory(addr, frs);
setGPR(code.ra, addr);
}
int MemoryMap::processWriteCommand(MEMMAP_Message& msg)
{
int counter;
unsigned char address;
unsigned char value;
for(counter=0;counter<msg.Field.Length;counter++){
address = msg.Field.Address + counter;
value = msg.Field.data[counter];
writeMemory(address,value);
}
return true;
}
void LMVCache::combineInit(const VMemPushLineReq *vreq)
{
I(vreq);
I(vreq->getVersionRef()->isSafe());
PAddr paddr = vreq->getPAddr();
I(!isCombining(paddr));
combWriteEnergy->inc();
if (vreq->getStateRef()->isLeastSpecLine()) {
// write to a non-version cache
combineHit.inc();
#ifdef TS_VICTIM_DISPLACE_CLEAN
writeMemory(paddr);
#else
if (vreq->getStateRef()->isDirty())
writeMemory(paddr);
#endif
return;
}
combineInit(paddr, vreq->getVersionDuplicate(), vreq->getStateRef());
}
int runFrom(int PC, int A, int CC, int HX) {
int SP=readSP();
if (verbose>2)
flsprintf(stdout,"Execute code PC=%04X A=%02X CC=%02X H:X=%04X SP=%04X\n",PC,A,CC,HX,SP);
image[ SP + 1 ] = HX >> 8;
image[ SP + 2 ] = CC;
image[ SP + 3 ] = A;
image[ SP + 4 ] = HX & 0xFF;
image[ SP + 5 ] = PC >> 8;
image[ SP + 6 ] = PC & 0xFF;
writeMemory(SP + 1 , 6 , 0);
sendByte(0x28); // Monitor mode RUN command
//struct timespec tspec;
//tspec.tv_sec=0;
//tspec.tv_nsec=5000000; /* wait at least 1 ms (datasheet specifies 11 bit times) */
//nanosleep(&tspec,0);
return SP;
}
void opcode0x16(uint8_t* data)
{
uint8_t memoryValue=0;
printf("%s%s%s", opcodeEncStart, opcode0x16Encountered, opcodeEncEnd);
printf("OP_PARSE: Operand is 0x%02X\n", data[1]);
memoryValue = readMemory(data[1] + xreg);
// Set the carry flag if bit 7 (8) is set
auxSetCarryFlag(memoryValue);
memoryValue = memoryValue << 1;
// Set the negative flag if bit 7 (8) is set
auxSetNegativeFlag(memoryValue);
writeMemory((data[1] + xreg), memoryValue);
pcnt += 2;
return;
}
Error rntFlyAsm(unsigned int address, char *cmd)
{
MemCell memcell,
value;
Error rval;
char buff[111];
rval = parseAsmInstr(cmd, &memcell);
if(rval != ERR_None)
{
consoleOut("Error parsing asm instruction\n");
return rval;
}
rval = writeMemory(address, memcell);
if(rval != ERR_None)
{
consoleOut("Error writing to memory\n");
return rval;
}
else
{
ProcInfo info;
if(memoryChanged(&address, &value) != ERR_InvalidState)
{
sprintf(buff, " [Memory] %010u:\t%d (%s)\n", address, value.getal, cmd);
consoleOut(buff);
}
// Next instruction could have changed
info = getStatus();
if(info.progCounter == address)
{
rntDisplayStatus();
}
}
return ERR_None;
}
void opcode0x0E(uint8_t* data)
{
uint8_t memoryValue=0;
printf("%s%s%s", opcodeEncStart, opcode0x0EEncountered, opcodeEncEnd);
uint16_t memoryAddress = (data[1] << 8) | data[2];
printf("OP_PARSE: Operand is 0x%04X\n", memoryAddress);
memoryValue = readMemory(memoryAddress);
// Set the carry flag if bit 7 (8) is set
auxSetCarryFlag(memoryValue);
memoryValue = memoryValue << 1;
// Set the negative flag if bit 7 (8) is set
auxSetNegativeFlag(memoryValue);
writeMemory(memoryAddress, memoryValue);
pcnt += 3;
return;
}
void OdyPatch::writePatch(unsigned char patchNum)
{
unsigned int startAddr = (unsigned int)PATCH_SIZE * patchNum;
unsigned int addr = 0;
unsigned char i;
unsigned char data[PATCH_SIZE];
for(i=0;i<10;++i)
{
data[addr] = funcValue_c_[i];
addr++;
}
for(i=0;i<6;++i)
{
data[addr] = ctrlValue_[i];
addr++;
}
for(i=0;i<2;++i) //no need to read/write last 3 func opts
{
data[addr] = optionValue_c_[i];
addr++;
}
writeMemory((const void*)data, (void*)startAddr, sizeof(data));
}
void connectTarget() {
int j;
if (connected)
return;
flsprintf(stdout, "Security code: ");
for (j = 0; j<8; ++j) {
sendByte(scode[j]);
flsprintf(stdout, ".");
}
flsprintf(stdout, " ");
flushBreak();
readMemory(RAM, 1 , 0);
connected=1;
if ((image[ RAM ] & 0x40) == 0)
flsprintf(stdout,"failed\n");
else
flsprintf(stdout,"passed\n");
// in case FLBPR is RAM based we clear it first by just writing it
image[FLBPR]=0xFF;
writeMemory(FLBPR,1,0);
}
int main(int argc, char *argv[]) {
// A201860038A00798E903A818A9028501A60165008501860088D0F5
// const char program[] = { 0xC8, 0x20, 0x00, 0x00 };
// const char program[] = { 0xA2, 0x01, 0x86, 0x00, 0x38, 0xA0, 0x07, 0x98, 0xE9, 0x03, 0xA8, 0x18, 0xA9, 0x02, 0x85, 0x01, 0xA6, 0x01, 0x65, 0x00, 0x85, 0x01, 0x86, 0x00, 0x88, 0xD0, 0xF5 };
if(argc != 2) {
printf("Usage: %s program \n", argv[0]);
return -1;
}
char *program;
int program_length = readFileBytes(argv[1], &program);
printf("Program (%i bytes): \n", program_length);
int i;
for(i = 0; i < program_length; i++) {
printf("%i:%02X ", i, (unsigned char)program[i]);
}
printf("\n");
CPU cpu;
initializeCPU(&cpu);
cpu.pc = 0x4000;
writeMemory(&cpu, program, cpu.pc, program_length);
// cpu.pc += 559; // 700 // 799
// cpu.pc += 799; // test 06
// cpu.pc += 1192; // test 09
// char *buf = malloc(sizeof(char) * 2);
// buf[0] = 0xC0;
// buf[1] = 0x01;
// writeMemory(&cpu, buf, 0x0105, 2);
// cpu.ps = 0x1;
// cpu.a = 0x7;
// cpu.x = 0x2;
// cpu.y = 0x3;
// char *buf2 = malloc(sizeof(char) * 2);
// buf2[0] = 0x08;
// buf2[1] = 0xEE;
// writeMemory(&cpu, buf2, 0x0105, 2);
// printf("cpu->ps: %i\n", cpu.ps);
// printf("cpu->sp: %i\n", cpu.sp);
char str[1];
// int i;
for(;;) {
printf("cpu->pc: %i\n", cpu.pc);
// scanf("%s", str);
step(&cpu);
printMemory(&cpu);
printf("\n\n\n");
printf("cpu->sp: %x\n", cpu.sp);
printf("cpu->a: %x\n", cpu.a);
printf("cpu->x: %x\n", cpu.x);
printf("cpu->y: %x\n", cpu.y);
printf("cpu->ps: %x\n\n", cpu.ps);
if(cpu.pc == 17825) {
break;
}
}
printMemory(&cpu);
printf("### results:\n");
printf("cpu->sp: %x\n", cpu.sp);
printf("cpu->a: %x\n", cpu.a);
printf("cpu->x: %x\n", cpu.x);
printf("cpu->y: %x\n", cpu.y);
printf("cpu->ps: %x\n", cpu.ps);
printf("cpu->cycles: %i\n", cpu.cycles);
// printf("%s\n", );
// printbitssimple(cpu.ps);
printf("MEMORY 9: %x\n", *cpu.memory[0x80]);
printf("MEMORY final: %x\n", *cpu.memory[0x0210]);
freeCPU(&cpu);
return 0;
}
void executeVm(Cpu_t *cpu)
{
uint16_t tmp;
uint16_t mode;
uint16_t instr,k;
//SYSTEMOUTHEX("\npc:",cpu->Pc);
tmp=readMemory(cpu,IMM);
//SYSTEMOUTHEX(" instr code:",tmp);
//showCpu(cpu);
//SYSTEMOUTHEX("pc:",cpu->Pc);
mode=tmp&03000;
instr=tmp&0777;
switch(instr)
{
// ALU instructions
// two word instructions
// instruction with addressing mode, operand
//#define NOP2 00000 // A->A nop with 2 instructions
case NOP2:{
DISASM("NOP2");
INCPC(cpu);
}break;
//#define MINUS 00006 // A-M-1 -> A
case MINUS:{
DISASM("MINUS");
INCPC(cpu);
tmp=readMemory(cpu,mode);
cpu->A-=tmp;
cpu->A--;
if(cpu->flags&(1<<AF_FLAG))cpu->A++;
if(cpu->A>0777)cpu->flags|=(1<<AF_FLAG);
else cpu->flags&=~(1<<AF_FLAG);
cpu->A&=0777;
}break;
//#define PLUS 00011 // A+M -> A
case PLUS:{
DISASM("PLUS");
INCPC(cpu);
//SYSTEMOUTHEX("@:",cpu->Pc);
tmp=readMemory(cpu,mode);
//SYSTEMOUTHEX("plus:",tmp);
cpu->A+=tmp;
if(cpu->flags&(1<<AF_FLAG))cpu->A++;
if(cpu->A>0777)cpu->flags|=(1<<AF_FLAG);
else cpu->flags&=~(1<<AF_FLAG);
cpu->A&=0777;
}break;
//#define DOUBLE 00014 // A*2 -> A, operand not used
case DOUBLE:{
DISASM("DOUBLE");
INCPC(cpu);
tmp=readMemory(cpu,mode);
cpu->A=2*tmp;
//if(cpu->flags&(1<<AF_FLAG))cpu->A++;
if(cpu->A>0777)cpu->flags|=(1<<AF_FLAG);
else cpu->flags&=~(1<<AF_FLAG);
cpu->A&=0777;
}break;
//#define DEC 00017 // A-1 -> A, operand not used
case DEC:{
DISASM("DEC");
INCPC(cpu);
//tmp=readMemory(cpu,mode);
cpu->A--;
//if(cpu->flags&(1<<AF_FLAG))cpu->A++;
//if(cpu->A>0777)cpu->flags|=(1<<AF_FLAG);
//else cpu->flags&=~(1<<AF_FLAG);
cpu->A&=0777;
}break;
//#define INV 00020 // NOT A -> A, operand not used
case INV:{
DISASM("INV");
INCPC(cpu);
cpu->A=~cpu->A;
cpu->A&=0777;
}break;
//#define NOR 00021 // A NOR M -> A
case NOR:{
DISASM("NOR");
INCPC(cpu);
tmp=readMemory(cpu,mode);
cpu->A=~(cpu->A|tmp);
cpu->A&=0777;
}break;
//#define ZERO 00023 // 0 -> A -> A
case ZERO:{
DISASM("ZERO");
INCPC(cpu);
cpu->A=0;
}break;
//#define NAND 00024 // A NAND M -> A
case NAND:{
DISASM("NAND");
INCPC(cpu);
tmp=readMemory(cpu,mode);
cpu->A=~(cpu->A&tmp);
cpu->A&=0777;
}break;
//#define INVM 00025 // NOT M -> A
case INVM:{
DISASM("INVM");
INCPC(cpu);
tmp=readMemory(cpu,mode);
cpu->A=~tmp;
cpu->A&=0777;
}break;
//#define EXOR 00026 // A EXOR M -> A
case EXOR:{
DISASM("EXOR");
INCPC(cpu);
tmp=readMemory(cpu,mode);
cpu->A=(cpu->A^tmp);
cpu->A&=0777;
}break;
//#define EXNOR 00031 // A EXNOR M -> A
case EXNOR:{
DISASM("EXNOR");
INCPC(cpu);
tmp=readMemory(cpu,mode);
cpu->A=~(cpu->A^tmp);
cpu->A&=0777;
}break;
//#define AND 00033 // A and M -> A
case AND:{
DISASM("AND");
INCPC(cpu);
tmp=readMemory(cpu,mode);
cpu->A=(cpu->A&tmp);
cpu->A&=0777;
}break;
//#define ONES 00034 // 0777->A set all ones
case ONES:{
DISASM("ZERO");
INCPC(cpu);
cpu->A=0777;
}break;
//#define OR 00036 // A or M -> A
case OR:{
DISASM("OR");
INCPC(cpu);
tmp=readMemory(cpu,mode);
cpu->A=(cpu->A|tmp);
cpu->A&=0777;
}break;
//******************************************************
// stack instructions
//******************************************************
//#define PLPC 00600 // pull PC ( return )
case PLPC:{
DISASM("PLPC (return)");
cpu->Pc=pop(cpu)-1;
}break;
//#define PLP 00601 // pull P
case PLP:{
DISASM("PLP ( display )");
cpu->display=pop(cpu)-1;
}break;
//#define PLIO 00602 // pull I/O
case PLIO:{
DISASM("PLIO (outport)");
cpu->outport=pop(cpu)-1;
}break;
//#define PLA 00603 // pull A
case PLA:{
DISASM("PLA");
cpu->A=pop(cpu)-1;
}break;
//#define PHPC 00604 // push PC
case PHPC:{
DISASM("PHPC");
push(cpu,cpu->Pc); // warning: check if original T3 pushes next address
}break;
//#define PHP 00614 // push P
case PHP:{
DISASM("PHP (keys)");
push(cpu,cpu->keys);
}break;
//#define PHIO 00624 // push I/O
case PHIO:{
DISASM("PHIO (outport)");
push(cpu,cpu->outport);
}break;
//#define PHA 00634 // push A
case PHA:{
DISASM("PHA");
push(cpu,cpu->A);
}break;
//******************************************************
// register memory transfer instructions
//******************************************************
//#define STPC 00100 // PC -> M
case STPC:{
DISASM("STPC");
INCPC(cpu);
writeMemory(cpu,mode,cpu->Pc);
}break;
//#define STP 00110 // P -> M
case STP:{
DISASM("STP");
INCPC(cpu);
writeMemory(cpu,mode,cpu->keys);
}break;
//#define STIO 00120 // I/O -> M
case STIO:{
DISASM("STIO");
INCPC(cpu);
writeMemory(cpu,mode,cpu->inport);
}break;
//#define STA 00130 // A -> M
case STA:{
DISASM("STA");
INCPC(cpu);
writeMemory(cpu,mode,cpu->A);
}break;
//#define LDPC 00104 // M -> PC
case LDPC:{
DISASM("LDA");
INCPC(cpu);
cpu->A=readMemory(cpu,mode);
}break;
//#define LDP 00105 // M -> P
case LDP:{
DISASM("LDP");
INCPC(cpu);
cpu->display=readMemory(cpu,mode);
}break;
//#define LDIO 00106 // M -> I/O
case LDIO:{
DISASM("LDP");
INCPC(cpu);
cpu->outport=readMemory(cpu,mode);
}break;
//#define LDA 00107 // M -> A
case LDA:{
DISASM("LDA");
INCPC(cpu);
cpu->A=readMemory(cpu,mode);
}break;
// compare instructions
//******************************************************
// compare instruction
//******************************************************
//#define CMP 00200 // A-M -> FLG
case CMP:{
DISASM("CMP");
INCPC(cpu);
tmp=readMemory(cpu,mode);
cpu->flags&=~((1<<EQ_FLAG)|(1<<GT_FLAG)|(1<<SM_FLAG)|(1<<MSB_FLAG));
//#define EQ_FLAG 0 // A = OPR
if(tmp==cpu->A)cpu->flags|=(1<<EQ_FLAG);
//printf("a:%x dest:%x\n",cpu->A,tmp);
//#define GT_FLAG 1 // A > OPR
if(tmp>cpu->A)cpu->flags|=(1<<GT_FLAG);
//#define SM_FLAG 2 // A < OPR
if(tmp<cpu->A)cpu->flags|=(1<<SM_FLAG);
//#define ALU_FLAG 3 //
//#define MSB_FLAG 4 // MSB of A
if(cpu->A&0400)cpu->flags|=(1<<MSB_FLAG);
}break;
//******************************************************
// machine control instructions
//******************************************************
//#define RST 00400 // 0001->PC
case RST:{
DISASM("RST");
cpu->Pc=1;
}break;
//#define STOP 00401 // stop
case STOP:{
DISASM("STOP");
cpu->Pc--;
}break;
//#define RSD 00402 // reset display
case RSD:{
DISASM("RSD");
cpu->display=0;
}break;
//#define SHIB 00403 // select high bank
case SHIB:{
DISASM("select high bank");
cpu->bank=1;
}break;
//#define SLOB 00404 // select low bank
case SLOB:{
DISASM("select low bank");
cpu->bank=0;
}break;
//#define RSSP 00405 // 0->SP, reset stack pointer
case RSSP:{
DISASM("RSSP");
cpu->Sp=0;
}break;
//#define RSA 00406 // 0->ACCU, reset accumulator
case RSA:{
DISASM("RSA");
cpu->A=0;
}break;
//#define STB 00407 // strobe ?
case STB:{
DISASM("strobe?");
}break;
//SAF 00410 // set accu flag ( AF_FLAG )
case SAF:{
DISASM("SAF");
cpu->flags|=(1<<AF_FLAG);
}break;
//#define CAF 00411 // clear accu flag ( AF_FLAG )
case CAF:{
DISASM("CAF");
cpu->flags&=~(1<<AF_FLAG);
}break;
//#define SSF 00412 // set shift flag ( SF_FLAG )
case SSF:{
DISASM("SSF");
cpu->flags|=(1<<SF_FLAG);
}break;
//#define CSF 00413 // clear shift flag ( SF_FLAG )
case CSF:{
DISASM("CSF");
cpu->flags&=~(1<<SF_FLAG);
}break;
//#define NOP1 00414 // one word nop
case NOP1:{
DISASM("NOP1");
}break;
//******************************************************
// register register transfer instructions
//******************************************************
//#define TPCP 00501 // PC -> P // PC -> display
case TPCP:{
DISASM("TPCP");
cpu->display=cpu->Pc;
}break;
//#define TPCIO 00502 // PC -> IO ( outport )
case TPCIO:{
DISASM("TPCIO");
cpu->outport=cpu->Pc;
}break;
//#define TPCA 00503 // PC -> A
case TPCA:{
DISASM("TPCA");
cpu->A=cpu->Pc;
}break;
//#define TPPC 00510 // (keys) P -> PC
case TPPC:{
DISASM("TPPC (keys)");
cpu->Pc=cpu->keys;
}break;
//#define TPP 00511 // P -> P read keyboard, write display
case TPP:{
DISASM("TPP (keys->display)");
cpu->display=cpu->keys;
}break;
//#define TPIO 00512 // P -> IO
case TPIO:{
DISASM("TPIO (keys->outport)");
cpu->outport=cpu->keys;
}break;
//#define TPA 00513 // P -> A // keys -> A
case TPA:{
DISASM("TPIO (keys->outport)");
cpu->A=cpu->keys;
}break;
//#define TIOPC 00520 // IO->PC
case TIOPC:{
DISASM("TIOPC (inport->pc)");
cpu->Pc=cpu->inport;
}break;
//#define TIOP 00521 // IO->P
case TIOP:{
DISASM("TIOP (inport->display)");
cpu->display=cpu->inport;
}break;
//#define TIOA 00523 // IO->A
case TIOA:{
DISASM("TIOA");
cpu->A=cpu->inport;
}break;
//#define TAPC 00530 // A->PC ( variable jump )
case TAPC:{
DISASM("TAPC (jmp(A))");
cpu->Pc=cpu->A;
}break;
//#define TAP 00531 // A->P store A in display
case TAP:{
DISASM("TAP");
cpu->display=cpu->A;
}break;
//#define TAIO 00532 // A->IO store A in outport
case TAIO:{
DISASM("TAIO");
cpu->outport=cpu->A;
}break;
//******************************************************
// masked functions
//******************************************************
default:{
tmp=instr&JMPMASK;
uint8_t flags;
flags=instr&FLAGMASK;
//ERROR("instr", tmp);
SYSTEMOUTHEX("flag selector",flags);
SYSTEMOUTHEX(" cpu.flags",cpu->flags);
SYSTEMOUTCR;
switch(tmp)
{
//******************************************************
// program flow instructions
//******************************************************
case JMPS:{
DISASM("JMPS");
INCPC(cpu);
if(cpu->flags&(1<<flags))
{
DISASM("jump");
cpu->Pc=readMemory(cpu,mode)-1;
}
}break;
case JMPR:{
DISASM("JMPR");
INCPC(cpu);
if(!(cpu->flags&(1<<flags)))
{
DISASM("jump");
cpu->Pc=readMemory(cpu,mode)-1;
}
}break;
case GSBS:{
DISASM("GSBS");
INCPC(cpu);
if(cpu->flags&(1<<flags))
{
DISASM(" (call)");
push(cpu,cpu->Pc+1);
cpu->Pc=readMemory(cpu,mode)-1;
}
}break;
case GSBR:{
DISASM("GSBR");
INCPC(cpu);
if(!(cpu->flags&(1<<flags)))
{
DISASM(" (call)");
push(cpu,cpu->Pc+1);
cpu->Pc=readMemory(cpu,mode)-1;
//dumpMem1(cpu);
}
}break;
default:
{
//******************************************************
// shift instructions
//******************************************************
tmp=instr&SHIFTMASK;
uint8_t shift=instr&07;
switch(tmp)
{
//#define ROL 00700 // rotate left n bits
case ROL:{
tmp=cpu->A;
tmp=tmp<<shift;
tmp|=cpu->A>>(13-shift);
if(tmp&010000)cpu->flags|=(1<<SF_FLAG);
else cpu->flags&=~(1<<SF_FLAG);
cpu->A=tmp&0777;
}break;
//#define ROR 00710 // rotate right n bits
case ROR:{
tmp=cpu->A;
tmp=tmp>>shift;
tmp|=cpu->A<<(13-shift);
if(tmp&010000)cpu->flags|=(1<<SF_FLAG);
else cpu->flags&=~(1<<SF_FLAG);
cpu->A=tmp&0777;
}break;
//#define SFL 00720 // shift left n bits
case SFL:{
tmp=cpu->A;
tmp=tmp<<shift;
cpu->A=tmp&0777;
if(tmp&010000)cpu->flags|=(1<<SF_FLAG);
else cpu->flags&=~(1<<SF_FLAG);
}break;
//#define SFR 00730 // shift right n bits
case SFR:{
tmp=cpu->A;
tmp=tmp>>shift;
cpu->A=tmp&0777;
if((cpu->A)>>(shift-1)&1)cpu->flags|=(1<<SF_FLAG);
else cpu->flags&=~(1<<SF_FLAG);
}break;
default:
{
ERROR("error: unknown instruction",instr);
simulatorReset(cpu);
cpu->Pc--;
}break;
}
}
}
}break;
}
void mips1::behavior() {
unsigned ins_id;
cache_item_t* ins_cache;
if (has_delayed_load) {
APP_MEM->load(delayed_load_program);
ac_pc = ac_start_addr;
has_delayed_load = false;
}
for (;;) {
bhv_pc = ac_pc;
if( bhv_pc >= dec_cache_size){
cerr << "ArchC: Address out of bounds (pc=0x" << hex << bhv_pc << ")." << endl;
stop();
return;
}
else {
if( start_up ){
decode_pc = ac_pc;
ISA.syscall.set_prog_args(argc, argv);
start_up=0;
init_dec_cache();
}
else{
decode_pc = bhv_pc;
}
//!Handling System calls.
switch( decode_pc ){
#define AC_SYSC(NAME,LOCATION) \
case LOCATION: \
ISA.syscall.NAME(); \
break; \
#include <ac_syscall.def>
#undef AC_SYSC
default:
ins_cache = (DEC_CACHE+decode_pc);
if ( !ins_cache->valid ){
quant = 0;
ins_cache->instr_p = new ac_instr<mips1_parms::AC_DEC_FIELD_NUMBER>((ISA.decoder)->Decode(reinterpret_cast<unsigned char*>(buffer), quant));
ins_cache->valid = 1;
}
instr_vec = ins_cache->instr_p;
ins_id = instr_vec->get(IDENT);
if( ins_id == 0 ) {
cerr << "ArchC Error: Unidentified instruction. " << endl;
cerr << "PC = " << hex << decode_pc << dec << endl;
stop();
return;
}
ac_pc = decode_pc;
ISA.cur_instr_id = ins_id;
if (!ac_annul_sig) ISA._behavior_instruction(instr_vec->get(1));
switch (ins_id) {
case 1: // Instruction lb
if (!ac_annul_sig) ISA._behavior_mips1_Type_I(instr_vec->get(1), instr_vec->get(2), instr_vec->get(3), instr_vec->get(7));
if (!ac_annul_sig) ISA.behavior_lb(instr_vec->get(1), instr_vec->get(2), instr_vec->get(3), instr_vec->get(7));
break;
case 2: // Instruction lbu
if (!ac_annul_sig) ISA._behavior_mips1_Type_I(instr_vec->get(1), instr_vec->get(2), instr_vec->get(3), instr_vec->get(7));
if (!ac_annul_sig) ISA.behavior_lbu(instr_vec->get(1), instr_vec->get(2), instr_vec->get(3), instr_vec->get(7));
break;
case 3: // Instruction lh
if (!ac_annul_sig) ISA._behavior_mips1_Type_I(instr_vec->get(1), instr_vec->get(2), instr_vec->get(3), instr_vec->get(7));
if (!ac_annul_sig) ISA.behavior_lh(instr_vec->get(1), instr_vec->get(2), instr_vec->get(3), instr_vec->get(7));
break;
case 4: // Instruction lhu
if (!ac_annul_sig) ISA._behavior_mips1_Type_I(instr_vec->get(1), instr_vec->get(2), instr_vec->get(3), instr_vec->get(7));
if (!ac_annul_sig) ISA.behavior_lhu(instr_vec->get(1), instr_vec->get(2), instr_vec->get(3), instr_vec->get(7));
break;
case 5: // Instruction lw
if (!ac_annul_sig) ISA._behavior_mips1_Type_I(instr_vec->get(1), instr_vec->get(2), instr_vec->get(3), instr_vec->get(7));
if (!ac_annul_sig) ISA.behavior_lw(instr_vec->get(1), instr_vec->get(2), instr_vec->get(3), instr_vec->get(7));
break;
case 6: // Instruction lwl
if (!ac_annul_sig) ISA._behavior_mips1_Type_I(instr_vec->get(1), instr_vec->get(2), instr_vec->get(3), instr_vec->get(7));
if (!ac_annul_sig) ISA.behavior_lwl(instr_vec->get(1), instr_vec->get(2), instr_vec->get(3), instr_vec->get(7));
break;
case 7: // Instruction lwr
if (!ac_annul_sig) ISA._behavior_mips1_Type_I(instr_vec->get(1), instr_vec->get(2), instr_vec->get(3), instr_vec->get(7));
if (!ac_annul_sig) ISA.behavior_lwr(instr_vec->get(1), instr_vec->get(2), instr_vec->get(3), instr_vec->get(7));
break;
case 8: // Instruction sb
if (!ac_annul_sig) ISA._behavior_mips1_Type_I(instr_vec->get(1), instr_vec->get(2), instr_vec->get(3), instr_vec->get(7));
if (!ac_annul_sig) ISA.behavior_sb(instr_vec->get(1), instr_vec->get(2), instr_vec->get(3), instr_vec->get(7));
break;
case 9: // Instruction sh
if (!ac_annul_sig) ISA._behavior_mips1_Type_I(instr_vec->get(1), instr_vec->get(2), instr_vec->get(3), instr_vec->get(7));
if (!ac_annul_sig) ISA.behavior_sh(instr_vec->get(1), instr_vec->get(2), instr_vec->get(3), instr_vec->get(7));
break;
case 10: // Instruction sw
if (!ac_annul_sig) ISA._behavior_mips1_Type_I(instr_vec->get(1), instr_vec->get(2), instr_vec->get(3), instr_vec->get(7));
if (!ac_annul_sig) ISA.behavior_sw(instr_vec->get(1), instr_vec->get(2), instr_vec->get(3), instr_vec->get(7));
break;
case 11: // Instruction swl
if (!ac_annul_sig) ISA._behavior_mips1_Type_I(instr_vec->get(1), instr_vec->get(2), instr_vec->get(3), instr_vec->get(7));
if (!ac_annul_sig) ISA.behavior_swl(instr_vec->get(1), instr_vec->get(2), instr_vec->get(3), instr_vec->get(7));
break;
case 12: // Instruction swr
if (!ac_annul_sig) ISA._behavior_mips1_Type_I(instr_vec->get(1), instr_vec->get(2), instr_vec->get(3), instr_vec->get(7));
if (!ac_annul_sig) ISA.behavior_swr(instr_vec->get(1), instr_vec->get(2), instr_vec->get(3), instr_vec->get(7));
break;
case 13: // Instruction addi
if (!ac_annul_sig) ISA._behavior_mips1_Type_I(instr_vec->get(1), instr_vec->get(2), instr_vec->get(3), instr_vec->get(7));
if (!ac_annul_sig) ISA.behavior_addi(instr_vec->get(1), instr_vec->get(2), instr_vec->get(3), instr_vec->get(7));
break;
case 14: // Instruction addiu
if (!ac_annul_sig) ISA._behavior_mips1_Type_I(instr_vec->get(1), instr_vec->get(2), instr_vec->get(3), instr_vec->get(7));
if (!ac_annul_sig) ISA.behavior_addiu(instr_vec->get(1), instr_vec->get(2), instr_vec->get(3), instr_vec->get(7));
break;
case 15: // Instruction slti
if (!ac_annul_sig) ISA._behavior_mips1_Type_I(instr_vec->get(1), instr_vec->get(2), instr_vec->get(3), instr_vec->get(7));
if (!ac_annul_sig) ISA.behavior_slti(instr_vec->get(1), instr_vec->get(2), instr_vec->get(3), instr_vec->get(7));
break;
case 16: // Instruction sltiu
if (!ac_annul_sig) ISA._behavior_mips1_Type_I(instr_vec->get(1), instr_vec->get(2), instr_vec->get(3), instr_vec->get(7));
if (!ac_annul_sig) ISA.behavior_sltiu(instr_vec->get(1), instr_vec->get(2), instr_vec->get(3), instr_vec->get(7));
break;
case 17: // Instruction andi
if (!ac_annul_sig) ISA._behavior_mips1_Type_I(instr_vec->get(1), instr_vec->get(2), instr_vec->get(3), instr_vec->get(7));
if (!ac_annul_sig) ISA.behavior_andi(instr_vec->get(1), instr_vec->get(2), instr_vec->get(3), instr_vec->get(7));
break;
case 18: // Instruction ori
if (!ac_annul_sig) ISA._behavior_mips1_Type_I(instr_vec->get(1), instr_vec->get(2), instr_vec->get(3), instr_vec->get(7));
if (!ac_annul_sig) ISA.behavior_ori(instr_vec->get(1), instr_vec->get(2), instr_vec->get(3), instr_vec->get(7));
break;
case 19: // Instruction xori
if (!ac_annul_sig) ISA._behavior_mips1_Type_I(instr_vec->get(1), instr_vec->get(2), instr_vec->get(3), instr_vec->get(7));
if (!ac_annul_sig) ISA.behavior_xori(instr_vec->get(1), instr_vec->get(2), instr_vec->get(3), instr_vec->get(7));
break;
case 20: // Instruction lui
if (!ac_annul_sig) ISA._behavior_mips1_Type_I(instr_vec->get(1), instr_vec->get(2), instr_vec->get(3), instr_vec->get(7));
if (!ac_annul_sig) ISA.behavior_lui(instr_vec->get(1), instr_vec->get(2), instr_vec->get(3), instr_vec->get(7));
break;
case 21: // Instruction add
if (!ac_annul_sig) ISA._behavior_mips1_Type_R(instr_vec->get(1), instr_vec->get(2), instr_vec->get(3), instr_vec->get(4), instr_vec->get(5), instr_vec->get(6));
if (!ac_annul_sig) ISA.behavior_add(instr_vec->get(1), instr_vec->get(2), instr_vec->get(3), instr_vec->get(4), instr_vec->get(5), instr_vec->get(6));
break;
case 22: // Instruction addu
if (!ac_annul_sig) ISA._behavior_mips1_Type_R(instr_vec->get(1), instr_vec->get(2), instr_vec->get(3), instr_vec->get(4), instr_vec->get(5), instr_vec->get(6));
if (!ac_annul_sig) ISA.behavior_addu(instr_vec->get(1), instr_vec->get(2), instr_vec->get(3), instr_vec->get(4), instr_vec->get(5), instr_vec->get(6));
break;
case 23: // Instruction sub
if (!ac_annul_sig) ISA._behavior_mips1_Type_R(instr_vec->get(1), instr_vec->get(2), instr_vec->get(3), instr_vec->get(4), instr_vec->get(5), instr_vec->get(6));
if (!ac_annul_sig) ISA.behavior_sub(instr_vec->get(1), instr_vec->get(2), instr_vec->get(3), instr_vec->get(4), instr_vec->get(5), instr_vec->get(6));
break;
case 24: // Instruction subu
if (!ac_annul_sig) ISA._behavior_mips1_Type_R(instr_vec->get(1), instr_vec->get(2), instr_vec->get(3), instr_vec->get(4), instr_vec->get(5), instr_vec->get(6));
if (!ac_annul_sig) ISA.behavior_subu(instr_vec->get(1), instr_vec->get(2), instr_vec->get(3), instr_vec->get(4), instr_vec->get(5), instr_vec->get(6));
break;
case 25: // Instruction slt
if (!ac_annul_sig) ISA._behavior_mips1_Type_R(instr_vec->get(1), instr_vec->get(2), instr_vec->get(3), instr_vec->get(4), instr_vec->get(5), instr_vec->get(6));
if (!ac_annul_sig) ISA.behavior_slt(instr_vec->get(1), instr_vec->get(2), instr_vec->get(3), instr_vec->get(4), instr_vec->get(5), instr_vec->get(6));
break;
case 26: // Instruction sltu
if (!ac_annul_sig) ISA._behavior_mips1_Type_R(instr_vec->get(1), instr_vec->get(2), instr_vec->get(3), instr_vec->get(4), instr_vec->get(5), instr_vec->get(6));
if (!ac_annul_sig) ISA.behavior_sltu(instr_vec->get(1), instr_vec->get(2), instr_vec->get(3), instr_vec->get(4), instr_vec->get(5), instr_vec->get(6));
break;
case 27: // Instruction instr_and
if (!ac_annul_sig) ISA._behavior_mips1_Type_R(instr_vec->get(1), instr_vec->get(2), instr_vec->get(3), instr_vec->get(4), instr_vec->get(5), instr_vec->get(6));
if (!ac_annul_sig) ISA.behavior_instr_and(instr_vec->get(1), instr_vec->get(2), instr_vec->get(3), instr_vec->get(4), instr_vec->get(5), instr_vec->get(6));
break;
case 28: // Instruction instr_or
if (!ac_annul_sig) ISA._behavior_mips1_Type_R(instr_vec->get(1), instr_vec->get(2), instr_vec->get(3), instr_vec->get(4), instr_vec->get(5), instr_vec->get(6));
if (!ac_annul_sig) ISA.behavior_instr_or(instr_vec->get(1), instr_vec->get(2), instr_vec->get(3), instr_vec->get(4), instr_vec->get(5), instr_vec->get(6));
break;
case 29: // Instruction instr_xor
if (!ac_annul_sig) ISA._behavior_mips1_Type_R(instr_vec->get(1), instr_vec->get(2), instr_vec->get(3), instr_vec->get(4), instr_vec->get(5), instr_vec->get(6));
if (!ac_annul_sig) ISA.behavior_instr_xor(instr_vec->get(1), instr_vec->get(2), instr_vec->get(3), instr_vec->get(4), instr_vec->get(5), instr_vec->get(6));
break;
case 30: // Instruction instr_nor
if (!ac_annul_sig) ISA._behavior_mips1_Type_R(instr_vec->get(1), instr_vec->get(2), instr_vec->get(3), instr_vec->get(4), instr_vec->get(5), instr_vec->get(6));
if (!ac_annul_sig) ISA.behavior_instr_nor(instr_vec->get(1), instr_vec->get(2), instr_vec->get(3), instr_vec->get(4), instr_vec->get(5), instr_vec->get(6));
break;
case 31: // Instruction nop
if (!ac_annul_sig) ISA._behavior_mips1_Type_R(instr_vec->get(1), instr_vec->get(2), instr_vec->get(3), instr_vec->get(4), instr_vec->get(5), instr_vec->get(6));
if (!ac_annul_sig) ISA.behavior_nop(instr_vec->get(1), instr_vec->get(2), instr_vec->get(3), instr_vec->get(4), instr_vec->get(5), instr_vec->get(6));
break;
case 32: // Instruction sll
if (!ac_annul_sig) ISA._behavior_mips1_Type_R(instr_vec->get(1), instr_vec->get(2), instr_vec->get(3), instr_vec->get(4), instr_vec->get(5), instr_vec->get(6));
if (!ac_annul_sig) ISA.behavior_sll(instr_vec->get(1), instr_vec->get(2), instr_vec->get(3), instr_vec->get(4), instr_vec->get(5), instr_vec->get(6));
break;
case 33: // Instruction srl
if (!ac_annul_sig) ISA._behavior_mips1_Type_R(instr_vec->get(1), instr_vec->get(2), instr_vec->get(3), instr_vec->get(4), instr_vec->get(5), instr_vec->get(6));
if (!ac_annul_sig) ISA.behavior_srl(instr_vec->get(1), instr_vec->get(2), instr_vec->get(3), instr_vec->get(4), instr_vec->get(5), instr_vec->get(6));
break;
case 34: // Instruction sra
if (!ac_annul_sig) ISA._behavior_mips1_Type_R(instr_vec->get(1), instr_vec->get(2), instr_vec->get(3), instr_vec->get(4), instr_vec->get(5), instr_vec->get(6));
if (!ac_annul_sig) ISA.behavior_sra(instr_vec->get(1), instr_vec->get(2), instr_vec->get(3), instr_vec->get(4), instr_vec->get(5), instr_vec->get(6));
break;
case 35: // Instruction sllv
if (!ac_annul_sig) ISA._behavior_mips1_Type_R(instr_vec->get(1), instr_vec->get(2), instr_vec->get(3), instr_vec->get(4), instr_vec->get(5), instr_vec->get(6));
if (!ac_annul_sig) ISA.behavior_sllv(instr_vec->get(1), instr_vec->get(2), instr_vec->get(3), instr_vec->get(4), instr_vec->get(5), instr_vec->get(6));
break;
case 36: // Instruction srlv
if (!ac_annul_sig) ISA._behavior_mips1_Type_R(instr_vec->get(1), instr_vec->get(2), instr_vec->get(3), instr_vec->get(4), instr_vec->get(5), instr_vec->get(6));
if (!ac_annul_sig) ISA.behavior_srlv(instr_vec->get(1), instr_vec->get(2), instr_vec->get(3), instr_vec->get(4), instr_vec->get(5), instr_vec->get(6));
break;
case 37: // Instruction srav
if (!ac_annul_sig) ISA._behavior_mips1_Type_R(instr_vec->get(1), instr_vec->get(2), instr_vec->get(3), instr_vec->get(4), instr_vec->get(5), instr_vec->get(6));
if (!ac_annul_sig) ISA.behavior_srav(instr_vec->get(1), instr_vec->get(2), instr_vec->get(3), instr_vec->get(4), instr_vec->get(5), instr_vec->get(6));
break;
case 38: // Instruction mult
if (!ac_annul_sig) ISA._behavior_mips1_Type_R(instr_vec->get(1), instr_vec->get(2), instr_vec->get(3), instr_vec->get(4), instr_vec->get(5), instr_vec->get(6));
if (!ac_annul_sig) ISA.behavior_mult(instr_vec->get(1), instr_vec->get(2), instr_vec->get(3), instr_vec->get(4), instr_vec->get(5), instr_vec->get(6));
break;
case 39: // Instruction multu
if (!ac_annul_sig) ISA._behavior_mips1_Type_R(instr_vec->get(1), instr_vec->get(2), instr_vec->get(3), instr_vec->get(4), instr_vec->get(5), instr_vec->get(6));
if (!ac_annul_sig) ISA.behavior_multu(instr_vec->get(1), instr_vec->get(2), instr_vec->get(3), instr_vec->get(4), instr_vec->get(5), instr_vec->get(6));
break;
case 40: // Instruction div
if (!ac_annul_sig) ISA._behavior_mips1_Type_R(instr_vec->get(1), instr_vec->get(2), instr_vec->get(3), instr_vec->get(4), instr_vec->get(5), instr_vec->get(6));
if (!ac_annul_sig) ISA.behavior_div(instr_vec->get(1), instr_vec->get(2), instr_vec->get(3), instr_vec->get(4), instr_vec->get(5), instr_vec->get(6));
break;
case 41: // Instruction divu
if (!ac_annul_sig) ISA._behavior_mips1_Type_R(instr_vec->get(1), instr_vec->get(2), instr_vec->get(3), instr_vec->get(4), instr_vec->get(5), instr_vec->get(6));
if (!ac_annul_sig) ISA.behavior_divu(instr_vec->get(1), instr_vec->get(2), instr_vec->get(3), instr_vec->get(4), instr_vec->get(5), instr_vec->get(6));
break;
case 42: // Instruction mfhi
if (!ac_annul_sig) ISA._behavior_mips1_Type_R(instr_vec->get(1), instr_vec->get(2), instr_vec->get(3), instr_vec->get(4), instr_vec->get(5), instr_vec->get(6));
if (!ac_annul_sig) ISA.behavior_mfhi(instr_vec->get(1), instr_vec->get(2), instr_vec->get(3), instr_vec->get(4), instr_vec->get(5), instr_vec->get(6));
break;
case 43: // Instruction mthi
if (!ac_annul_sig) ISA._behavior_mips1_Type_R(instr_vec->get(1), instr_vec->get(2), instr_vec->get(3), instr_vec->get(4), instr_vec->get(5), instr_vec->get(6));
if (!ac_annul_sig) ISA.behavior_mthi(instr_vec->get(1), instr_vec->get(2), instr_vec->get(3), instr_vec->get(4), instr_vec->get(5), instr_vec->get(6));
break;
case 44: // Instruction mflo
if (!ac_annul_sig) ISA._behavior_mips1_Type_R(instr_vec->get(1), instr_vec->get(2), instr_vec->get(3), instr_vec->get(4), instr_vec->get(5), instr_vec->get(6));
if (!ac_annul_sig) ISA.behavior_mflo(instr_vec->get(1), instr_vec->get(2), instr_vec->get(3), instr_vec->get(4), instr_vec->get(5), instr_vec->get(6));
break;
case 45: // Instruction mtlo
if (!ac_annul_sig) ISA._behavior_mips1_Type_R(instr_vec->get(1), instr_vec->get(2), instr_vec->get(3), instr_vec->get(4), instr_vec->get(5), instr_vec->get(6));
if (!ac_annul_sig) ISA.behavior_mtlo(instr_vec->get(1), instr_vec->get(2), instr_vec->get(3), instr_vec->get(4), instr_vec->get(5), instr_vec->get(6));
break;
case 46: // Instruction j
if (!ac_annul_sig) ISA._behavior_mips1_Type_J(instr_vec->get(1), instr_vec->get(8));
if (!ac_annul_sig) ISA.behavior_j(instr_vec->get(1), instr_vec->get(8));
break;
case 47: // Instruction jal
if (!ac_annul_sig) ISA._behavior_mips1_Type_J(instr_vec->get(1), instr_vec->get(8));
if (!ac_annul_sig) ISA.behavior_jal(instr_vec->get(1), instr_vec->get(8));
break;
case 48: // Instruction jr
if (!ac_annul_sig) ISA._behavior_mips1_Type_R(instr_vec->get(1), instr_vec->get(2), instr_vec->get(3), instr_vec->get(4), instr_vec->get(5), instr_vec->get(6));
if (!ac_annul_sig) ISA.behavior_jr(instr_vec->get(1), instr_vec->get(2), instr_vec->get(3), instr_vec->get(4), instr_vec->get(5), instr_vec->get(6));
break;
case 49: // Instruction jalr
if (!ac_annul_sig) ISA._behavior_mips1_Type_R(instr_vec->get(1), instr_vec->get(2), instr_vec->get(3), instr_vec->get(4), instr_vec->get(5), instr_vec->get(6));
if (!ac_annul_sig) ISA.behavior_jalr(instr_vec->get(1), instr_vec->get(2), instr_vec->get(3), instr_vec->get(4), instr_vec->get(5), instr_vec->get(6));
break;
case 50: // Instruction beq
if (!ac_annul_sig) ISA._behavior_mips1_Type_I(instr_vec->get(1), instr_vec->get(2), instr_vec->get(3), instr_vec->get(7));
if (!ac_annul_sig) ISA.behavior_beq(instr_vec->get(1), instr_vec->get(2), instr_vec->get(3), instr_vec->get(7));
break;
case 51: // Instruction bne
if (!ac_annul_sig) ISA._behavior_mips1_Type_I(instr_vec->get(1), instr_vec->get(2), instr_vec->get(3), instr_vec->get(7));
if (!ac_annul_sig) ISA.behavior_bne(instr_vec->get(1), instr_vec->get(2), instr_vec->get(3), instr_vec->get(7));
break;
case 52: // Instruction blez
if (!ac_annul_sig) ISA._behavior_mips1_Type_I(instr_vec->get(1), instr_vec->get(2), instr_vec->get(3), instr_vec->get(7));
if (!ac_annul_sig) ISA.behavior_blez(instr_vec->get(1), instr_vec->get(2), instr_vec->get(3), instr_vec->get(7));
break;
case 53: // Instruction bgtz
if (!ac_annul_sig) ISA._behavior_mips1_Type_I(instr_vec->get(1), instr_vec->get(2), instr_vec->get(3), instr_vec->get(7));
if (!ac_annul_sig) ISA.behavior_bgtz(instr_vec->get(1), instr_vec->get(2), instr_vec->get(3), instr_vec->get(7));
break;
case 54: // Instruction bltz
if (!ac_annul_sig) ISA._behavior_mips1_Type_I(instr_vec->get(1), instr_vec->get(2), instr_vec->get(3), instr_vec->get(7));
if (!ac_annul_sig) ISA.behavior_bltz(instr_vec->get(1), instr_vec->get(2), instr_vec->get(3), instr_vec->get(7));
break;
case 55: // Instruction bgez
if (!ac_annul_sig) ISA._behavior_mips1_Type_I(instr_vec->get(1), instr_vec->get(2), instr_vec->get(3), instr_vec->get(7));
if (!ac_annul_sig) ISA.behavior_bgez(instr_vec->get(1), instr_vec->get(2), instr_vec->get(3), instr_vec->get(7));
break;
case 56: // Instruction bltzal
if (!ac_annul_sig) ISA._behavior_mips1_Type_I(instr_vec->get(1), instr_vec->get(2), instr_vec->get(3), instr_vec->get(7));
if (!ac_annul_sig) ISA.behavior_bltzal(instr_vec->get(1), instr_vec->get(2), instr_vec->get(3), instr_vec->get(7));
break;
case 57: // Instruction bgezal
if (!ac_annul_sig) ISA._behavior_mips1_Type_I(instr_vec->get(1), instr_vec->get(2), instr_vec->get(3), instr_vec->get(7));
if (!ac_annul_sig) ISA.behavior_bgezal(instr_vec->get(1), instr_vec->get(2), instr_vec->get(3), instr_vec->get(7));
break;
case 58: // Instruction sys_call
if (!ac_annul_sig) ISA._behavior_mips1_Type_R(instr_vec->get(1), instr_vec->get(2), instr_vec->get(3), instr_vec->get(4), instr_vec->get(5), instr_vec->get(6));
if (!ac_annul_sig) ISA.behavior_sys_call(instr_vec->get(1), instr_vec->get(2), instr_vec->get(3), instr_vec->get(4), instr_vec->get(5), instr_vec->get(6));
break;
case 59: // Instruction instr_break
if (!ac_annul_sig) ISA._behavior_mips1_Type_R(instr_vec->get(1), instr_vec->get(2), instr_vec->get(3), instr_vec->get(4), instr_vec->get(5), instr_vec->get(6));
if (!ac_annul_sig) ISA.behavior_instr_break(instr_vec->get(1), instr_vec->get(2), instr_vec->get(3), instr_vec->get(4), instr_vec->get(5), instr_vec->get(6));
break;
} // switch (ins_id)
break;
}
//hit&miss data_cache & instruction_cache
if(useMemory(ins_id) || writeMemory(ins_id)){
if(dcache_hit(DC_ADDR,writeMemory(ins_id)))
dcount_hit++;
else
dcount_miss++;
}
if(icache_hit(ac_pc.read())){
icount_hit++;
}
else{
icount_miss++;
}
//end data_cache
storeInstruction(ins_id,
instr_vec->get(2),
instr_vec->get(3),
instr_vec->get(4));
checkHazard(ac_pc.read());
if ((!ac_wait_sig) && (!ac_annul_sig)) ac_instr_counter+=1;
ac_annul_sig = 0;
}
//!Updating Regs for behavioral simulation.
if(!ac_wait_sig){
bhv_pc = ac_pc;
}
if (ac_stop_flag) {
return;
}
else {
if (instr_in_batch < instr_batch_size) {
instr_in_batch++;
}
else {
instr_in_batch = 0;
wait(1, SC_NS);
}
}
} // for (;;)
} // behavior()