/// runOnMachineFunction - This uses the printMachineInstruction()
/// method to print assembly for each instruction.
///
bool AlphaAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
this->MF = &MF;
SetupMachineFunction(MF);
O << "\n\n";
// Print out constants referenced by the function
EmitConstantPool(MF.getConstantPool());
// Print out jump tables referenced by the function
EmitJumpTableInfo(MF.getJumpTableInfo(), MF);
// Print out labels for the function.
const Function *F = MF.getFunction();
OutStreamer.SwitchSection(getObjFileLowering().SectionForGlobal(F, Mang, TM));
EmitAlignment(MF.getAlignment(), F);
switch (F->getLinkage()) {
default: llvm_unreachable("Unknown linkage type!");
case Function::InternalLinkage: // Symbols default to internal.
case Function::PrivateLinkage:
case Function::LinkerPrivateLinkage:
break;
case Function::ExternalLinkage:
O << "\t.globl " << CurrentFnName << "\n";
break;
case Function::WeakAnyLinkage:
case Function::WeakODRLinkage:
case Function::LinkOnceAnyLinkage:
case Function::LinkOnceODRLinkage:
O << TAI->getWeakRefDirective() << CurrentFnName << "\n";
break;
}
printVisibility(CurrentFnName, F->getVisibility());
O << "\t.ent " << CurrentFnName << "\n";
O << CurrentFnName << ":\n";
// Print out code for the function.
for (MachineFunction::const_iterator I = MF.begin(), E = MF.end();
I != E; ++I) {
if (I != MF.begin()) {
printBasicBlockLabel(I, true, true);
O << '\n';
}
for (MachineBasicBlock::const_iterator II = I->begin(), E = I->end();
II != E; ++II) {
// Print the assembly for the instruction.
++EmittedInsts;
printInstruction(II);
}
}
O << "\t.end " << CurrentFnName << "\n";
// We didn't modify anything.
return false;
}
void MachineVerifier::verifyLiveVariables() {
assert(LiveVars && "Don't call verifyLiveVariables without LiveVars");
for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) {
unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
LiveVariables::VarInfo &VI = LiveVars->getVarInfo(Reg);
for (MachineFunction::const_iterator MFI = MF->begin(), MFE = MF->end();
MFI != MFE; ++MFI) {
BBInfo &MInfo = MBBInfoMap[MFI];
// Our vregsRequired should be identical to LiveVariables' AliveBlocks
if (MInfo.vregsRequired.count(Reg)) {
if (!VI.AliveBlocks.test(MFI->getNumber())) {
report("LiveVariables: Block missing from AliveBlocks", MFI);
*OS << "Virtual register " << PrintReg(Reg)
<< " must be live through the block.\n";
}
} else {
if (VI.AliveBlocks.test(MFI->getNumber())) {
report("LiveVariables: Block should not be in AliveBlocks", MFI);
*OS << "Virtual register " << PrintReg(Reg)
<< " is not needed live through the block.\n";
}
}
}
}
}
/// runOnMachineFunction - This uses the printMachineInstruction()
/// method to print assembly for each instruction.
///
bool AlphaAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
SetupMachineFunction(MF);
O << "\n\n";
// Print out constants referenced by the function
EmitConstantPool(MF.getConstantPool());
// Print out jump tables referenced by the function
EmitJumpTableInfo(MF.getJumpTableInfo(), MF);
// Print out labels for the function.
const Function *F = MF.getFunction();
SwitchToSection(TAI->SectionForGlobal(F));
EmitAlignment(4, F);
switch (F->getLinkage()) {
default: assert(0 && "Unknown linkage type!");
case Function::InternalLinkage: // Symbols default to internal.
case Function::PrivateLinkage:
break;
case Function::ExternalLinkage:
O << "\t.globl " << CurrentFnName << "\n";
break;
case Function::WeakLinkage:
case Function::LinkOnceLinkage:
O << TAI->getWeakRefDirective() << CurrentFnName << "\n";
break;
}
printVisibility(CurrentFnName, F->getVisibility());
O << "\t.ent " << CurrentFnName << "\n";
O << CurrentFnName << ":\n";
// Print out code for the function.
for (MachineFunction::const_iterator I = MF.begin(), E = MF.end();
I != E; ++I) {
if (I != MF.begin()) {
printBasicBlockLabel(I, true, true);
O << '\n';
}
for (MachineBasicBlock::const_iterator II = I->begin(), E = I->end();
II != E; ++II) {
// Print the assembly for the instruction.
++EmittedInsts;
if (!printInstruction(II)) {
assert(0 && "Unhandled instruction in asm writer!");
abort();
}
}
}
O << "\t.end " << CurrentFnName << "\n";
// We didn't modify anything.
return false;
}
/// analyzePHINodes - Gather information about the PHI nodes in here. In
/// particular, we want to map the variable information of a virtual register
/// which is used in a PHI node. We map that to the BB the vreg is coming from.
///
void LiveVariables::analyzePHINodes(const MachineFunction& Fn) {
for (MachineFunction::const_iterator I = Fn.begin(), E = Fn.end();
I != E; ++I)
for (MachineBasicBlock::const_iterator BBI = I->begin(), BBE = I->end();
BBI != BBE && BBI->getOpcode() == TargetInstrInfo::PHI; ++BBI)
for (unsigned i = 1, e = BBI->getNumOperands(); i != e; i += 2)
PHIVarInfo[BBI->getOperand(i + 1).getMBB()->getNumber()]
.push_back(BBI->getOperand(i).getReg());
}
/// analyzePHINodes - Gather information about the PHI nodes in here. In
/// particular, we want to map the number of uses of a virtual register which is
/// used in a PHI node. We map that to the BB the vreg is coming from. This is
/// used later to determine when the vreg is killed in the BB.
///
void llvm::PHIElimination::analyzePHINodes(const MachineFunction& Fn) {
for (MachineFunction::const_iterator I = Fn.begin(), E = Fn.end();
I != E; ++I)
for (MachineBasicBlock::const_iterator BBI = I->begin(), BBE = I->end();
BBI != BBE && BBI->getOpcode() == TargetInstrInfo::PHI; ++BBI)
for (unsigned i = 1, e = BBI->getNumOperands(); i != e; i += 2)
++VRegPHIUseCount[BBVRegPair(BBI->getOperand(i + 1).getMBB(),
BBI->getOperand(i).getReg())];
}
/// analyzePHINodes - Gather information about the PHI nodes in here. In
/// particular, we want to map the number of uses of a virtual register which is
/// used in a PHI node. We map that to the BB the vreg is coming from. This is
/// used later to determine when the vreg is killed in the BB.
///
void PHIElimination::analyzePHINodes(const MachineFunction& MF) {
for (MachineFunction::const_iterator I = MF.begin(), E = MF.end();
I != E; ++I)
for (MachineBasicBlock::const_iterator BBI = I->begin(), BBE = I->end();
BBI != BBE && BBI->isPHI(); ++BBI)
for (unsigned i = 1, e = BBI->getNumOperands(); i != e; i += 2)
++VRegPHIUseCount[BBVRegPair(BBI->getOperand(i+1).getMBB()->getNumber(),
BBI->getOperand(i).getReg())];
}
/// extractLexicalScopes - Extract instruction ranges for each lexical scopes
/// for the given machine function.
void LexicalScopes::
extractLexicalScopes(SmallVectorImpl<InsnRange> &MIRanges,
DenseMap<const MachineInstr *, LexicalScope *> &MI2ScopeMap) {
// Scan each instruction and create scopes. First build working set of scopes.
for (MachineFunction::const_iterator I = MF->begin(), E = MF->end();
I != E; ++I) {
const MachineInstr *RangeBeginMI = NULL;
const MachineInstr *PrevMI = NULL;
DebugLoc PrevDL;
for (MachineBasicBlock::const_iterator II = I->begin(), IE = I->end();
II != IE; ++II) {
const MachineInstr *MInsn = II;
// Check if instruction has valid location information.
const DebugLoc MIDL = MInsn->getDebugLoc();
if (MIDL.isUnknown()) {
PrevMI = MInsn;
continue;
}
// If scope has not changed then skip this instruction.
if (MIDL == PrevDL) {
PrevMI = MInsn;
continue;
}
// Ignore DBG_VALUE. It does not contribute to any instruction in output.
if (MInsn->isDebugValue())
continue;
if (RangeBeginMI) {
// If we have already seen a beginning of an instruction range and
// current instruction scope does not match scope of first instruction
// in this range then create a new instruction range.
InsnRange R(RangeBeginMI, PrevMI);
MI2ScopeMap[RangeBeginMI] = getOrCreateLexicalScope(PrevDL);
MIRanges.push_back(R);
}
// This is a beginning of a new instruction range.
RangeBeginMI = MInsn;
// Reset previous markers.
PrevMI = MInsn;
PrevDL = MIDL;
}
// Create last instruction range.
if (RangeBeginMI && PrevMI && !PrevDL.isUnknown()) {
InsnRange R(RangeBeginMI, PrevMI);
MIRanges.push_back(R);
MI2ScopeMap[RangeBeginMI] = getOrCreateLexicalScope(PrevDL);
}
}
}
void WinException::computeIP2StateTable(
const MachineFunction *MF, const WinEHFuncInfo &FuncInfo,
SmallVectorImpl<std::pair<const MCExpr *, int>> &IPToStateTable) {
for (MachineFunction::const_iterator FuncletStart = MF->begin(),
FuncletEnd = MF->begin(),
End = MF->end();
FuncletStart != End; FuncletStart = FuncletEnd) {
// Find the end of the funclet
while (++FuncletEnd != End) {
if (FuncletEnd->isEHFuncletEntry()) {
break;
}
}
// Don't emit ip2state entries for cleanup funclets. Any interesting
// exceptional actions in cleanups must be handled in a separate IR
// function.
if (FuncletStart->isCleanupFuncletEntry())
continue;
MCSymbol *StartLabel;
int BaseState;
if (FuncletStart == MF->begin()) {
BaseState = NullState;
StartLabel = Asm->getFunctionBegin();
} else {
auto *FuncletPad =
cast<FuncletPadInst>(FuncletStart->getBasicBlock()->getFirstNonPHI());
assert(FuncInfo.FuncletBaseStateMap.count(FuncletPad) != 0);
BaseState = FuncInfo.FuncletBaseStateMap.find(FuncletPad)->second;
StartLabel = getMCSymbolForMBB(Asm, &*FuncletStart);
}
assert(StartLabel && "need local function start label");
IPToStateTable.push_back(
std::make_pair(create32bitRef(StartLabel), BaseState));
for (const auto &StateChange : InvokeStateChangeIterator::range(
FuncInfo, FuncletStart, FuncletEnd, BaseState)) {
// Compute the label to report as the start of this entry; use the EH
// start label for the invoke if we have one, otherwise (this is a call
// which may unwind to our caller and does not have an EH start label, so)
// use the previous end label.
const MCSymbol *ChangeLabel = StateChange.NewStartLabel;
if (!ChangeLabel)
ChangeLabel = StateChange.PreviousEndLabel;
// Emit an entry indicating that PCs after 'Label' have this EH state.
IPToStateTable.push_back(
std::make_pair(getLabelPlusOne(ChangeLabel), StateChange.NewState));
// FIXME: assert that NewState is between CatchLow and CatchHigh.
}
}
}
/// runOnMachineFunction - This uses the printMachineInstruction()
/// method to print assembly for each instruction.
///
bool SparcAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
SetupMachineFunction(MF);
// Print out constants referenced by the function
EmitConstantPool(MF.getConstantPool());
// BBNumber is used here so that a given Printer will never give two
// BBs the same name. (If you have a better way, please let me know!)
static unsigned BBNumber = 0;
O << "\n\n";
// What's my mangled name?
CurrentFnName = Mang->getValueName(MF.getFunction());
// Print out the label for the function.
const Function *F = MF.getFunction();
SwitchToTextSection(getSectionForFunction(*F).c_str(), F);
EmitAlignment(4, F);
O << "\t.globl\t" << CurrentFnName << "\n";
O << "\t.type\t" << CurrentFnName << ", #function\n";
O << CurrentFnName << ":\n";
// Number each basic block so that we can consistently refer to them
// in PC-relative references.
// FIXME: Why not use the MBB numbers?
NumberForBB.clear();
for (MachineFunction::const_iterator I = MF.begin(), E = MF.end();
I != E; ++I) {
NumberForBB[I->getBasicBlock()] = BBNumber++;
}
// Print out code for the function.
for (MachineFunction::const_iterator I = MF.begin(), E = MF.end();
I != E; ++I) {
// Print a label for the basic block.
if (I != MF.begin()) {
printBasicBlockLabel(I, true);
O << '\n';
}
for (MachineBasicBlock::const_iterator II = I->begin(), E = I->end();
II != E; ++II) {
// Print the assembly for the instruction.
O << "\t";
printInstruction(II);
++EmittedInsts;
}
}
// We didn't modify anything.
return false;
}
void BT::runEdgeQueue(BitVector &BlockScanned) {
while (!FlowQ.empty()) {
CFGEdge Edge = FlowQ.front();
FlowQ.pop();
if (EdgeExec.count(Edge))
return;
EdgeExec.insert(Edge);
ReachedBB.insert(Edge.second);
const MachineBasicBlock &B = *MF.getBlockNumbered(Edge.second);
MachineBasicBlock::const_iterator It = B.begin(), End = B.end();
// Visit PHI nodes first.
while (It != End && It->isPHI()) {
const MachineInstr &PI = *It++;
InstrExec.insert(&PI);
visitPHI(PI);
}
// If this block has already been visited through a flow graph edge,
// then the instructions have already been processed. Any updates to
// the cells would now only happen through visitUsesOf...
if (BlockScanned[Edge.second])
return;
BlockScanned[Edge.second] = true;
// Visit non-branch instructions.
while (It != End && !It->isBranch()) {
const MachineInstr &MI = *It++;
InstrExec.insert(&MI);
visitNonBranch(MI);
}
// If block end has been reached, add the fall-through edge to the queue.
if (It == End) {
MachineFunction::const_iterator BIt = B.getIterator();
MachineFunction::const_iterator Next = std::next(BIt);
if (Next != MF.end() && B.isSuccessor(&*Next)) {
int ThisN = B.getNumber();
int NextN = Next->getNumber();
FlowQ.push(CFGEdge(ThisN, NextN));
}
} else {
// Handle the remaining sequence of branches. This function will update
// the work queue.
visitBranchesFrom(*It);
}
} // while (!FlowQ->empty())
}
/// Emit the language-specific data that __C_specific_handler expects. This
/// handler lives in the x64 Microsoft C runtime and allows catching or cleaning
/// up after faults with __try, __except, and __finally. The typeinfo values
/// are not really RTTI data, but pointers to filter functions that return an
/// integer (1, 0, or -1) indicating how to handle the exception. For __finally
/// blocks and other cleanups, the landing pad label is zero, and the filter
/// function is actually a cleanup handler with the same prototype. A catch-all
/// entry is modeled with a null filter function field and a non-zero landing
/// pad label.
///
/// Possible filter function return values:
/// EXCEPTION_EXECUTE_HANDLER (1):
/// Jump to the landing pad label after cleanups.
/// EXCEPTION_CONTINUE_SEARCH (0):
/// Continue searching this table or continue unwinding.
/// EXCEPTION_CONTINUE_EXECUTION (-1):
/// Resume execution at the trapping PC.
///
/// Inferred table structure:
/// struct Table {
/// int NumEntries;
/// struct Entry {
/// imagerel32 LabelStart;
/// imagerel32 LabelEnd;
/// imagerel32 FilterOrFinally; // One means catch-all.
/// imagerel32 LabelLPad; // Zero means __finally.
/// } Entries[NumEntries];
/// };
void WinException::emitCSpecificHandlerTable(const MachineFunction *MF) {
auto &OS = *Asm->OutStreamer;
MCContext &Ctx = Asm->OutContext;
WinEHFuncInfo &FuncInfo = MMI->getWinEHFuncInfo(MF->getFunction());
// Use the assembler to compute the number of table entries through label
// difference and division.
MCSymbol *TableBegin =
Ctx.createTempSymbol("lsda_begin", /*AlwaysAddSuffix=*/true);
MCSymbol *TableEnd =
Ctx.createTempSymbol("lsda_end", /*AlwaysAddSuffix=*/true);
const MCExpr *LabelDiff = getOffset(TableEnd, TableBegin);
const MCExpr *EntrySize = MCConstantExpr::create(16, Ctx);
const MCExpr *EntryCount = MCBinaryExpr::createDiv(LabelDiff, EntrySize, Ctx);
OS.EmitValue(EntryCount, 4);
OS.EmitLabel(TableBegin);
// Iterate over all the invoke try ranges. Unlike MSVC, LLVM currently only
// models exceptions from invokes. LLVM also allows arbitrary reordering of
// the code, so our tables end up looking a bit different. Rather than
// trying to match MSVC's tables exactly, we emit a denormalized table. For
// each range of invokes in the same state, we emit table entries for all
// the actions that would be taken in that state. This means our tables are
// slightly bigger, which is OK.
const MCSymbol *LastStartLabel = nullptr;
int LastEHState = -1;
// Break out before we enter into a finally funclet.
// FIXME: We need to emit separate EH tables for cleanups.
MachineFunction::const_iterator End = MF->end();
MachineFunction::const_iterator Stop = std::next(MF->begin());
while (Stop != End && !Stop->isEHFuncletEntry())
++Stop;
for (const auto &StateChange :
InvokeStateChangeIterator::range(FuncInfo, MF->begin(), Stop)) {
// Emit all the actions for the state we just transitioned out of
// if it was not the null state
if (LastEHState != -1)
emitSEHActionsForRange(FuncInfo, LastStartLabel,
StateChange.PreviousEndLabel, LastEHState);
LastStartLabel = StateChange.NewStartLabel;
LastEHState = StateChange.NewState;
}
OS.EmitLabel(TableEnd);
}
/// runOnMachineFunction - This uses the printInstruction()
/// method to print assembly for each instruction.
///
bool PIC16AsmPrinter::runOnMachineFunction(MachineFunction &MF) {
this->MF = &MF;
// This calls the base class function required to be called at beginning
// of runOnMachineFunction.
SetupMachineFunction(MF);
// Get the mangled name.
const Function *F = MF.getFunction();
CurrentFnName = Mang->getValueName(F);
// Emit the function variables.
emitFunctionData(MF);
std::string codeSection;
codeSection = "code." + CurrentFnName + ".# " + "CODE";
const Section *fCodeSection = TAI->getNamedSection(codeSection.c_str(),
SectionFlags::Code);
O << "\n";
SwitchToSection (fCodeSection);
// Print out code for the function.
for (MachineFunction::const_iterator I = MF.begin(), E = MF.end();
I != E; ++I) {
// Print a label for the basic block.
if (I != MF.begin()) {
printBasicBlockLabel(I, true);
O << '\n';
}
else
O << CurrentFnName << ":\n";
CurBank = "";
for (MachineBasicBlock::const_iterator II = I->begin(), E = I->end();
II != E; ++II) {
// Print the assembly for the instruction.
printMachineInstruction(II);
}
}
return false; // we didn't modify anything.
}
/// runOnMachineFunction - This uses the printMachineInstruction()
/// method to print assembly for each instruction.
///
bool IA64AsmPrinter::runOnMachineFunction(MachineFunction &MF) {
this->MF = &MF;
SetupMachineFunction(MF);
O << "\n\n";
// Print out constants referenced by the function
EmitConstantPool(MF.getConstantPool());
const Function *F = MF.getFunction();
SwitchToSection(TAI->SectionForGlobal(F));
// Print out labels for the function.
EmitAlignment(5);
O << "\t.global\t" << CurrentFnName << '\n';
printVisibility(CurrentFnName, F->getVisibility());
O << "\t.type\t" << CurrentFnName << ", @function\n";
O << CurrentFnName << ":\n";
// Print out code for the function.
for (MachineFunction::const_iterator I = MF.begin(), E = MF.end();
I != E; ++I) {
// Print a label for the basic block if there are any predecessors.
if (!I->pred_empty()) {
printBasicBlockLabel(I, true, true);
O << '\n';
}
for (MachineBasicBlock::const_iterator II = I->begin(), E = I->end();
II != E; ++II) {
// Print the assembly for the instruction.
printMachineInstruction(II);
}
}
// We didn't modify anything.
return false;
}
bool VirtRegReduction::runOnMachineFunction(MachineFunction &MF)
{
bool Changed = false;
#if VRRPROF
const Function *F = MF.getFunction();
std::string FN = F->getName().str();
llog("starting vrr... %s (%d)\n", FN.c_str(), (int)time(NULL));
llog("starting immRegs finder... (%d)\n", (int)time(NULL));
#endif
std::auto_ptr<std::unordered_set<unsigned> > immRegsHolder;
std::unordered_set<unsigned> *immRegs = NULL;
// single-def regs defined by a MoveImm shouldn't coalesce as we may be
// able to fold them later
{
std::unordered_map<unsigned, const MachineInstr *> singleDef;
MachineFunction::const_iterator I = MF.begin(), E = MF.end();
// find all registers w/ a single def
for(; I != E; I++)
{
MachineBasicBlock::const_iterator BI = I->begin(), BE = I->end();
for(; BI != BE; BI++)
{
MachineInstr::const_mop_iterator II, IE;
II = BI->operands_begin();
IE = BI->operands_end();
for(; II != IE; II++)
if(II->isReg() && II->isDef())
{
unsigned R = II->getReg();
std::unordered_map<unsigned, const MachineInstr *>::iterator SI = singleDef.find(R);
if(SI == singleDef.end())
singleDef[R] = BI; // first seen! insert
else
SI->second = NULL; // second seen -- replace w/ NULL
}
}
}
std::unordered_map<unsigned, const MachineInstr *>::const_iterator SI = singleDef.begin(), SE = singleDef.end();
for(; SI != SE; SI++)
{
if(SI->second && SI->second->getDesc().isMoveImmediate()) // single def imm?
{
if(!immRegs)
immRegsHolder.reset(immRegs = new std::unordered_set<unsigned>);
immRegs->insert(SI->first); // don't coalesce
}
}
}
#if VRRPROF
llog("starting tdkRegs finder... (%d)\n", (int)time(NULL));
#endif
std::auto_ptr<std::unordered_set<unsigned> > tdkRegsHolder;
std::unordered_set<unsigned> *tdkRegs = NULL;
bool setjmpSafe = !MF.callsSetJmp() && MF.getFunction()->doesNotThrow();
{
tdkRegsHolder.reset(tdkRegs = new std::unordered_set<unsigned>);
std::unordered_map<unsigned, unsigned> trivialDefKills;
MachineFunction::const_iterator I = MF.begin(), E = MF.end();
// find all registers defed and killed in the same block w/ no intervening
// unsafe (due to setjmp) calls + side-effecty operations
for(; I != E; I++)
{
std::unordered_set<unsigned> defs;
MachineBasicBlock::const_iterator BI = I->begin(), BE = I->end();
for(; BI != BE; BI++)
{
// TODO need to add || BI->getDesc().isInlineAsm() here to help stackification?
if((!setjmpSafe && BI->getDesc().isCall()) || BI->getDesc().hasUnmodeledSideEffects()) {
// invalidate on a call instruction if setjmp present, or instr with side effects regardless
defs.clear();
}
MachineInstr::const_mop_iterator II, IE;
// uses when we're not tracking a reg it make it unsafe
II = BI->operands_begin();
IE = BI->operands_end();
for(; II != IE; II++)
if(II->isReg() && II->isUse())
{
unsigned R = II->getReg();
std::unordered_set<unsigned>::const_iterator DI = defs.find(R);
if(DI == defs.end())
trivialDefKills[R] = 100;
}
// kills of tracked defs are trivial def/kills
II = BI->operands_begin();
IE = BI->operands_end();
for(; II != IE; II++)
if(II->isReg() && II->isKill())
{
unsigned R = II->getReg();
std::unordered_set<unsigned>::const_iterator DI = defs.find(R);
if(DI != defs.end())
{
defs.erase(DI);
trivialDefKills[R]++;
}
else
trivialDefKills[R] = 100; // don't use
}
// record all defs in this instruction
II = BI->operands_begin();
IE = BI->operands_end();
for(; II != IE; II++)
if(II->isReg() && II->isDef())
defs.insert(II->getReg());
}
}
std::unordered_map<unsigned, unsigned>::const_iterator DKI = trivialDefKills.begin(),
DKE = trivialDefKills.end();
for(; DKI != DKE; DKI++)
if(DKI->second == 1)
tdkRegs->insert(DKI->first);
}
#if VRRPROF
llog("starting conflict graph construction... (%d)\n", (int)time(NULL));
#endif
std::unordered_set<unsigned>::const_iterator tdkE = tdkRegs->end();
std::unordered_set<unsigned> *okRegs = NULL;
if(!setjmpSafe)
okRegs = tdkRegs;
MachineRegisterInfo *RI = &(MF.getRegInfo());
// will eventually hold a virt register coloring for this function
ConflictGraph::Coloring coloring;
{
ConflictGraph cg;
LiveIntervals &LIS = getAnalysis<LiveIntervals>();
LiveIntervals::const_iterator I = LIS.begin(), E = LIS.end();
// check every possible LiveInterval, LiveInterval pair of the same
// register class for overlap and add overlaps to the conflict graph
// also, treat trivially def-kill-ed regs and not trivially def-kill-ed
// regs as conflicting so they end up using different VRs -- this makes
// stackification easier later in the toolchain
for(; I != E; I++)
{
unsigned R = I->first;
if(TargetRegisterInfo::isPhysicalRegister(R))
continue;
if(okRegs && okRegs->find(R) == okRegs->end())
continue;
// leave singly-defined MoveImm regs for later coalescing
if(immRegs && immRegs->find(R) != immRegs->end())
continue;
// const TargetRegisterClass *RC = RI->getRegClass(R);
const LiveInterval *LI = I->second;
if(LI->empty())
continue;
cg.addVertex(R);
bool notTDK = tdkRegs->find(R) == tdkE;
LiveIntervals::const_iterator I1 = I;
I1++;
for(; I1 != E; I1++)
{
unsigned R1 = I1->first;
if(TargetRegisterInfo::isPhysicalRegister(R1))
continue;
if(okRegs && okRegs->find(R1) == okRegs->end())
continue;
// leave singly-defined MoveImm regs for later coalescing
if(immRegs && immRegs->find(R1) != immRegs->end())
continue;
/* Don't bother checked RC -- even though it sounds like an opt, it doesn't speed us up in practice
const TargetRegisterClass *RC1 = RI->getRegClass(R1);
if(RC != RC1)
continue; // different reg class... won't conflict
*/
const LiveInterval *LI1 = I1->second;
// conflict if intervals overlap OR they're not both TDK or both NOT TDK
if(LI->overlaps(*LI1) || notTDK != (tdkRegs->find(R1) == tdkE))
cg.addEdge(R, R1);
}
}
#if VRRPROF
llog("starting coloring... (%d)\n", (int)time(NULL));
#endif
cg.color(&coloring);
#if VRRPROF
llog("starting vreg=>vreg construction... (%d)\n", (int)time(NULL));
#endif
typedef std::unordered_map<unsigned, unsigned> VRegMap;
VRegMap Regs;
// build up map of vreg=>vreg
{
std::unordered_map<const TargetRegisterClass *, std::unordered_map<unsigned, unsigned> > RCColor2VReg;
ConflictGraph::Coloring::const_iterator I = coloring.begin(), E = coloring.end();
for(; I != E; I++)
{
unsigned R = I->first;
unsigned Color = I->second;
const TargetRegisterClass *RC = RI->getRegClass(R);
std::unordered_map<unsigned, unsigned> &Color2VReg = RCColor2VReg[RC];
VRegMap::const_iterator CI = Color2VReg.find(Color);
if(CI != Color2VReg.end())
Regs[R] = CI->second; // seen this color; map it
else
Regs[R] = Color2VReg[Color] = R; // first sighting of color; bind to this reg
}
}
#if VRRPROF
llog("starting remap... (%d)\n", (int)time(NULL));
#endif
// remap regs
{
VRegMap::const_iterator I = Regs.begin(), E = Regs.end();
for(; I != E; I++)
if(I->first != I->second)
{
RI->replaceRegWith(I->first, I->second);
Changed = true;
}
}
}
#if VRRPROF
llog("done... (%d)\n", (int)time(NULL));
#endif
return Changed;
}
bool MachineVerifier::runOnMachineFunction(MachineFunction &MF) {
raw_ostream *OutFile = 0;
if (OutFileName) {
std::string ErrorInfo;
OutFile = new raw_fd_ostream(OutFileName, ErrorInfo,
raw_fd_ostream::F_Append);
if (!ErrorInfo.empty()) {
errs() << "Error opening '" << OutFileName << "': " << ErrorInfo << '\n';
exit(1);
}
OS = OutFile;
} else {
OS = &errs();
}
foundErrors = 0;
this->MF = &MF;
TM = &MF.getTarget();
TII = TM->getInstrInfo();
TRI = TM->getRegisterInfo();
MRI = &MF.getRegInfo();
LiveVars = NULL;
LiveInts = NULL;
LiveStks = NULL;
Indexes = NULL;
if (PASS) {
LiveInts = PASS->getAnalysisIfAvailable<LiveIntervals>();
// We don't want to verify LiveVariables if LiveIntervals is available.
if (!LiveInts)
LiveVars = PASS->getAnalysisIfAvailable<LiveVariables>();
LiveStks = PASS->getAnalysisIfAvailable<LiveStacks>();
Indexes = PASS->getAnalysisIfAvailable<SlotIndexes>();
}
visitMachineFunctionBefore();
for (MachineFunction::const_iterator MFI = MF.begin(), MFE = MF.end();
MFI!=MFE; ++MFI) {
visitMachineBasicBlockBefore(MFI);
for (MachineBasicBlock::const_iterator MBBI = MFI->begin(),
MBBE = MFI->end(); MBBI != MBBE; ++MBBI) {
if (MBBI->getParent() != MFI) {
report("Bad instruction parent pointer", MFI);
*OS << "Instruction: " << *MBBI;
continue;
}
visitMachineInstrBefore(MBBI);
for (unsigned I = 0, E = MBBI->getNumOperands(); I != E; ++I)
visitMachineOperand(&MBBI->getOperand(I), I);
visitMachineInstrAfter(MBBI);
}
visitMachineBasicBlockAfter(MFI);
}
visitMachineFunctionAfter();
if (OutFile)
delete OutFile;
else if (foundErrors)
report_fatal_error("Found "+Twine(foundErrors)+" machine code errors.");
// Clean up.
regsLive.clear();
regsDefined.clear();
regsDead.clear();
regsKilled.clear();
regsLiveInButUnused.clear();
MBBInfoMap.clear();
return false; // no changes
}
void MachineVerifier::verifyLiveIntervals() {
assert(LiveInts && "Don't call verifyLiveIntervals without LiveInts");
for (LiveIntervals::const_iterator LVI = LiveInts->begin(),
LVE = LiveInts->end(); LVI != LVE; ++LVI) {
const LiveInterval &LI = *LVI->second;
// Spilling and splitting may leave unused registers around. Skip them.
if (MRI->use_empty(LI.reg))
continue;
// Physical registers have much weirdness going on, mostly from coalescing.
// We should probably fix it, but for now just ignore them.
if (TargetRegisterInfo::isPhysicalRegister(LI.reg))
continue;
assert(LVI->first == LI.reg && "Invalid reg to interval mapping");
for (LiveInterval::const_vni_iterator I = LI.vni_begin(), E = LI.vni_end();
I!=E; ++I) {
VNInfo *VNI = *I;
const VNInfo *DefVNI = LI.getVNInfoAt(VNI->def);
if (!DefVNI) {
if (!VNI->isUnused()) {
report("Valno not live at def and not marked unused", MF);
*OS << "Valno #" << VNI->id << " in " << LI << '\n';
}
continue;
}
if (VNI->isUnused())
continue;
if (DefVNI != VNI) {
report("Live range at def has different valno", MF);
*OS << "Valno #" << VNI->id << " is defined at " << VNI->def
<< " where valno #" << DefVNI->id << " is live in " << LI << '\n';
continue;
}
const MachineBasicBlock *MBB = LiveInts->getMBBFromIndex(VNI->def);
if (!MBB) {
report("Invalid definition index", MF);
*OS << "Valno #" << VNI->id << " is defined at " << VNI->def
<< " in " << LI << '\n';
continue;
}
if (VNI->isPHIDef()) {
if (VNI->def != LiveInts->getMBBStartIdx(MBB)) {
report("PHIDef value is not defined at MBB start", MF);
*OS << "Valno #" << VNI->id << " is defined at " << VNI->def
<< ", not at the beginning of BB#" << MBB->getNumber()
<< " in " << LI << '\n';
}
} else {
// Non-PHI def.
const MachineInstr *MI = LiveInts->getInstructionFromIndex(VNI->def);
if (!MI) {
report("No instruction at def index", MF);
*OS << "Valno #" << VNI->id << " is defined at " << VNI->def
<< " in " << LI << '\n';
} else if (!MI->modifiesRegister(LI.reg, TRI)) {
report("Defining instruction does not modify register", MI);
*OS << "Valno #" << VNI->id << " in " << LI << '\n';
}
bool isEarlyClobber = false;
if (MI) {
for (MachineInstr::const_mop_iterator MOI = MI->operands_begin(),
MOE = MI->operands_end(); MOI != MOE; ++MOI) {
if (MOI->isReg() && MOI->getReg() == LI.reg && MOI->isDef() &&
MOI->isEarlyClobber()) {
isEarlyClobber = true;
break;
}
}
}
// Early clobber defs begin at USE slots, but other defs must begin at
// DEF slots.
if (isEarlyClobber) {
if (!VNI->def.isUse()) {
report("Early clobber def must be at a USE slot", MF);
*OS << "Valno #" << VNI->id << " is defined at " << VNI->def
<< " in " << LI << '\n';
}
} else if (!VNI->def.isDef()) {
report("Non-PHI, non-early clobber def must be at a DEF slot", MF);
*OS << "Valno #" << VNI->id << " is defined at " << VNI->def
<< " in " << LI << '\n';
}
}
}
for (LiveInterval::const_iterator I = LI.begin(), E = LI.end(); I!=E; ++I) {
const VNInfo *VNI = I->valno;
assert(VNI && "Live range has no valno");
if (VNI->id >= LI.getNumValNums() || VNI != LI.getValNumInfo(VNI->id)) {
report("Foreign valno in live range", MF);
I->print(*OS);
*OS << " has a valno not in " << LI << '\n';
}
if (VNI->isUnused()) {
report("Live range valno is marked unused", MF);
I->print(*OS);
*OS << " in " << LI << '\n';
}
const MachineBasicBlock *MBB = LiveInts->getMBBFromIndex(I->start);
if (!MBB) {
report("Bad start of live segment, no basic block", MF);
I->print(*OS);
*OS << " in " << LI << '\n';
continue;
}
SlotIndex MBBStartIdx = LiveInts->getMBBStartIdx(MBB);
if (I->start != MBBStartIdx && I->start != VNI->def) {
report("Live segment must begin at MBB entry or valno def", MBB);
I->print(*OS);
*OS << " in " << LI << '\n' << "Basic block starts at "
<< MBBStartIdx << '\n';
}
const MachineBasicBlock *EndMBB =
LiveInts->getMBBFromIndex(I->end.getPrevSlot());
if (!EndMBB) {
report("Bad end of live segment, no basic block", MF);
I->print(*OS);
*OS << " in " << LI << '\n';
continue;
}
if (I->end != LiveInts->getMBBEndIdx(EndMBB)) {
// The live segment is ending inside EndMBB
const MachineInstr *MI =
LiveInts->getInstructionFromIndex(I->end.getPrevSlot());
if (!MI) {
report("Live segment doesn't end at a valid instruction", EndMBB);
I->print(*OS);
*OS << " in " << LI << '\n' << "Basic block starts at "
<< MBBStartIdx << '\n';
} else if (TargetRegisterInfo::isVirtualRegister(LI.reg) &&
!MI->readsVirtualRegister(LI.reg)) {
// A live range can end with either a redefinition, a kill flag on a
// use, or a dead flag on a def.
// FIXME: Should we check for each of these?
bool hasDeadDef = false;
for (MachineInstr::const_mop_iterator MOI = MI->operands_begin(),
MOE = MI->operands_end(); MOI != MOE; ++MOI) {
if (MOI->isReg() && MOI->getReg() == LI.reg && MOI->isDef() && MOI->isDead()) {
hasDeadDef = true;
break;
}
}
if (!hasDeadDef) {
report("Instruction killing live segment neither defines nor reads "
"register", MI);
I->print(*OS);
*OS << " in " << LI << '\n';
}
}
}
// Now check all the basic blocks in this live segment.
MachineFunction::const_iterator MFI = MBB;
// Is this live range the beginning of a non-PHIDef VN?
if (I->start == VNI->def && !VNI->isPHIDef()) {
// Not live-in to any blocks.
if (MBB == EndMBB)
continue;
// Skip this block.
++MFI;
}
for (;;) {
assert(LiveInts->isLiveInToMBB(LI, MFI));
// We don't know how to track physregs into a landing pad.
if (TargetRegisterInfo::isPhysicalRegister(LI.reg) &&
MFI->isLandingPad()) {
if (&*MFI == EndMBB)
break;
++MFI;
continue;
}
// Check that VNI is live-out of all predecessors.
for (MachineBasicBlock::const_pred_iterator PI = MFI->pred_begin(),
PE = MFI->pred_end(); PI != PE; ++PI) {
SlotIndex PEnd = LiveInts->getMBBEndIdx(*PI).getPrevSlot();
const VNInfo *PVNI = LI.getVNInfoAt(PEnd);
if (VNI->isPHIDef() && VNI->def == LiveInts->getMBBStartIdx(MFI))
continue;
if (!PVNI) {
report("Register not marked live out of predecessor", *PI);
*OS << "Valno #" << VNI->id << " live into BB#" << MFI->getNumber()
<< '@' << LiveInts->getMBBStartIdx(MFI) << ", not live at "
<< PEnd << " in " << LI << '\n';
continue;
}
if (PVNI != VNI) {
report("Different value live out of predecessor", *PI);
*OS << "Valno #" << PVNI->id << " live out of BB#"
<< (*PI)->getNumber() << '@' << PEnd
<< "\nValno #" << VNI->id << " live into BB#" << MFI->getNumber()
<< '@' << LiveInts->getMBBStartIdx(MFI) << " in " << LI << '\n';
}
}
if (&*MFI == EndMBB)
break;
++MFI;
}
}
// Check the LI only has one connected component.
if (TargetRegisterInfo::isVirtualRegister(LI.reg)) {
ConnectedVNInfoEqClasses ConEQ(*LiveInts);
unsigned NumComp = ConEQ.Classify(&LI);
if (NumComp > 1) {
report("Multiple connected components in live interval", MF);
*OS << NumComp << " components in " << LI << '\n';
for (unsigned comp = 0; comp != NumComp; ++comp) {
*OS << comp << ": valnos";
for (LiveInterval::const_vni_iterator I = LI.vni_begin(),
E = LI.vni_end(); I!=E; ++I)
if (comp == ConEQ.getEqClass(*I))
*OS << ' ' << (*I)->id;
*OS << '\n';
}
}
}
}
}
/// ComputeCallSiteTable - Compute the call-site table. The entry for an invoke
/// has a try-range containing the call, a non-zero landing pad, and an
/// appropriate action. The entry for an ordinary call has a try-range
/// containing the call and zero for the landing pad and the action. Calls
/// marked 'nounwind' have no entry and must not be contained in the try-range
/// of any entry - they form gaps in the table. Entries must be ordered by
/// try-range address.
void DwarfException::
ComputeCallSiteTable(SmallVectorImpl<CallSiteEntry> &CallSites,
const RangeMapType &PadMap,
const SmallVectorImpl<const LandingPadInfo *> &LandingPads,
const SmallVectorImpl<unsigned> &FirstActions) {
// The end label of the previous invoke or nounwind try-range.
MCSymbol *LastLabel = 0;
// Whether there is a potentially throwing instruction (currently this means
// an ordinary call) between the end of the previous try-range and now.
bool SawPotentiallyThrowing = false;
// Whether the last CallSite entry was for an invoke.
bool PreviousIsInvoke = false;
// Visit all instructions in order of address.
for (MachineFunction::const_iterator I = Asm->MF->begin(), E = Asm->MF->end();
I != E; ++I) {
for (MachineBasicBlock::const_iterator MI = I->begin(), E = I->end();
MI != E; ++MI) {
if (!MI->isLabel()) {
if (MI->isCall())
SawPotentiallyThrowing |= !CallToNoUnwindFunction(MI);
continue;
}
// End of the previous try-range?
MCSymbol *BeginLabel = MI->getOperand(0).getMCSymbol();
if (BeginLabel == LastLabel)
SawPotentiallyThrowing = false;
// Beginning of a new try-range?
RangeMapType::const_iterator L = PadMap.find(BeginLabel);
if (L == PadMap.end())
// Nope, it was just some random label.
continue;
const PadRange &P = L->second;
const LandingPadInfo *LandingPad = LandingPads[P.PadIndex];
assert(BeginLabel == LandingPad->BeginLabels[P.RangeIndex] &&
"Inconsistent landing pad map!");
// For Dwarf exception handling (SjLj handling doesn't use this). If some
// instruction between the previous try-range and this one may throw,
// create a call-site entry with no landing pad for the region between the
// try-ranges.
if (SawPotentiallyThrowing && Asm->MAI->isExceptionHandlingDwarf()) {
CallSiteEntry Site = { LastLabel, BeginLabel, 0, 0 };
CallSites.push_back(Site);
PreviousIsInvoke = false;
}
LastLabel = LandingPad->EndLabels[P.RangeIndex];
assert(BeginLabel && LastLabel && "Invalid landing pad!");
if (!LandingPad->LandingPadLabel) {
// Create a gap.
PreviousIsInvoke = false;
} else {
// This try-range is for an invoke.
CallSiteEntry Site = {
BeginLabel,
LastLabel,
LandingPad->LandingPadLabel,
FirstActions[P.PadIndex]
};
// Try to merge with the previous call-site. SJLJ doesn't do this
if (PreviousIsInvoke && Asm->MAI->isExceptionHandlingDwarf()) {
CallSiteEntry &Prev = CallSites.back();
if (Site.PadLabel == Prev.PadLabel && Site.Action == Prev.Action) {
// Extend the range of the previous entry.
Prev.EndLabel = Site.EndLabel;
continue;
}
}
// Otherwise, create a new call-site.
if (Asm->MAI->isExceptionHandlingDwarf())
CallSites.push_back(Site);
else {
// SjLj EH must maintain the call sites in the order assigned
// to them by the SjLjPrepare pass.
unsigned SiteNo = MMI->getCallSiteBeginLabel(BeginLabel);
if (CallSites.size() < SiteNo)
CallSites.resize(SiteNo);
CallSites[SiteNo - 1] = Site;
}
PreviousIsInvoke = true;
}
}
}
// If some instruction between the previous try-range and the end of the
// function may throw, create a call-site entry with no landing pad for the
// region following the try-range.
if (SawPotentiallyThrowing && Asm->MAI->isExceptionHandlingDwarf()) {
CallSiteEntry Site = { LastLabel, 0, 0, 0 };
CallSites.push_back(Site);
}
}
void InterferenceCache::Entry::update(unsigned MBBNum) {
SlotIndex Start, Stop;
tie(Start, Stop) = Indexes->getMBBRange(MBBNum);
// Use advanceTo only when possible.
if (PrevPos != Start) {
if (!PrevPos.isValid() || Start < PrevPos)
for (unsigned i = 0, e = Iters.size(); i != e; ++i)
Iters[i].find(Start);
else
for (unsigned i = 0, e = Iters.size(); i != e; ++i)
Iters[i].advanceTo(Start);
PrevPos = Start;
}
MachineFunction::const_iterator MFI = MF->getBlockNumbered(MBBNum);
BlockInterference *BI = &Blocks[MBBNum];
ArrayRef<SlotIndex> RegMaskSlots;
ArrayRef<const uint32_t*> RegMaskBits;
for (;;) {
BI->Tag = Tag;
BI->First = BI->Last = SlotIndex();
// Check for first interference.
for (unsigned i = 0, e = Iters.size(); i != e; ++i) {
Iter &I = Iters[i];
if (!I.valid())
continue;
SlotIndex StartI = I.start();
if (StartI >= Stop)
continue;
if (!BI->First.isValid() || StartI < BI->First)
BI->First = StartI;
}
// Also check for register mask interference.
RegMaskSlots = LIS->getRegMaskSlotsInBlock(MBBNum);
RegMaskBits = LIS->getRegMaskBitsInBlock(MBBNum);
SlotIndex Limit = BI->First.isValid() ? BI->First : Stop;
for (unsigned i = 0, e = RegMaskSlots.size();
i != e && RegMaskSlots[i] < Limit; ++i)
if (MachineOperand::clobbersPhysReg(RegMaskBits[i], PhysReg)) {
// Register mask i clobbers PhysReg before the LIU interference.
BI->First = RegMaskSlots[i];
break;
}
PrevPos = Stop;
if (BI->First.isValid())
break;
// No interference in this block? Go ahead and precompute the next block.
if (++MFI == MF->end())
return;
MBBNum = MFI->getNumber();
BI = &Blocks[MBBNum];
if (BI->Tag == Tag)
return;
tie(Start, Stop) = Indexes->getMBBRange(MBBNum);
}
// Check for last interference in block.
for (unsigned i = 0, e = Iters.size(); i != e; ++i) {
Iter &I = Iters[i];
if (!I.valid() || I.start() >= Stop)
continue;
I.advanceTo(Stop);
bool Backup = !I.valid() || I.start() >= Stop;
if (Backup)
--I;
SlotIndex StopI = I.stop();
if (!BI->Last.isValid() || StopI > BI->Last)
BI->Last = StopI;
if (Backup)
++I;
}
// Also check for register mask interference.
SlotIndex Limit = BI->Last.isValid() ? BI->Last : Start;
for (unsigned i = RegMaskSlots.size();
i && RegMaskSlots[i-1].getDeadSlot() > Limit; --i)
if (MachineOperand::clobbersPhysReg(RegMaskBits[i-1], PhysReg)) {
// Register mask i-1 clobbers PhysReg after the LIU interference.
// Model the regmask clobber as a dead def.
BI->Last = RegMaskSlots[i-1].getDeadSlot();
break;
}
}
/// runOnMachineFunction - This emits the frame section, autos section and
/// assembly for each instruction. Also takes care of function begin debug
/// directive and file begin debug directive (if required) for the function.
///
bool PIC16AsmPrinter::runOnMachineFunction(MachineFunction &MF) {
this->MF = &MF;
// This calls the base class function required to be called at beginning
// of runOnMachineFunction.
SetupMachineFunction(MF);
// Get the mangled name.
const Function *F = MF.getFunction();
CurrentFnName = Mang->getMangledName(F);
// Emit the function frame (args and temps).
EmitFunctionFrame(MF);
DbgInfo.BeginFunction(MF);
// Emit the autos section of function.
EmitAutos(CurrentFnName);
// Now emit the instructions of function in its code section.
const MCSection *fCodeSection =
getObjFileLowering().getSectionForFunction(CurrentFnName);
// Start the Code Section.
O << "\n";
OutStreamer.SwitchSection(fCodeSection);
// Emit the frame address of the function at the beginning of code.
O << "\tretlw low(" << PAN::getFrameLabel(CurrentFnName) << ")\n";
O << "\tretlw high(" << PAN::getFrameLabel(CurrentFnName) << ")\n";
// Emit function start label.
O << CurrentFnName << ":\n";
DebugLoc CurDL;
O << "\n";
// Print out code for the function.
for (MachineFunction::const_iterator I = MF.begin(), E = MF.end();
I != E; ++I) {
// Print a label for the basic block.
if (I != MF.begin()) {
printBasicBlockLabel(I, true);
O << '\n';
}
// Print a basic block.
for (MachineBasicBlock::const_iterator II = I->begin(), E = I->end();
II != E; ++II) {
// Emit the line directive if source line changed.
const DebugLoc DL = II->getDebugLoc();
if (!DL.isUnknown() && DL != CurDL) {
DbgInfo.ChangeDebugLoc(MF, DL);
CurDL = DL;
}
// Print the assembly for the instruction.
printMachineInstruction(II);
}
}
// Emit function end debug directives.
DbgInfo.EndFunction(MF);
return false; // we didn't modify anything.
}
void MachineVerifier::verifyLiveIntervals() {
assert(LiveInts && "Don't call verifyLiveIntervals without LiveInts");
for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) {
unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
// Spilling and splitting may leave unused registers around. Skip them.
if (MRI->reg_nodbg_empty(Reg))
continue;
if (!LiveInts->hasInterval(Reg)) {
report("Missing live interval for virtual register", MF);
*OS << PrintReg(Reg, TRI) << " still has defs or uses\n";
continue;
}
const LiveInterval &LI = LiveInts->getInterval(Reg);
assert(Reg == LI.reg && "Invalid reg to interval mapping");
for (LiveInterval::const_vni_iterator I = LI.vni_begin(), E = LI.vni_end();
I!=E; ++I) {
VNInfo *VNI = *I;
const VNInfo *DefVNI = LI.getVNInfoAt(VNI->def);
if (!DefVNI) {
if (!VNI->isUnused()) {
report("Valno not live at def and not marked unused", MF);
*OS << "Valno #" << VNI->id << " in " << LI << '\n';
}
continue;
}
if (VNI->isUnused())
continue;
if (DefVNI != VNI) {
report("Live range at def has different valno", MF);
*OS << "Valno #" << VNI->id << " is defined at " << VNI->def
<< " where valno #" << DefVNI->id << " is live in " << LI << '\n';
continue;
}
const MachineBasicBlock *MBB = LiveInts->getMBBFromIndex(VNI->def);
if (!MBB) {
report("Invalid definition index", MF);
*OS << "Valno #" << VNI->id << " is defined at " << VNI->def
<< " in " << LI << '\n';
continue;
}
if (VNI->isPHIDef()) {
if (VNI->def != LiveInts->getMBBStartIdx(MBB)) {
report("PHIDef value is not defined at MBB start", MF);
*OS << "Valno #" << VNI->id << " is defined at " << VNI->def
<< ", not at the beginning of BB#" << MBB->getNumber()
<< " in " << LI << '\n';
}
} else {
// Non-PHI def.
const MachineInstr *MI = LiveInts->getInstructionFromIndex(VNI->def);
if (!MI) {
report("No instruction at def index", MF);
*OS << "Valno #" << VNI->id << " is defined at " << VNI->def
<< " in " << LI << '\n';
continue;
}
bool hasDef = false;
bool isEarlyClobber = false;
for (ConstMIBundleOperands MOI(MI); MOI.isValid(); ++MOI) {
if (!MOI->isReg() || !MOI->isDef())
continue;
if (TargetRegisterInfo::isVirtualRegister(LI.reg)) {
if (MOI->getReg() != LI.reg)
continue;
} else {
if (!TargetRegisterInfo::isPhysicalRegister(MOI->getReg()) ||
!TRI->regsOverlap(LI.reg, MOI->getReg()))
continue;
}
hasDef = true;
if (MOI->isEarlyClobber())
isEarlyClobber = true;
}
if (!hasDef) {
report("Defining instruction does not modify register", MI);
*OS << "Valno #" << VNI->id << " in " << LI << '\n';
}
// Early clobber defs begin at USE slots, but other defs must begin at
// DEF slots.
if (isEarlyClobber) {
if (!VNI->def.isEarlyClobber()) {
report("Early clobber def must be at an early-clobber slot", MF);
*OS << "Valno #" << VNI->id << " is defined at " << VNI->def
<< " in " << LI << '\n';
}
} else if (!VNI->def.isRegister()) {
report("Non-PHI, non-early clobber def must be at a register slot",
MF);
*OS << "Valno #" << VNI->id << " is defined at " << VNI->def
<< " in " << LI << '\n';
}
}
}
for (LiveInterval::const_iterator I = LI.begin(), E = LI.end(); I!=E; ++I) {
const VNInfo *VNI = I->valno;
assert(VNI && "Live range has no valno");
if (VNI->id >= LI.getNumValNums() || VNI != LI.getValNumInfo(VNI->id)) {
report("Foreign valno in live range", MF);
I->print(*OS);
*OS << " has a valno not in " << LI << '\n';
}
if (VNI->isUnused()) {
report("Live range valno is marked unused", MF);
I->print(*OS);
*OS << " in " << LI << '\n';
}
const MachineBasicBlock *MBB = LiveInts->getMBBFromIndex(I->start);
if (!MBB) {
report("Bad start of live segment, no basic block", MF);
I->print(*OS);
*OS << " in " << LI << '\n';
continue;
}
SlotIndex MBBStartIdx = LiveInts->getMBBStartIdx(MBB);
if (I->start != MBBStartIdx && I->start != VNI->def) {
report("Live segment must begin at MBB entry or valno def", MBB);
I->print(*OS);
*OS << " in " << LI << '\n' << "Basic block starts at "
<< MBBStartIdx << '\n';
}
const MachineBasicBlock *EndMBB =
LiveInts->getMBBFromIndex(I->end.getPrevSlot());
if (!EndMBB) {
report("Bad end of live segment, no basic block", MF);
I->print(*OS);
*OS << " in " << LI << '\n';
continue;
}
// No more checks for live-out segments.
if (I->end == LiveInts->getMBBEndIdx(EndMBB))
continue;
// The live segment is ending inside EndMBB
const MachineInstr *MI =
LiveInts->getInstructionFromIndex(I->end.getPrevSlot());
if (!MI) {
report("Live segment doesn't end at a valid instruction", EndMBB);
I->print(*OS);
*OS << " in " << LI << '\n' << "Basic block starts at "
<< MBBStartIdx << '\n';
continue;
}
// The block slot must refer to a basic block boundary.
if (I->end.isBlock()) {
report("Live segment ends at B slot of an instruction", MI);
I->print(*OS);
*OS << " in " << LI << '\n';
}
if (I->end.isDead()) {
// Segment ends on the dead slot.
// That means there must be a dead def.
if (!SlotIndex::isSameInstr(I->start, I->end)) {
report("Live segment ending at dead slot spans instructions", MI);
I->print(*OS);
*OS << " in " << LI << '\n';
}
}
// A live segment can only end at an early-clobber slot if it is being
// redefined by an early-clobber def.
if (I->end.isEarlyClobber()) {
if (I+1 == E || (I+1)->start != I->end) {
report("Live segment ending at early clobber slot must be "
"redefined by an EC def in the same instruction", MI);
I->print(*OS);
*OS << " in " << LI << '\n';
}
}
// The following checks only apply to virtual registers. Physreg liveness
// is too weird to check.
if (TargetRegisterInfo::isVirtualRegister(LI.reg)) {
// A live range can end with either a redefinition, a kill flag on a
// use, or a dead flag on a def.
bool hasRead = false;
bool hasDeadDef = false;
for (ConstMIBundleOperands MOI(MI); MOI.isValid(); ++MOI) {
if (!MOI->isReg() || MOI->getReg() != LI.reg)
continue;
if (MOI->readsReg())
hasRead = true;
if (MOI->isDef() && MOI->isDead())
hasDeadDef = true;
}
if (I->end.isDead()) {
if (!hasDeadDef) {
report("Instruction doesn't have a dead def operand", MI);
I->print(*OS);
*OS << " in " << LI << '\n';
}
} else {
if (!hasRead) {
report("Instruction ending live range doesn't read the register",
MI);
I->print(*OS);
*OS << " in " << LI << '\n';
}
}
}
// Now check all the basic blocks in this live segment.
MachineFunction::const_iterator MFI = MBB;
// Is this live range the beginning of a non-PHIDef VN?
if (I->start == VNI->def && !VNI->isPHIDef()) {
// Not live-in to any blocks.
if (MBB == EndMBB)
continue;
// Skip this block.
++MFI;
}
for (;;) {
assert(LiveInts->isLiveInToMBB(LI, MFI));
// We don't know how to track physregs into a landing pad.
if (TargetRegisterInfo::isPhysicalRegister(LI.reg) &&
MFI->isLandingPad()) {
if (&*MFI == EndMBB)
break;
++MFI;
continue;
}
// Is VNI a PHI-def in the current block?
bool IsPHI = VNI->isPHIDef() &&
VNI->def == LiveInts->getMBBStartIdx(MFI);
// Check that VNI is live-out of all predecessors.
for (MachineBasicBlock::const_pred_iterator PI = MFI->pred_begin(),
PE = MFI->pred_end(); PI != PE; ++PI) {
SlotIndex PEnd = LiveInts->getMBBEndIdx(*PI);
const VNInfo *PVNI = LI.getVNInfoBefore(PEnd);
// All predecessors must have a live-out value.
if (!PVNI) {
report("Register not marked live out of predecessor", *PI);
*OS << "Valno #" << VNI->id << " live into BB#" << MFI->getNumber()
<< '@' << LiveInts->getMBBStartIdx(MFI) << ", not live before "
<< PEnd << " in " << LI << '\n';
continue;
}
// Only PHI-defs can take different predecessor values.
if (!IsPHI && PVNI != VNI) {
report("Different value live out of predecessor", *PI);
*OS << "Valno #" << PVNI->id << " live out of BB#"
<< (*PI)->getNumber() << '@' << PEnd
<< "\nValno #" << VNI->id << " live into BB#" << MFI->getNumber()
<< '@' << LiveInts->getMBBStartIdx(MFI) << " in "
<< PrintReg(Reg) << ": " << LI << '\n';
}
}
if (&*MFI == EndMBB)
break;
++MFI;
}
}
// Check the LI only has one connected component.
if (TargetRegisterInfo::isVirtualRegister(LI.reg)) {
ConnectedVNInfoEqClasses ConEQ(*LiveInts);
unsigned NumComp = ConEQ.Classify(&LI);
if (NumComp > 1) {
report("Multiple connected components in live interval", MF);
*OS << NumComp << " components in " << LI << '\n';
for (unsigned comp = 0; comp != NumComp; ++comp) {
*OS << comp << ": valnos";
for (LiveInterval::const_vni_iterator I = LI.vni_begin(),
E = LI.vni_end(); I!=E; ++I)
if (comp == ConEQ.getEqClass(*I))
*OS << ' ' << (*I)->id;
*OS << '\n';
}
}
}
}
}
void InterferenceCache::Entry::update(unsigned MBBNum) {
SlotIndex Start, Stop;
tie(Start, Stop) = Indexes->getMBBRange(MBBNum);
// Use advanceTo only when possible.
if (PrevPos != Start) {
if (!PrevPos.isValid() || Start < PrevPos)
for (unsigned i = 0, e = Iters.size(); i != e; ++i)
Iters[i].find(Start);
else
for (unsigned i = 0, e = Iters.size(); i != e; ++i)
Iters[i].advanceTo(Start);
PrevPos = Start;
}
MachineFunction::const_iterator MFI = MF->getBlockNumbered(MBBNum);
BlockInterference *BI = &Blocks[MBBNum];
for (;;) {
BI->Tag = Tag;
BI->First = BI->Last = SlotIndex();
// Check for first interference.
for (unsigned i = 0, e = Iters.size(); i != e; ++i) {
Iter &I = Iters[i];
if (!I.valid())
continue;
SlotIndex StartI = I.start();
if (StartI >= Stop)
continue;
if (!BI->First.isValid() || StartI < BI->First)
BI->First = StartI;
}
PrevPos = Stop;
if (BI->First.isValid())
break;
// No interference in this block? Go ahead and precompute the next block.
if (++MFI == MF->end())
return;
MBBNum = MFI->getNumber();
BI = &Blocks[MBBNum];
if (BI->Tag == Tag)
return;
tie(Start, Stop) = Indexes->getMBBRange(MBBNum);
}
// Check for last interference in block.
for (unsigned i = 0, e = Iters.size(); i != e; ++i) {
Iter &I = Iters[i];
if (!I.valid() || I.start() >= Stop)
continue;
I.advanceTo(Stop);
bool Backup = !I.valid() || I.start() >= Stop;
if (Backup)
--I;
SlotIndex StopI = I.stop();
if (!BI->Last.isValid() || StopI > BI->Last)
BI->Last = StopI;
if (Backup)
++I;
}
}
/// runOnMachineFunction - This uses the printMachineInstruction()
/// method to print assembly for each instruction.
///
bool X86IntelAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
SetupMachineFunction(MF);
O << "\n\n";
// Print out constants referenced by the function
EmitConstantPool(MF.getConstantPool());
// Print out labels for the function.
const Function *F = MF.getFunction();
unsigned CC = F->getCallingConv();
// Populate function information map. Actually, We don't want to populate
// non-stdcall or non-fastcall functions' information right now.
if (CC == CallingConv::X86_StdCall || CC == CallingConv::X86_FastCall)
FunctionInfoMap[F] = *MF.getInfo<X86MachineFunctionInfo>();
decorateName(CurrentFnName, F);
SwitchToTextSection("_text", F);
unsigned FnAlign = 4;
if (F->hasFnAttr(Attribute::OptimizeForSize))
FnAlign = 1;
switch (F->getLinkage()) {
default: assert(0 && "Unsupported linkage type!");
case Function::PrivateLinkage:
case Function::InternalLinkage:
EmitAlignment(FnAlign);
break;
case Function::DLLExportLinkage:
DLLExportedFns.insert(CurrentFnName);
//FALLS THROUGH
case Function::ExternalLinkage:
O << "\tpublic " << CurrentFnName << "\n";
EmitAlignment(FnAlign);
break;
}
O << CurrentFnName << "\tproc near\n";
// Print out code for the function.
for (MachineFunction::const_iterator I = MF.begin(), E = MF.end();
I != E; ++I) {
// Print a label for the basic block if there are any predecessors.
if (!I->pred_empty()) {
printBasicBlockLabel(I, true, true);
O << '\n';
}
for (MachineBasicBlock::const_iterator II = I->begin(), E = I->end();
II != E; ++II) {
// Print the assembly for the instruction.
printMachineInstruction(II);
}
}
// Print out jump tables referenced by the function.
EmitJumpTableInfo(MF.getJumpTableInfo(), MF);
O << CurrentFnName << "\tendp\n";
O.flush();
// We didn't modify anything.
return false;
}
/// runOnMachineFunction - This uses the printInstruction()
/// method to print assembly for each instruction.
///
bool PIC16AsmPrinter::runOnMachineFunction(MachineFunction &MF) {
this->MF = &MF;
// This calls the base class function required to be called at beginning
// of runOnMachineFunction.
SetupMachineFunction(MF);
// Get the mangled name.
const Function *F = MF.getFunction();
CurrentFnName = Mang->getValueName(F);
// Emit the function variables.
EmitFunctionFrame(MF);
// Emit function begin debug directives
DbgInfo.EmitFunctBeginDI(F);
EmitAutos(CurrentFnName);
const char *codeSection = PAN::getCodeSectionName(CurrentFnName).c_str();
const Section *fCodeSection = TAI->getNamedSection(codeSection,
SectionFlags::Code);
O << "\n";
// Start the Code Section.
SwitchToSection (fCodeSection);
// Emit the frame address of the function at the beginning of code.
O << "\tretlw low(" << PAN::getFrameLabel(CurrentFnName) << ")\n";
O << "\tretlw high(" << PAN::getFrameLabel(CurrentFnName) << ")\n";
// Emit function start label.
O << CurrentFnName << ":\n";
// For emitting line directives, we need to keep track of the current
// source line. When it changes then only emit the line directive.
unsigned CurLine = 0;
O << "\n";
// Print out code for the function.
for (MachineFunction::const_iterator I = MF.begin(), E = MF.end();
I != E; ++I) {
// Print a label for the basic block.
if (I != MF.begin()) {
printBasicBlockLabel(I, true);
O << '\n';
}
for (MachineBasicBlock::const_iterator II = I->begin(), E = I->end();
II != E; ++II) {
// Emit the line directive if source line changed.
const DebugLoc DL = II->getDebugLoc();
if (!DL.isUnknown()) {
unsigned line = MF.getDebugLocTuple(DL).Line;
if (line != CurLine) {
O << "\t.line " << line << "\n";
CurLine = line;
}
}
// Print the assembly for the instruction.
printMachineInstruction(II);
}
}
// Emit function end debug directives.
DbgInfo.EmitFunctEndDI(F, CurLine);
return false; // we didn't modify anything.
}
bool AccessFrequency::runOnMachineFunction(MachineFunction &mf)
{
MF = &mf;
MRI = &mf.getRegInfo();
TRI = MF->getTarget().getRegisterInfo();
m_nVars = 0;
const llvm::Function *fn = mf.getFunction();
std::string szMain = "main";
if(fn->getName() != szMain && g_hFuncCall[szMain].find(fn->getName()) == g_hFuncCall[szMain].end() )
{
errs() << "--------qali:--------Skip function " << fn->getName() << " in AccessFrequency !\n";
return true;
}
for (MachineFunction::const_iterator FI = MF->begin(), FE = MF->end();
FI != FE; ++FI)
{
double dFactor = 0.0;
const BasicBlock *bb = FI->getBasicBlock();
if( bb != NULL )
{
//const std::map<const Function *, std::map<const BasicBlock *, double> > &hF2B2Acc =(SP->BlockInformation);
std::map<const Function *, std::map<const BasicBlock *, double> >::const_iterator f2b2acc_p, E = g_hF2B2Acc->end();
if( (f2b2acc_p = g_hF2B2Acc->find(fn) ) != E )
{
std::map<const BasicBlock *, double>::const_iterator b2acc_p, EE = f2b2acc_p->second.end();
if( (b2acc_p = f2b2acc_p->second.find(bb) ) != EE )
dFactor = b2acc_p->second;
}
}
if( dFactor == 0.0 )
dFactor = 1.0;
for (MachineBasicBlock::const_iterator BBI = FI->begin(), BBE = FI->end();
BBI != BBE; ++BBI)
{
DEBUG(BBI->print(dbgs(), NULL ));
//MachineInstr *MI = BBI;
for (unsigned i = 0, e = BBI->getNumOperands(); i != e; ++ i)
{
const MachineOperand &MO = BBI->getOperand(i);
// TODO (qali#1#): To hack other kinds of MachineOperands
switch (MO.getType() )
{
case MachineOperand::MO_Register:
if( MO.getReg() != 0
&& TargetRegisterInfo::isVirtualRegister(MO.getReg()) )
{
unsigned MOReg = MO.getReg();
unsigned int nSize = getRegSize(MOReg);
if( MO.isUse() )
{
int nAcc = ROUND(dFactor);
m_RegReadMap[MOReg] = m_RegReadMap[MOReg] + dFactor;
//if( nAcc >= 1)
m_SimTrace.push_back(llvm::TraceRecord(MOReg, nAcc));
}
else if( MO.isDef())
{
int nAcc = ROUND(dFactor);
m_RegWriteMap[MOReg] = m_RegWriteMap[MOReg] + dFactor;
//if( nAcc >= 1)
m_SimTrace.push_back(llvm::TraceRecord(MOReg, nAcc, false));
}
else
assert("Unrecoganized operation in AccessFrequency::runOnMachineFunction!\n");
}
break;
default:
break;
}
}
// Analyze the memoperations
if(!BBI->memoperands_empty() )
{
for( MachineInstr::mmo_iterator i = BBI->memoperands_begin(), e = BBI->memoperands_end();
i != e; ++ i) {
if( (*i)->isLoad() )
{
const char *tmp = (**i).getValue()->getName().data();
m_StackReadMap[tmp] ++;
}
else if( (*i)->isStore())
{
const char *tmp = (**i).getValue()->getName().data();
m_StackWriteMap[tmp] ++;
}
else
{
assert(false);
dbgs() << __FILE__ << __LINE__;
}
}
}
}
}
m_nVars = m_RegReadMap.size();
//print(afout);
//printInt(afout);
//reset();
std::string szInfo;
std::string szSrcFile = mf.getMMI().getModule()->getModuleIdentifier();
std::string szFile = szSrcFile + ".accInt";
raw_fd_ostream accIfout(szFile.c_str(), szInfo, raw_fd_ostream::F_Append );
printInt(accIfout);
accIfout.close();
szFile = szSrcFile + ".acc";
raw_fd_ostream accfout(szFile.c_str(), szInfo, raw_fd_ostream::F_Append );
print(accfout);
accfout.close();
szFile = szSrcFile + "." + "var";
raw_fd_ostream varfout(szFile.c_str(), szInfo, raw_fd_ostream::F_Append );
printVars(varfout);
varfout.close();
szFile = szSrcFile + ".read";
raw_fd_ostream readfout(szFile.c_str(), szInfo, raw_fd_ostream::F_Append );
printRead(readfout);
readfout.close();
szFile = szSrcFile + ".write";
raw_fd_ostream writefout(szFile.c_str(), szInfo, raw_fd_ostream::F_Append );
printWrite(writefout);
writefout.close();
szFile = szSrcFile + ".size";
raw_fd_ostream sizefout(szFile.c_str(), szInfo, raw_fd_ostream::F_Append );
printSize(sizefout);
sizefout.close();
return true;
}
void BT::run() {
reset();
assert(FlowQ.empty());
typedef GraphTraits<const MachineFunction*> MachineFlowGraphTraits;
const MachineBasicBlock *Entry = MachineFlowGraphTraits::getEntryNode(&MF);
unsigned MaxBN = 0;
for (MachineFunction::const_iterator I = MF.begin(), E = MF.end();
I != E; ++I) {
assert(I->getNumber() >= 0 && "Disconnected block");
unsigned BN = I->getNumber();
if (BN > MaxBN)
MaxBN = BN;
}
// Keep track of visited blocks.
BitVector BlockScanned(MaxBN+1);
int EntryN = Entry->getNumber();
// Generate a fake edge to get something to start with.
FlowQ.push(CFGEdge(-1, EntryN));
while (!FlowQ.empty()) {
CFGEdge Edge = FlowQ.front();
FlowQ.pop();
if (EdgeExec.count(Edge))
continue;
EdgeExec.insert(Edge);
const MachineBasicBlock &B = *MF.getBlockNumbered(Edge.second);
MachineBasicBlock::const_iterator It = B.begin(), End = B.end();
// Visit PHI nodes first.
while (It != End && It->isPHI()) {
const MachineInstr &PI = *It++;
InstrExec.insert(&PI);
visitPHI(PI);
}
// If this block has already been visited through a flow graph edge,
// then the instructions have already been processed. Any updates to
// the cells would now only happen through visitUsesOf...
if (BlockScanned[Edge.second])
continue;
BlockScanned[Edge.second] = true;
// Visit non-branch instructions.
while (It != End && !It->isBranch()) {
const MachineInstr &MI = *It++;
InstrExec.insert(&MI);
visitNonBranch(MI);
}
// If block end has been reached, add the fall-through edge to the queue.
if (It == End) {
MachineFunction::const_iterator BIt = B.getIterator();
MachineFunction::const_iterator Next = std::next(BIt);
if (Next != MF.end() && B.isSuccessor(&*Next)) {
int ThisN = B.getNumber();
int NextN = Next->getNumber();
FlowQ.push(CFGEdge(ThisN, NextN));
}
} else {
// Handle the remaining sequence of branches. This function will update
// the work queue.
visitBranchesFrom(*It);
}
} // while (!FlowQ->empty())
if (Trace)
print_cells(dbgs() << "Cells after propagation:\n");
}
unsigned char* JITDwarfEmitter::EmitExceptionTable(MachineFunction* MF,
unsigned char* StartFunction,
unsigned char* EndFunction) const {
assert(MMI && "MachineModuleInfo not registered!");
// Map all labels and get rid of any dead landing pads.
MMI->TidyLandingPads(JCE->getLabelLocations());
const std::vector<const GlobalVariable *> &TypeInfos = MMI->getTypeInfos();
const std::vector<unsigned> &FilterIds = MMI->getFilterIds();
const std::vector<LandingPadInfo> &PadInfos = MMI->getLandingPads();
if (PadInfos.empty()) return 0;
// Sort the landing pads in order of their type ids. This is used to fold
// duplicate actions.
SmallVector<const LandingPadInfo *, 64> LandingPads;
LandingPads.reserve(PadInfos.size());
for (unsigned i = 0, N = PadInfos.size(); i != N; ++i)
LandingPads.push_back(&PadInfos[i]);
std::sort(LandingPads.begin(), LandingPads.end(), PadLT);
// Negative type ids index into FilterIds, positive type ids index into
// TypeInfos. The value written for a positive type id is just the type
// id itself. For a negative type id, however, the value written is the
// (negative) byte offset of the corresponding FilterIds entry. The byte
// offset is usually equal to the type id, because the FilterIds entries
// are written using a variable width encoding which outputs one byte per
// entry as long as the value written is not too large, but can differ.
// This kind of complication does not occur for positive type ids because
// type infos are output using a fixed width encoding.
// FilterOffsets[i] holds the byte offset corresponding to FilterIds[i].
SmallVector<int, 16> FilterOffsets;
FilterOffsets.reserve(FilterIds.size());
int Offset = -1;
for(std::vector<unsigned>::const_iterator I = FilterIds.begin(),
E = FilterIds.end(); I != E; ++I) {
FilterOffsets.push_back(Offset);
Offset -= MCAsmInfo::getULEB128Size(*I);
}
// Compute the actions table and gather the first action index for each
// landing pad site.
SmallVector<ActionEntry, 32> Actions;
SmallVector<unsigned, 64> FirstActions;
FirstActions.reserve(LandingPads.size());
int FirstAction = 0;
unsigned SizeActions = 0;
for (unsigned i = 0, N = LandingPads.size(); i != N; ++i) {
const LandingPadInfo *LP = LandingPads[i];
const std::vector<int> &TypeIds = LP->TypeIds;
const unsigned NumShared = i ? SharedTypeIds(LP, LandingPads[i-1]) : 0;
unsigned SizeSiteActions = 0;
if (NumShared < TypeIds.size()) {
unsigned SizeAction = 0;
ActionEntry *PrevAction = 0;
if (NumShared) {
const unsigned SizePrevIds = LandingPads[i-1]->TypeIds.size();
assert(Actions.size());
PrevAction = &Actions.back();
SizeAction = MCAsmInfo::getSLEB128Size(PrevAction->NextAction) +
MCAsmInfo::getSLEB128Size(PrevAction->ValueForTypeID);
for (unsigned j = NumShared; j != SizePrevIds; ++j) {
SizeAction -= MCAsmInfo::getSLEB128Size(PrevAction->ValueForTypeID);
SizeAction += -PrevAction->NextAction;
PrevAction = PrevAction->Previous;
}
}
// Compute the actions.
for (unsigned I = NumShared, M = TypeIds.size(); I != M; ++I) {
int TypeID = TypeIds[I];
assert(-1-TypeID < (int)FilterOffsets.size() && "Unknown filter id!");
int ValueForTypeID = TypeID < 0 ? FilterOffsets[-1 - TypeID] : TypeID;
unsigned SizeTypeID = MCAsmInfo::getSLEB128Size(ValueForTypeID);
int NextAction = SizeAction ? -(SizeAction + SizeTypeID) : 0;
SizeAction = SizeTypeID + MCAsmInfo::getSLEB128Size(NextAction);
SizeSiteActions += SizeAction;
ActionEntry Action = {ValueForTypeID, NextAction, PrevAction};
Actions.push_back(Action);
PrevAction = &Actions.back();
}
// Record the first action of the landing pad site.
FirstAction = SizeActions + SizeSiteActions - SizeAction + 1;
} // else identical - re-use previous FirstAction
FirstActions.push_back(FirstAction);
// Compute this sites contribution to size.
SizeActions += SizeSiteActions;
}
// Compute the call-site table. Entries must be ordered by address.
SmallVector<CallSiteEntry, 64> CallSites;
RangeMapType PadMap;
for (unsigned i = 0, N = LandingPads.size(); i != N; ++i) {
const LandingPadInfo *LandingPad = LandingPads[i];
for (unsigned j=0, E = LandingPad->BeginLabels.size(); j != E; ++j) {
MCSymbol *BeginLabel = LandingPad->BeginLabels[j];
assert(!PadMap.count(BeginLabel) && "Duplicate landing pad labels!");
PadRange P = { i, j };
PadMap[BeginLabel] = P;
}
}
bool MayThrow = false;
MCSymbol *LastLabel = 0;
for (MachineFunction::const_iterator I = MF->begin(), E = MF->end();
I != E; ++I) {
for (MachineBasicBlock::const_iterator MI = I->begin(), E = I->end();
MI != E; ++MI) {
if (!MI->isLabel()) {
MayThrow |= MI->getDesc().isCall();
continue;
}
MCSymbol *BeginLabel = MI->getOperand(0).getMCSymbol();
assert(BeginLabel && "Invalid label!");
if (BeginLabel == LastLabel)
MayThrow = false;
RangeMapType::iterator L = PadMap.find(BeginLabel);
if (L == PadMap.end())
continue;
PadRange P = L->second;
const LandingPadInfo *LandingPad = LandingPads[P.PadIndex];
assert(BeginLabel == LandingPad->BeginLabels[P.RangeIndex] &&
"Inconsistent landing pad map!");
// If some instruction between the previous try-range and this one may
// throw, create a call-site entry with no landing pad for the region
// between the try-ranges.
if (MayThrow) {
CallSiteEntry Site = {LastLabel, BeginLabel, 0, 0};
CallSites.push_back(Site);
}
LastLabel = LandingPad->EndLabels[P.RangeIndex];
CallSiteEntry Site = {BeginLabel, LastLabel,
LandingPad->LandingPadLabel, FirstActions[P.PadIndex]};
assert(Site.BeginLabel && Site.EndLabel && Site.PadLabel &&
"Invalid landing pad!");
// Try to merge with the previous call-site.
if (CallSites.size()) {
CallSiteEntry &Prev = CallSites.back();
if (Site.PadLabel == Prev.PadLabel && Site.Action == Prev.Action) {
// Extend the range of the previous entry.
Prev.EndLabel = Site.EndLabel;
continue;
}
}
// Otherwise, create a new call-site.
CallSites.push_back(Site);
}
}
// If some instruction between the previous try-range and the end of the
// function may throw, create a call-site entry with no landing pad for the
// region following the try-range.
if (MayThrow) {
CallSiteEntry Site = {LastLabel, 0, 0, 0};
CallSites.push_back(Site);
}
// Final tallies.
unsigned SizeSites = CallSites.size() * (sizeof(int32_t) + // Site start.
sizeof(int32_t) + // Site length.
sizeof(int32_t)); // Landing pad.
for (unsigned i = 0, e = CallSites.size(); i < e; ++i)
SizeSites += MCAsmInfo::getULEB128Size(CallSites[i].Action);
unsigned SizeTypes = TypeInfos.size() * TD->getPointerSize();
unsigned TypeOffset = sizeof(int8_t) + // Call site format
// Call-site table length
MCAsmInfo::getULEB128Size(SizeSites) +
SizeSites + SizeActions + SizeTypes;
// Begin the exception table.
JCE->emitAlignmentWithFill(4, 0);
// Asm->EOL("Padding");
unsigned char* DwarfExceptionTable = (unsigned char*)JCE->getCurrentPCValue();
// Emit the header.
JCE->emitByte(dwarf::DW_EH_PE_omit);
// Asm->EOL("LPStart format (DW_EH_PE_omit)");
JCE->emitByte(dwarf::DW_EH_PE_absptr);
// Asm->EOL("TType format (DW_EH_PE_absptr)");
JCE->emitULEB128Bytes(TypeOffset);
// Asm->EOL("TType base offset");
JCE->emitByte(dwarf::DW_EH_PE_udata4);
// Asm->EOL("Call site format (DW_EH_PE_udata4)");
JCE->emitULEB128Bytes(SizeSites);
// Asm->EOL("Call-site table length");
// Emit the landing pad site information.
for (unsigned i = 0; i < CallSites.size(); ++i) {
CallSiteEntry &S = CallSites[i];
intptr_t BeginLabelPtr = 0;
intptr_t EndLabelPtr = 0;
if (!S.BeginLabel) {
BeginLabelPtr = (intptr_t)StartFunction;
JCE->emitInt32(0);
} else {
BeginLabelPtr = JCE->getLabelAddress(S.BeginLabel);
JCE->emitInt32(BeginLabelPtr - (intptr_t)StartFunction);
}
// Asm->EOL("Region start");
if (!S.EndLabel)
EndLabelPtr = (intptr_t)EndFunction;
else
EndLabelPtr = JCE->getLabelAddress(S.EndLabel);
JCE->emitInt32(EndLabelPtr - BeginLabelPtr);
//Asm->EOL("Region length");
if (!S.PadLabel) {
JCE->emitInt32(0);
} else {
unsigned PadLabelPtr = JCE->getLabelAddress(S.PadLabel);
JCE->emitInt32(PadLabelPtr - (intptr_t)StartFunction);
}
// Asm->EOL("Landing pad");
JCE->emitULEB128Bytes(S.Action);
// Asm->EOL("Action");
}
// Emit the actions.
for (unsigned I = 0, N = Actions.size(); I != N; ++I) {
ActionEntry &Action = Actions[I];
JCE->emitSLEB128Bytes(Action.ValueForTypeID);
//Asm->EOL("TypeInfo index");
JCE->emitSLEB128Bytes(Action.NextAction);
//Asm->EOL("Next action");
}
// Emit the type ids.
for (unsigned M = TypeInfos.size(); M; --M) {
const GlobalVariable *GV = TypeInfos[M - 1];
if (GV) {
if (TD->getPointerSize() == sizeof(int32_t))
JCE->emitInt32((intptr_t)Jit.getOrEmitGlobalVariable(GV));
else
JCE->emitInt64((intptr_t)Jit.getOrEmitGlobalVariable(GV));
} else {
if (TD->getPointerSize() == sizeof(int32_t))
JCE->emitInt32(0);
else
JCE->emitInt64(0);
}
// Asm->EOL("TypeInfo");
}
// Emit the filter typeids.
for (unsigned j = 0, M = FilterIds.size(); j < M; ++j) {
unsigned TypeID = FilterIds[j];
JCE->emitULEB128Bytes(TypeID);
//Asm->EOL("Filter TypeInfo index");
}
JCE->emitAlignmentWithFill(4, 0);
return DwarfExceptionTable;
}
/// PrepareMonoLSDA - Collect information needed by EmitMonoLSDA
///
/// This function collects information available only during EndFunction which is needed
/// by EmitMonoLSDA and stores it into EHFrameInfo. It is the same as the
/// beginning of EmitExceptionTable.
///
void DwarfMonoException::PrepareMonoLSDA(FunctionEHFrameInfo *EHFrameInfo) {
const std::vector<const GlobalVariable *> &TypeInfos = MMI->getTypeInfos();
const std::vector<LandingPadInfo> &PadInfos = MMI->getLandingPads();
const MachineFunction *MF = Asm->MF;
// Sort the landing pads in order of their type ids. This is used to fold
// duplicate actions.
SmallVector<const LandingPadInfo *, 64> LandingPads;
LandingPads.reserve(PadInfos.size());
for (unsigned i = 0, N = PadInfos.size(); i != N; ++i)
LandingPads.push_back(&PadInfos[i]);
std::sort(LandingPads.begin(), LandingPads.end(),
[](const LandingPadInfo *L,
const LandingPadInfo *R) { return L->TypeIds < R->TypeIds; });
// Invokes and nounwind calls have entries in PadMap (due to being bracketed
// by try-range labels when lowered). Ordinary calls do not, so appropriate
// try-ranges for them need be deduced when using DWARF exception handling.
RangeMapType PadMap;
for (unsigned i = 0, N = LandingPads.size(); i != N; ++i) {
const LandingPadInfo *LandingPad = LandingPads[i];
for (unsigned j = 0, E = LandingPad->BeginLabels.size(); j != E; ++j) {
MCSymbol *BeginLabel = LandingPad->BeginLabels[j];
assert(!PadMap.count(BeginLabel) && "Duplicate landing pad labels!");
PadRange P = { i, j };
PadMap[BeginLabel] = P;
}
}
// Compute the call-site table.
SmallVector<MonoCallSiteEntry, 64> CallSites;
MCSymbol *LastLabel = 0;
for (MachineFunction::const_iterator I = MF->begin(), E = MF->end();
I != E; ++I) {
for (MachineBasicBlock::const_iterator MI = I->begin(), E = I->end();
MI != E; ++MI) {
if (!MI->isLabel()) {
continue;
}
MCSymbol *BeginLabel = MI->getOperand(0).getMCSymbol();
assert(BeginLabel && "Invalid label!");
RangeMapType::iterator L = PadMap.find(BeginLabel);
if (L == PadMap.end())
continue;
PadRange P = L->second;
const LandingPadInfo *LandingPad = LandingPads[P.PadIndex];
assert(BeginLabel == LandingPad->BeginLabels[P.RangeIndex] &&
"Inconsistent landing pad map!");
// Mono emits one landing pad for each CLR exception clause,
// and the type info contains the clause index
assert (LandingPad->TypeIds.size() == 1);
assert (LandingPad->LandingPadLabel);
LastLabel = LandingPad->EndLabels[P.RangeIndex];
MonoCallSiteEntry Site = {BeginLabel, LastLabel,
LandingPad->LandingPadLabel, LandingPad->TypeIds [0]};
assert(Site.BeginLabel && Site.EndLabel && Site.PadLabel &&
"Invalid landing pad!");
// FIXME: This doesn't work because it includes ranges outside clauses
#if 0
// Try to merge with the previous call-site.
if (CallSites.size()) {
MonoCallSiteEntry &Prev = CallSites.back();
if (Site.PadLabel == Prev.PadLabel && Site.TypeID == Prev.TypeID) {
// Extend the range of the previous entry.
Prev.EndLabel = Site.EndLabel;
continue;
}
}
#endif
// Otherwise, create a new call-site.
CallSites.push_back(Site);
}
}
//
// Compute a mapping from method names to their AOT method index
//
if (FuncIndexes.size () == 0) {
const Module *m = MMI->getModule ();
NamedMDNode *indexes = m->getNamedMetadata ("mono.function_indexes");
if (indexes) {
for (unsigned int i = 0; i < indexes->getNumOperands (); ++i) {
MDNode *n = indexes->getOperand (i);
MDString *s = (MDString*)n->getOperand (0);
ConstantInt *idx = (ConstantInt*)n->getOperand (1);
FuncIndexes.GetOrCreateValue (s->getString (), (int)idx->getLimitedValue () + 1);
}
}
}
MonoEHFrameInfo *MonoEH = &EHFrameInfo->MonoEH;
// Save information for EmitMonoLSDA
MonoEH->MF = Asm->MF;
MonoEH->FunctionNumber = Asm->getFunctionNumber();
MonoEH->CallSites.insert(MonoEH->CallSites.begin(), CallSites.begin(), CallSites.end());
MonoEH->TypeInfos = TypeInfos;
MonoEH->PadInfos = PadInfos;
MonoEH->MonoMethodIdx = FuncIndexes.lookup (Asm->MF->getFunction ()->getName ()) - 1;
//outs()<<"A:"<<Asm->MF->getFunction()->getName() << " " << MonoEH->MonoMethodIdx << "\n";
int ThisSlot = Asm->MF->getMonoInfo()->getThisStackSlot();
if (ThisSlot != -1) {
unsigned FrameReg;
MonoEH->ThisOffset = Asm->MF->getTarget ().getSubtargetImpl ()->getFrameLowering ()->getFrameIndexReference (*Asm->MF, ThisSlot, FrameReg);
MonoEH->FrameReg = Asm->MF->getTarget ().getSubtargetImpl ()->getRegisterInfo ()->getDwarfRegNum (FrameReg, true);
} else {
MonoEH->FrameReg = -1;
}
}
