static void L2()
{register object *base=vs_base;
register object *sup=base+VM2; VC2
vs_check;
bds_check;
{object V3;
check_arg(5);
V3=(base[0]);
vs_top=sup;
goto TTL;
TTL:;
base[5]=make_cclosure_new(LC6,Cnil,Cnil,Cdata);
base[5]=MMcons(base[5],Cnil);
base[6]=make_cclosure_new(LC7,Cnil,base[5],Cdata);
base[6]=MMcons(base[6],base[5]);
base[7]= (base[5]->c.c_car);
base[8]= (base[6]->c.c_car);
bds_bind(VV[0],base[7]);
bds_bind(VV[1],base[8]);
vs_base=vs_top;
L5(base);
bds_unwind1;
bds_unwind1;
return;
}
}
__libc_csu_fini(
_unknown_ __eax, // r0
_unknown_ __ebx, // r1
signed int __edx // r3
)
{// addr = 0x08048388
intOrPtr _v8; // _cfa_fffffff8
_unknown_ _v12; // _cfa_fffffff4
_unknown_ __ebp; // r6
_unknown_ _t7; // _t7
signed int _t9; // _t9
signed int _t11; // _t11
intOrPtr _t12; // _t12
_unknown_ _t13; // _t13
_unknown_ _t14; // _t14
_unknown_ _t15; // _t15
_unknown_ _t16; // _t16
__edx = __edx;
_push(__ebx);
_push(__eax);
_t9 = 0 >> 2;
_t11 = _t9 - 1;
if(_t9 != 0) {
while(1) {
*((intOrPtr*)(134517780 + _t11 * 4))();
__edx = _t11;
_t11 = _t11 - 1;
if(__edx == 0) {
break;
}
}
}
_t12 = _v8;
__esp = _t15;
_pop(__ebp);
_push(_t15);
_push(_t12);
_push(__edx);
L5();
_pop(__ebx);
__do_global_dtors_aux();
return;
}
//------------------------------------------------------------------------------
virtual FP Generate()
{
nsArch::nsx86::Cx86HLAIntrinsics& HLA( *( dynamic_cast< nsArch::nsx86::Cx86HLAIntrinsics* >( m_pHLA ) ) );
nsArch::nsx86::CCPU& CPU = dynamic_cast< nsArch::nsx86::CCPU& >( TheMachine()->Logic().CPU() );
//static const Cmp_unsigned__int32 PAGESIZE = 4096;
CPU.clear();
nsArch::nsx86::CLabel L1( CPU.newLabel() );
nsArch::nsx86::CLabel L2( CPU.newLabel() );
nsArch::nsx86::CLabel L3( CPU.newLabel() );
nsArch::nsx86::CLabel L4( CPU.newLabel() );
nsArch::nsx86::CLabel L5( CPU.newLabel() );
nsArch::nsx86::CLabel L6( CPU.newLabel() );
nsArch::nsx86::CLabel L7( CPU.newLabel() );
nsArch::nsx86::CLabel L8( CPU.newLabel() );
//CPU.int3();
CPU.push( CPU.reg_ebx() );
CPU.push( CPU.reg_edi() );
CPU.xor_( CPU.reg_edi(), CPU.reg_edi() ); //result sign assumed positive
CPU.mov( CPU.reg_eax(), nsArch::nsx86::CMem( CPU.reg_esp(), 16 ) ); //Hi Word of dividend
CPU.or_( CPU.reg_eax(), CPU.reg_eax() ); //test to see if signed
CPU.jge( L1 ); //skip rest if a is already positive
CPU.inc( CPU.reg_edi() ); //complement result sign flag bit
CPU.mov( CPU.reg_edx(), nsArch::nsx86::CMem( CPU.reg_esp(), 12 ) ); //Lo Word of dividend
CPU.neg( CPU.reg_eax() ); //make a positive
CPU.neg( CPU.reg_edx() );
CPU.sbb( CPU.reg_eax(), 0 );
CPU.mov( nsArch::nsx86::CMem( CPU.reg_esp(), 16 ), CPU.reg_eax() ); //save positive value
CPU.mov( nsArch::nsx86::CMem( CPU.reg_esp(), 12 ), CPU.reg_edx() );
CPU.bind( L1 );
CPU.mov( CPU.reg_eax(), nsArch::nsx86::CMem( CPU.reg_esp(), 24 ) ); //hi word of b
CPU.or_( CPU.reg_eax(), CPU.reg_eax() ); //test to see if signed
CPU.jge( L2 ); //skip rest if b is already positive
CPU.mov( CPU.reg_edx(), nsArch::nsx86::CMem( CPU.reg_esp(), 20 ) ); //lo word of b
CPU.neg( CPU.reg_eax() ); //make b positive
CPU.neg( CPU.reg_edx() );
CPU.sbb( CPU.reg_eax(), 0 );
CPU.mov( nsArch::nsx86::CMem( CPU.reg_esp(), 24 ), CPU.reg_eax() );
CPU.mov( nsArch::nsx86::CMem( CPU.reg_esp(), 20 ), CPU.reg_edx() ); //save positive value
CPU.bind( L2 );
CPU.or_( CPU.reg_eax(), CPU.reg_eax() ); //check to see if divisor < 4194304K
CPU.jnz( L3 ); //nope, gotta do this the hard way
CPU.mov( CPU.reg_ecx(), nsArch::nsx86::CMem( CPU.reg_esp(), 20 ) ); //load divisor
CPU.mov( CPU.reg_eax(), nsArch::nsx86::CMem( CPU.reg_esp(), 16 ) ); //load high word of dividend
CPU.xor_( CPU.reg_edx(), CPU.reg_edx() );
CPU.div( CPU.reg_ecx() ); //edx <- remainder
CPU.mov( CPU.reg_eax(), nsArch::nsx86::CMem( CPU.reg_esp(), 12 ) ); //edx:eax <- remainder:lo word of dividend
CPU.div( CPU.reg_ecx() ); //edx <- final remainder
CPU.mov( CPU.reg_eax(), CPU.reg_edx() ); //edx:eax <- remainder
CPU.xor_( CPU.reg_edx(), CPU.reg_edx() );
CPU.dec( CPU.reg_edi() ); //check result sign flag
CPU.jns( L4 ); //negate result, restore stack and return
CPU.jmp( L8 ); //result sign ok, restore stack and return
CPU.bind( L3 );
CPU.mov( CPU.reg_ebx(), CPU.reg_eax() ); //ebx:ecx <- divisor
CPU.mov( CPU.reg_ecx(), nsArch::nsx86::CMem( CPU.reg_esp(), 20 ) ); //load low word of divisor
CPU.mov( CPU.reg_edx(), nsArch::nsx86::CMem( CPU.reg_esp(), 16 ) ); //load high word of dividend
CPU.mov( CPU.reg_eax(), nsArch::nsx86::CMem( CPU.reg_esp(), 12 ) ); //load low word of dividend
CPU.bind( L5 );
CPU.shr( CPU.reg_ebx(), 1 ); //shift divisor right one bit
CPU.rcr( CPU.reg_ecx(), 1 );
CPU.shr( CPU.reg_edx(), 1 ); //shift dividend right one bit
CPU.rcr( CPU.reg_eax(), 1 );
CPU.or_( CPU.reg_ebx(), CPU.reg_ebx() );
CPU.jnz( L5 ); //loop until divisor < 4194304K
CPU.div( CPU.reg_ecx() ); //now divide, ignore remainder
CPU.mov( CPU.reg_ecx(), CPU.reg_eax() ); //save a copy of quotient in ECX
CPU.mul( nsArch::nsx86::dword_ptr( CPU.reg_esp(), 24 ) );
CPU.xchg( CPU.reg_ecx(), CPU.reg_eax() ); //save product, get quotient in EAX
CPU.mul( nsArch::nsx86::dword_ptr( CPU.reg_esp(), 20 ) );
CPU.add( CPU.reg_edx(), CPU.reg_ecx() ); //EDX:EAX = QUOT * DVSR
CPU.jc( L6 ); //carry means Quotient is off by 1
CPU.cmp( CPU.reg_edx(), nsArch::nsx86::CMem( CPU.reg_esp(), 16 ) ); //compare hi words of result and original
CPU.ja( L6 ); //if result > original, do subtract
CPU.jb( L7 ); //if result < original, we are ok
CPU.cmp( CPU.reg_eax(), nsArch::nsx86::CMem( CPU.reg_esp(), 12 ) ); // hi words are equal, compare lo words
CPU.jbe( L7 ); //if less or equal we are ok, else subtract
CPU.bind( L6 );
CPU.sub( CPU.reg_eax(), nsArch::nsx86::CMem( CPU.reg_esp(), 20 ) ); //subtract divisor from result
CPU.sbb( CPU.reg_edx(), nsArch::nsx86::CMem( CPU.reg_esp(), 24 ) );
CPU.bind( L7 );
CPU.sub( CPU.reg_eax(), nsArch::nsx86::CMem( CPU.reg_esp(), 12 ) ); //subtract dividend from result
CPU.sbb( CPU.reg_edx(), nsArch::nsx86::CMem( CPU.reg_esp(), 16 ) );
CPU.dec( CPU.reg_edi() ); //check result sign flag
CPU.jns( L8 ); //result is ok, restore stack and return
CPU.bind( L4 );
CPU.neg( CPU.reg_edx() ); //otherwise, negate the result
CPU.neg( CPU.reg_eax() );
CPU.sbb( CPU.reg_edx(), 0 );
CPU.bind( L8 );
CPU.pop( CPU.reg_edi() );
CPU.pop( CPU.reg_ebx() );
CPU.ret( nsArch::nsx86::CImm( 16 ) );
// Make JIT function.
FP fn = reinterpret_cast< FP >( CPU.make() );
// Ensure that everything is ok and write the launchpad
if( fn )
{
m_bGenerated = true;
if( m_pLaunchPad )
{
HLA.WriteLaunchPad( (byte*)fn, m_pLaunchPad );
}
}
return fn;
}
/*
f3x5[]
each symbol is 3x5 => 15 bits
a-z offset 0 length 26
0-9 offset 26 length 10
# offset 36 length 1
*/
unsigned short f3x5[] = {
// A
L1(011) |
L2(101) |
L3(101) |
L4(111) |
L5(101)
,
// B
L1(110) |
L2(101) |
L3(110) |
L4(101) |
L5(110)
,
// C
L1(011) |
L2(101) |
L3(100) |
L4(100) |
L5(011)
,
