s32 tsdemux_init(u32 vid, u32 aid, u32 sid, u32 pcrid, bool is_hevc)
{
s32 r;
u32 parser_sub_start_ptr;
u32 parser_sub_end_ptr;
u32 parser_sub_rp;
u32 pcr_num;
#if MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON6
switch_mod_gate_by_type(MOD_DEMUX, 1);
#endif
parser_sub_start_ptr = READ_MPEG_REG(PARSER_SUB_START_PTR);
parser_sub_end_ptr = READ_MPEG_REG(PARSER_SUB_END_PTR);
parser_sub_rp = READ_MPEG_REG(PARSER_SUB_RP);
WRITE_MPEG_REG(RESET1_REGISTER, RESET_PARSER);
#ifdef ENABLE_DEMUX_DRIVER
tsdemux_reset();
#else
WRITE_MPEG_REG(RESET1_REGISTER, RESET_PARSER | RESET_DEMUXSTB);
WRITE_MPEG_REG(STB_TOP_CONFIG, 0);
WRITE_MPEG_REG(DEMUX_CONTROL, 0);
#endif
/* set PID filter */
printk("tsdemux video_pid = 0x%x, audio_pid = 0x%x, sub_pid = 0x%x, pcrid = 0x%x\n",
vid, aid, sid, pcrid);
#ifndef ENABLE_DEMUX_DRIVER
WRITE_MPEG_REG(FM_WR_DATA,
(((vid & 0x1fff) | (VIDEO_PACKET << 13)) << 16) |
((aid & 0x1fff) | (AUDIO_PACKET << 13)));
WRITE_MPEG_REG(FM_WR_ADDR, 0x8000);
while (READ_MPEG_REG(FM_WR_ADDR) & 0x8000) {
;
}
WRITE_MPEG_REG(FM_WR_DATA,
(((sid & 0x1fff) | (SUB_PACKET << 13)) << 16) | 0xffff);
WRITE_MPEG_REG(FM_WR_ADDR, 0x8001);
while (READ_MPEG_REG(FM_WR_ADDR) & 0x8000) {
;
}
WRITE_MPEG_REG(MAX_FM_COMP_ADDR, 1);
WRITE_MPEG_REG(STB_INT_MASK, 0);
WRITE_MPEG_REG(STB_INT_STATUS, 0xffff);
/* TS data path */
WRITE_MPEG_REG(FEC_INPUT_CONTROL, 0x7000);
WRITE_MPEG_REG(DEMUX_MEM_REQ_EN,
(1 << VIDEO_PACKET) |
(1 << AUDIO_PACKET) |
(1 << SUB_PACKET));
WRITE_MPEG_REG(DEMUX_ENDIAN,
(7 << OTHER_ENDIAN) |
(7 << BYPASS_ENDIAN) |
(0 << SECTION_ENDIAN));
WRITE_MPEG_REG(TS_HIU_CTL, 1 << USE_HI_BSF_INTERFACE);
WRITE_MPEG_REG(TS_FILE_CONFIG,
(demux_skipbyte << 16) |
(6 << DES_OUT_DLY) |
(3 << TRANSPORT_SCRAMBLING_CONTROL_ODD) |
(1 << TS_HIU_ENABLE) |
(4 << FEC_FILE_CLK_DIV));
/* enable TS demux */
WRITE_MPEG_REG(DEMUX_CONTROL, (1 << STB_DEMUX_ENABLE) | (1 << KEEP_DUPLICATE_PACKAGE));
#endif
if (fetchbuf == 0) {
printk("%s: no fetchbuf\n", __FUNCTION__);
return -ENOMEM;
}
/* hook stream buffer with PARSER */
#if MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON8
if (HAS_HEVC_VDEC && is_hevc) {
WRITE_MPEG_REG(PARSER_VIDEO_START_PTR,
READ_VREG(HEVC_STREAM_START_ADDR));
WRITE_MPEG_REG(PARSER_VIDEO_END_PTR,
READ_VREG(HEVC_STREAM_END_ADDR) - 8);
CLEAR_MPEG_REG_MASK(PARSER_ES_CONTROL, ES_VID_MAN_RD_PTR);
WRITE_VREG(DOS_GEN_CTRL0, 3<<1); // set vififo_vbuf_rp_sel=>hevc
SET_VREG_MASK(HEVC_STREAM_CONTROL, (1<<3)|(0<<4)); // set use_parser_vbuf_wp
SET_VREG_MASK(HEVC_STREAM_CONTROL, 1); // set stream_fetch_enable
SET_VREG_MASK(HEVC_STREAM_FIFO_CTL, (1<<29)); // set stream_buffer_hole with 256 bytes
} else
#endif
{
WRITE_MPEG_REG(PARSER_VIDEO_START_PTR,
READ_VREG(VLD_MEM_VIFIFO_START_PTR));
WRITE_MPEG_REG(PARSER_VIDEO_END_PTR,
READ_VREG(VLD_MEM_VIFIFO_END_PTR));
CLEAR_MPEG_REG_MASK(PARSER_ES_CONTROL, ES_VID_MAN_RD_PTR);
WRITE_VREG(VLD_MEM_VIFIFO_BUF_CNTL, MEM_BUFCTRL_INIT);
CLEAR_VREG_MASK(VLD_MEM_VIFIFO_BUF_CNTL, MEM_BUFCTRL_INIT);
if (HAS_HEVC_VDEC) {
WRITE_VREG(DOS_GEN_CTRL0, 0); // set vififo_vbuf_rp_sel=>vdec
}
}
WRITE_MPEG_REG(PARSER_AUDIO_START_PTR,
READ_MPEG_REG(AIU_MEM_AIFIFO_START_PTR));
WRITE_MPEG_REG(PARSER_AUDIO_END_PTR,
READ_MPEG_REG(AIU_MEM_AIFIFO_END_PTR));
CLEAR_MPEG_REG_MASK(PARSER_ES_CONTROL, ES_AUD_MAN_RD_PTR);
WRITE_MPEG_REG(PARSER_CONFIG,
(10 << PS_CFG_PFIFO_EMPTY_CNT_BIT) |
(1 << PS_CFG_MAX_ES_WR_CYCLE_BIT) |
(16 << PS_CFG_MAX_FETCH_CYCLE_BIT));
WRITE_MPEG_REG(AIU_MEM_AIFIFO_BUF_CNTL, MEM_BUFCTRL_INIT);
CLEAR_MPEG_REG_MASK(AIU_MEM_AIFIFO_BUF_CNTL, MEM_BUFCTRL_INIT);
WRITE_MPEG_REG(PARSER_SUB_START_PTR, parser_sub_start_ptr);
WRITE_MPEG_REG(PARSER_SUB_END_PTR, parser_sub_end_ptr);
WRITE_MPEG_REG(PARSER_SUB_RP, parser_sub_rp);
SET_MPEG_REG_MASK(PARSER_ES_CONTROL, (7 << ES_SUB_WR_ENDIAN_BIT) | ES_SUB_MAN_RD_PTR);
#if MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON8
if (HAS_HEVC_VDEC)
r = pts_start((is_hevc) ? PTS_TYPE_HEVC : PTS_TYPE_VIDEO);
else
#endif
r = pts_start(PTS_TYPE_VIDEO);
if (r < 0) {
printk("Video pts start failed.(%d)\n", r);
goto err1;
}
if ((r = pts_start(PTS_TYPE_AUDIO)) < 0) {
printk("Audio pts start failed.(%d)\n", r);
goto err2;
}
r = request_irq(INT_PARSER, parser_isr,
IRQF_SHARED, "tsdemux-fetch",
(void *)tsdemux_fetch_id);
if (r) {
goto err3;
}
WRITE_MPEG_REG(PARSER_INT_STATUS, 0xffff);
WRITE_MPEG_REG(PARSER_INT_ENABLE, PARSER_INTSTAT_FETCH_CMD << PARSER_INT_HOST_EN_BIT);
WRITE_MPEG_REG(PARSER_VIDEO_HOLE, 0x400);
WRITE_MPEG_REG(PARSER_AUDIO_HOLE, 0x400);
discontinued_counter = 0;
#ifndef ENABLE_DEMUX_DRIVER
r = request_irq(INT_DEMUX, tsdemux_isr,
IRQF_SHARED, "tsdemux-irq",
(void *)tsdemux_irq_id);
WRITE_MPEG_REG(STB_INT_MASK,
(1 << SUB_PES_READY)
| (1 << NEW_PDTS_READY)
| (1 << DIS_CONTINUITY_PACKET));
if (r) {
goto err4;
}
#else
tsdemux_config();
tsdemux_request_irq(tsdemux_isr, (void *)tsdemux_irq_id);
if (vid < 0x1FFF) {
tsdemux_set_vid(vid);
}
if (aid < 0x1FFF) {
tsdemux_set_aid(aid);
}
if (sid < 0x1FFF) {
tsdemux_set_sid(sid);
}
if ((pcrid < 0x1FFF) && (pcrid != vid) && (pcrid != aid) && (pcrid != sid)) {
tsdemux_set_pcrid(pcrid);
}
#endif
if (pcrid < 0x1FFF){
/* set paramater to fetch pcr */
pcr_num=0;
if(pcrid == vid)
pcr_num=0;
else if(pcrid == aid)
pcr_num=1;
else
pcr_num=3;
if(READ_MPEG_REG(TS_HIU_CTL_2) & 0x40){
WRITE_MPEG_REG(PCR90K_CTL_2, 12 << 1);
WRITE_MPEG_REG(ASSIGN_PID_NUMBER_2, pcr_num);
printk("[tsdemux_init] To use device 2,pcr_num=%d \n",pcr_num);
}
else if(READ_MPEG_REG(TS_HIU_CTL_3) & 0x40){
WRITE_MPEG_REG(PCR90K_CTL_3, 12 << 1);
WRITE_MPEG_REG(ASSIGN_PID_NUMBER_3, pcr_num);
printk("[tsdemux_init] To use device 3,pcr_num=%d \n",pcr_num);
}
else{
WRITE_MPEG_REG(PCR90K_CTL, 12 << 1);
WRITE_MPEG_REG(ASSIGN_PID_NUMBER, pcr_num);
printk("[tsdemux_init] To use device 1,pcr_num=%d \n",pcr_num);
}
first_pcr = 0;
pcrscr_valid=1;
}
return 0;
#ifndef ENABLE_DEMUX_DRIVER
err4:
free_irq(INT_PARSER, (void *)tsdemux_fetch_id);
#endif
err3:
pts_stop(PTS_TYPE_AUDIO);
err2:
#if MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON8
if (HAS_HEVC_VDEC)
pts_stop((is_hevc) ? PTS_TYPE_HEVC : PTS_TYPE_VIDEO);
else
#endif
pts_stop(PTS_TYPE_VIDEO);
err1:
printk("TS Demux init failed.\n");
return -ENOENT;
}
static inline void feed_vb(s32 s)
{
u32 addr = READ_MPEG_REG(VLD_MEM_VIFIFO_START_PTR);
amlog_mask_level(LOG_MASK_PARSER,LOG_LEVEL_LOW,"feed start addr:0x%x\n",addr);
WRITE_MPEG_REG(VLD_MEM_VIFIFO_WP, (addr + s + PADDINGSIZE + 7) & ~7);
}
static ssize_t _rmparser_write(const char __user *buf, size_t count)
{
size_t r = count;
const char __user *p = buf;
u32 len;
int ret;
static int halt_droped_len=0;
u32 vwp,awp;
if (r > 0) {
len = min(r, (size_t)FETCHBUF_SIZE);
if (copy_from_user(fetchbuf_remap, p, len)) {
return -EFAULT;
}
fetch_done = 0;
wmb();
vwp=buf_wp(BUF_TYPE_VIDEO);
awp=buf_wp(BUF_TYPE_AUDIO);
WRITE_MPEG_REG(PARSER_FETCH_ADDR, virt_to_phys((u8 *)fetchbuf));
WRITE_MPEG_REG(PARSER_FETCH_CMD,
(7 << FETCH_ENDIAN) | len);
ret = wait_event_interruptible_timeout(rm_wq, fetch_done != 0, HZ/10);
if (ret == 0) {
WRITE_MPEG_REG(PARSER_FETCH_CMD, 0);
parse_halt ++;
printk("write timeout, retry,halt_count=%d parse_control=%x \n",
parse_halt,READ_MPEG_REG(PARSER_CONTROL));
vreal_set_fatal_flag(1);
if(parse_halt > 10) {
WRITE_MPEG_REG(PARSER_CONTROL, (ES_SEARCH | ES_PARSER_START));
printk("reset parse_control=%x\n",READ_MPEG_REG(PARSER_CONTROL));
}
return -EAGAIN;
} else if (ret < 0) {
return -ERESTARTSYS;
}
if(vwp==buf_wp(BUF_TYPE_VIDEO) && awp==buf_wp(BUF_TYPE_AUDIO)){
if((parse_halt+1)%10==1)
printk("Video&Audio WP not changed after write,video %x->%x,Audio:%x-->%x,parse_halt=%d\n",
vwp,buf_wp(BUF_TYPE_VIDEO),awp,buf_wp(BUF_TYPE_AUDIO),parse_halt);
parse_halt ++;/*wp not changed ,we think have bugs on parser now.*/
if(parse_halt > 10 && (stbuf_level(get_buf_by_type(BUF_TYPE_VIDEO))< 1000 || stbuf_level(get_buf_by_type(BUF_TYPE_AUDIO))< 100))
{/*reset while at least one is underflow.*/
WRITE_MPEG_REG(PARSER_CONTROL, (ES_SEARCH | ES_PARSER_START));
printk("reset parse_control=%x\n",READ_MPEG_REG(PARSER_CONTROL));
}
if(parse_halt <= 10 || halt_droped_len <100*1024){/*drops first 10 pkt ,some times maybe no av data*/
printk("drop this pkt=%d,len=%d\n",parse_halt,len);
p += len;
r -= len;
halt_droped_len+=len;
}else{
return -EAGAIN;
}
}else{
halt_droped_len=0;
parse_halt = 0;
p += len;
r -= len;
}
}
return count - r;
}
u32 timestamp_apts_get(void)
{
return READ_MPEG_REG(AUDIO_PTS);
}
u32 stbuf_sub_start_get(void)
{
return READ_MPEG_REG(PARSER_SUB_START_PTR);
}
void aml_m1_reset(struct snd_soc_codec* codec, bool first_time)
{
unsigned long data32;
if(first_time){
/* initialize clock for audiodac */
audio_set_clk(AUDIO_CLK_FREQ_48,0);
/* power up pll */
WRITE_MPEG_REG( HHI_AUD_PLL_CNTL, READ_MPEG_REG(HHI_AUD_PLL_CNTL) & ~(1 << 15));
/* enable audiodac clock */
WRITE_MPEG_REG_BITS(HHI_AUD_CLK_CNTL, 1, 23, 1);
msleep(100);
data32 = 0;
data32 |= 0 << 15; // [15] audac_soft_reset_n
data32 |= 0 << 14; // [14] audac_reset_ctrl: 0=use audac_reset_n pulse from reset module; 1=use audac_soft_reset_n.
data32 |= 0 << 9; // [9] delay_rd_en
data32 |= 0 << 8; // [8] audac_reg_clk_inv
data32 |= 0 << 1; // [7:1] audac_i2caddr
data32 |= 0 << 0; // [0] audac_intfsel: 0=use host bus; 1=use I2C.
WRITE_MPEG_REG(AIU_AUDAC_CTRL0, data32);
// Enable APB3 fail on error
data32 = 0;
data32 |= 1 << 15; // [15] err_en
data32 |= 255 << 0; // [11:0] max_err
WRITE_MPEG_REG(AIU_AUDAC_CTRL1, data32);
snd_soc_write(codec, ADAC_RESET, (0<<1));
snd_soc_write(codec, ADAC_RESET, (0<<1));
snd_soc_write(codec, ADAC_RESET, (0<<1));
snd_soc_write(codec, ADAC_RESET, (0<<1));
snd_soc_write(codec, ADAC_RESET, (0<<1));
msleep(100);
snd_soc_write(codec,ADAC_CLOCK, 0);
snd_soc_write(codec,ADAC_I2S_CONFIG_REG1, 6);
snd_soc_write(codec, ADAC_I2S_CONFIG_REG2, 1|(1<<3)); // I2S, split
snd_soc_write(codec, ADAC_POWER_CTRL_REG1, 0xc3);
snd_soc_write(codec, ADAC_POWER_CTRL_REG2, 0);
snd_soc_write(codec, ADAC_MUTE_CTRL_REG1,0);
snd_soc_write(codec,ADAC_DAC_ADC_MIXER, 0);
snd_soc_write(codec,ADAC_PLAYBACK_VOL_CTRL_LSB, 0x54);
snd_soc_write(codec,ADAC_PLAYBACK_VOL_CTRL_MSB, 0x54);
snd_soc_write(codec,ADAC_STEREO_HS_VOL_CTRL_LSB, 0x28);
snd_soc_write(codec,ADAC_STEREO_HS_VOL_CTRL_MSB, 0x28);
latch(codec);
snd_soc_write(codec, ADAC_POWER_CTRL_REG2, (0<<7));
latch(codec);
snd_soc_write(codec, ADAC_POWER_CTRL_REG2, (1<<7));
latch(codec);
}else{
latch(codec);
snd_soc_write(codec, ADAC_POWER_CTRL_REG2, (0<<7));
latch(codec);
snd_soc_write(codec, ADAC_POWER_CTRL_REG2, (1<<7));
latch(codec);
}
snd_soc_write(codec, ADAC_RESET, (0<<1));
latch(codec);
snd_soc_write(codec, ADAC_RESET, (1<<1));
latch(codec);
msleep(100);
}
u32 timestamp_vpts_get(void)
{
return READ_MPEG_REG(VIDEO_PTS);
}
unsigned int read_i2s_rd_ptr(void)
{
unsigned int val;
val = READ_MPEG_REG(AIU_MEM_I2S_RD_PTR);
return val;
}
unsigned int read_i2s_mute_swap_reg(void)
{
unsigned int val;
val = READ_MPEG_REG(AIU_I2S_MUTE_SWAP);
return val;
}
static void lvds_port_disable(void)
{
//disable minilvds_data channel
WRITE_MPEG_REG(LVDS_PHY_CNTL4, READ_MPEG_REG(LVDS_PHY_CNTL4) & ~(0x7f<<0));
}
void audio_set_clk(unsigned freq, unsigned fs_config)
{
int i;
struct clk *clk;
int xtal = 0;
int (*audio_clock_config)[2];
// if (fs_config == AUDIO_CLK_256FS) {
if(1){
int index=0;
switch(freq)
{
case AUDIO_CLK_FREQ_192:
index=4;
break;
case AUDIO_CLK_FREQ_96:
index=3;
break;
case AUDIO_CLK_FREQ_48:
index=2;
break;
case AUDIO_CLK_FREQ_441:
index=1;
break;
case AUDIO_CLK_FREQ_32:
index=0;
break;
case AUDIO_CLK_FREQ_8:
index = 5;
break;
case AUDIO_CLK_FREQ_11:
index = 6;
break;
case AUDIO_CLK_FREQ_12:
index = 7;
break;
case AUDIO_CLK_FREQ_16:
index = 8;
break;
case AUDIO_CLK_FREQ_22:
index = 9;
break;
case AUDIO_CLK_FREQ_24:
index = 10;
break;
default:
index=0;
break;
};
// get system crystal freq
clk=clk_get_sys("clk_xtal", NULL);
if(!clk)
{
printk(KERN_ERR "can't find clk %s for AUDIO PLL SETTING!\n\n","clk_xtal");
//return -1;
}
else
{
xtal=clk_get_rate(clk);
xtal=xtal/1000000;
if(xtal>=24 && xtal <=25)/*current only support 24,25*/
{
xtal-=24;
}
else
{
printk(KERN_WARNING "UNsupport xtal setting for audio xtal=%d,default to 24M\n",xtal);
xtal=0;
}
}
audio_clock_config = audio_clock_config_table[xtal];
// gate the clock off
WRITE_MPEG_REG( HHI_AUD_CLK_CNTL, READ_MPEG_REG(HHI_AUD_CLK_CNTL) & ~(1 << 8));
#ifdef CONFIG_SND_AML_M2
WRITE_MPEG_REG(HHI_AUD_PLL_CNTL2, 0x065e31ff);
WRITE_MPEG_REG(HHI_AUD_PLL_CNTL3, 0x9649a941);
// select Audio PLL as MCLK source
WRITE_MPEG_REG( HHI_AUD_CLK_CNTL, READ_MPEG_REG(HHI_AUD_CLK_CNTL) & ~(1 << 9));
#endif
// Put the PLL to sleep
WRITE_MPEG_REG( HHI_AUD_PLL_CNTL, READ_MPEG_REG(HHI_AUD_PLL_CNTL) | (1 << 15));
#ifdef CONFIG_SND_AML_M2
WRITE_MPEG_REG_BITS(AIU_CODEC_ADC_LRCLK_CTRL, 64-1, 0, 12);
WRITE_MPEG_REG_BITS(AIU_CODEC_DAC_LRCLK_CTRL, 64-1, 0, 12);
#endif
// Bring out of reset but keep bypassed to allow to stablize
//Wr( HHI_AUD_PLL_CNTL, (1 << 15) | (0 << 14) | (hiu_reg & 0x3FFF) );
WRITE_MPEG_REG( HHI_AUD_PLL_CNTL, (1 << 15) | (audio_clock_config[index][0] & 0x7FFF) );
// Set the XD value
WRITE_MPEG_REG( HHI_AUD_CLK_CNTL, (READ_MPEG_REG(HHI_AUD_CLK_CNTL) & ~(0xff << 0)) | audio_clock_config[index][1]);
// delay 5uS
//udelay(5);
for (i = 0; i < 500000; i++) ;
// Bring the PLL out of sleep
WRITE_MPEG_REG( HHI_AUD_PLL_CNTL, READ_MPEG_REG(HHI_AUD_PLL_CNTL) & ~(1 << 15));
// gate the clock on
WRITE_MPEG_REG( HHI_AUD_CLK_CNTL, READ_MPEG_REG(HHI_AUD_CLK_CNTL) | (1 << 8));
#if ((defined CONFIG_SND_AML_M1) || (defined CONFIG_SND_AML_M2))
WRITE_MPEG_REG(HHI_AUD_CLK_CNTL, READ_MPEG_REG(HHI_AUD_CLK_CNTL) |(1<<23));
#endif
// delay 2uS
//udelay(2);
for (i = 0; i < 200000; i++) ;
} else if (fs_config == AUDIO_CLK_384FS) {
}
}
static void lvds_port_enable(void)
{
printk("\n\nLVDS port enable.\n");
//enable minilvds_data channel
WRITE_MPEG_REG(LVDS_PHY_CNTL4, READ_MPEG_REG(LVDS_PHY_CNTL4) | (0x2f<<0));
}
void am_set_regmap(unsigned int cnt, struct am_reg_s *p)
{
unsigned short i;
unsigned int temp = 0;
for (i=0; i<cnt; i++) {
switch (p->type)
{
case REG_TYPE_PHY:
#ifdef PQ_DEBUG_EN
pr_info("%s: bus type: phy..............\n", __func__);
#endif
break;
case REG_TYPE_CBUS:
if (p->mask == 0xffffffff)
WRITE_CBUS_REG(p->addr, p->val);
else
WRITE_CBUS_REG(p->addr, (READ_CBUS_REG(p->addr) & (~p->mask)) | (p->val & p->mask));
#ifdef PQ_DEBUG_EN
pr_info("%s: cbus: Reg0x%x = 0x%x...............\n", __func__, p->addr, (p->val & p->mask));
#endif
break;
case REG_TYPE_APB:
if (p->mask == 0xffffffff)
WRITE_APB_REG(p->addr, p->val);
else
WRITE_APB_REG(p->addr, (READ_APB_REG(p->addr) & (~p->mask)) | (p->val & p->mask));
#ifdef PQ_DEBUG_EN
pr_info("%s: apb bus: Reg0x%x = 0x%x...............\n", __func__, p->addr, (p->val & p->mask));
#endif
break;
case REG_TYPE_MPEG:
if (p->mask == 0xffffffff)
WRITE_MPEG_REG(p->addr, p->val);
else
WRITE_MPEG_REG(p->addr, (READ_MPEG_REG(p->addr) & (~p->mask)) | (p->val & p->mask));
#ifdef PQ_DEBUG_EN
pr_info("%s: mpeg: Reg0x%x = 0x%x...............\n", __func__, p->addr, (p->val & p->mask));
#endif
break;
case REG_TYPE_AXI:
if (p->mask == 0xffffffff)
WRITE_AXI_REG(p->addr, p->val);
else
WRITE_AXI_REG(p->addr, (READ_AXI_REG(p->addr) & (~p->mask)) | (p->val & p->mask));
#ifdef PQ_DEBUG_EN
pr_info("%s: axi: Reg0x%x = 0x%x...............\n", __func__, p->addr, (p->val & p->mask));
#endif
break;
case REG_TYPE_AHB:
if (p->mask == 0xffffffff)
WRITE_AHB_REG(p->addr, p->val);
else
WRITE_AHB_REG(p->addr, (READ_AHB_REG(p->addr) & (~p->mask)) | (p->val & p->mask));
#ifdef PQ_DEBUG_EN
pr_info("%s: ahb: Reg0x%x = 0x%x...............\n", __func__, p->addr, (p->val & p->mask));
#endif
break;
case REG_TYPE_INDEX_VPPCHROMA:
WRITE_CBUS_REG(VPP_CHROMA_ADDR_PORT, p->addr);
if (p->mask == 0xffffffff)
{
WRITE_CBUS_REG(VPP_CHROMA_DATA_PORT, p->val);
}
else
{
temp = READ_CBUS_REG(VPP_CHROMA_DATA_PORT);
WRITE_CBUS_REG(VPP_CHROMA_ADDR_PORT, p->addr);
WRITE_CBUS_REG(VPP_CHROMA_DATA_PORT, (temp & (~p->mask)) | (p->val & p->mask));
}
#ifdef PQ_DEBUG_EN
pr_info("%s: vppchroma: 0x1d70:port0x%x = 0x%x...............\n", __func__, p->addr, (p->val & p->mask));
#endif
break;
case REG_TYPE_INDEX_GAMMA:
#ifdef PQ_DEBUG_EN
pr_info("%s: bus type: REG_TYPE_INDEX_GAMMA..............\n", __func__);
#endif
break;
case VALUE_TYPE_CONTRAST_BRIGHTNESS:
#ifdef PQ_DEBUG_EN
pr_info("%s: bus type: VALUE_TYPE_CONTRAST_BRIGHTNESS..............\n", __func__);
#endif
break;
case REG_TYPE_INDEX_VPP_COEF:
if (((p->addr&0xf) == 0)||((p->addr&0xf) == 0x8))
{
WRITE_CBUS_REG(VPP_CHROMA_ADDR_PORT, p->addr);
WRITE_CBUS_REG(VPP_CHROMA_DATA_PORT, p->val);
}
else
{
WRITE_CBUS_REG(VPP_CHROMA_DATA_PORT, p->val);
}
#ifdef PQ_DEBUG_EN
pr_info("%s: vppcoef: 0x1d70:port0x%x = 0x%x...............\n", __func__, p->addr, (p->val & p->mask));
#endif
break;
default:
pr_info("%s: bus type error!!!bustype = 0x%x................\n", __func__, p->type);
break;
}
p++;
}
return;
}
void am_set_regmap(struct am_regs_s *p)
{
unsigned short i;
unsigned int temp = 0;
for (i=0; i<p->length; i++) {
switch (p->am_reg[i].type)
{
case REG_TYPE_PHY:
#ifdef PQ_DEBUG_EN
pr_info("%s: bus type: phy..............\n", __func__);
#endif
break;
case REG_TYPE_CBUS:
if (p->am_reg[i].mask == 0xffffffff)
WRITE_CBUS_REG(p->am_reg[i].addr, p->am_reg[i].val);
else
WRITE_CBUS_REG(p->am_reg[i].addr, (READ_CBUS_REG(p->am_reg[i].addr) & (~(p->am_reg[i].mask))) | (p->am_reg[i].val & p->am_reg[i].mask));
#ifdef PQ_DEBUG_EN
pr_info("%s: cbus: Reg0x%x(%u)=0x%x(%u)val=%x(%u)mask=%x(%u)\n", __func__, p->am_reg[i].addr,p->am_reg[i].addr,
(p->am_reg[i].val & p->am_reg[i].mask),(p->am_reg[i].val & p->am_reg[i].mask),
p->am_reg[i].val,p->am_reg[i].val,p->am_reg[i].mask,p->am_reg[i].mask);
#endif
break;
case REG_TYPE_APB:
if (p->am_reg[i].mask == 0xffffffff)
WRITE_APB_REG(p->am_reg[i].addr, p->am_reg[i].val);
else
WRITE_APB_REG(p->am_reg[i].addr, (READ_APB_REG(p->am_reg[i].addr) & (~(p->am_reg[i].mask))) | (p->am_reg[i].val & p->am_reg[i].mask));
#ifdef PQ_DEBUG_EN
pr_info("%s: apb: Reg0x%x(%u)=0x%x(%u)val=%x(%u)mask=%x(%u)\n", __func__, p->am_reg[i].addr,p->am_reg[i].addr,
(p->am_reg[i].val & p->am_reg[i].mask),(p->am_reg[i].val & p->am_reg[i].mask),
p->am_reg[i].val,p->am_reg[i].val,p->am_reg[i].mask,p->am_reg[i].mask);
#endif
break;
case REG_TYPE_MPEG:
if (p->am_reg[i].mask == 0xffffffff)
WRITE_MPEG_REG(p->am_reg[i].addr, p->am_reg[i].val);
else
WRITE_MPEG_REG(p->am_reg[i].addr, (READ_MPEG_REG(p->am_reg[i].addr) & (~(p->am_reg[i].mask))) | (p->am_reg[i].val & p->am_reg[i].mask));
#ifdef PQ_DEBUG_EN
pr_info("%s: mpeg: Reg0x%x(%u)=0x%x(%u)val=%x(%u)mask=%x(%u)\n", __func__, p->am_reg[i].addr,p->am_reg[i].addr,
(p->am_reg[i].val & p->am_reg[i].mask),(p->am_reg[i].val & p->am_reg[i].mask),
p->am_reg[i].val,p->am_reg[i].val,p->am_reg[i].mask,p->am_reg[i].mask);
#endif
break;
case REG_TYPE_AXI:
if (p->am_reg[i].mask == 0xffffffff)
WRITE_AXI_REG(p->am_reg[i].addr, p->am_reg[i].val);
else
WRITE_AXI_REG(p->am_reg[i].addr, (READ_AXI_REG(p->am_reg[i].addr) & (~(p->am_reg[i].mask))) | (p->am_reg[i].val & p->am_reg[i].mask));
#ifdef PQ_DEBUG_EN
pr_info("%s: axi: Reg0x%x(%u)=0x%x(%u)val=%x(%u)mask=%x(%u)\n", __func__, p->am_reg[i].addr,p->am_reg[i].addr,
(p->am_reg[i].val & p->am_reg[i].mask),(p->am_reg[i].val & p->am_reg[i].mask),
p->am_reg[i].val,p->am_reg[i].val,p->am_reg[i].mask,p->am_reg[i].mask);
#endif
break;
case REG_TYPE_AHB:
if (p->am_reg[i].mask == 0xffffffff)
WRITE_AHB_REG(p->am_reg[i].addr, p->am_reg[i].val);
else
WRITE_AHB_REG(p->am_reg[i].addr, (READ_AHB_REG(p->am_reg[i].addr) & (~(p->am_reg[i].mask))) | (p->am_reg[i].val & p->am_reg[i].mask));
#ifdef PQ_DEBUG_EN
pr_info("%s: ahb: Reg0x%x(%u)=0x%x(%u)val=%x(%u)mask=%x(%u)\n", __func__, p->am_reg[i].addr,p->am_reg[i].addr,
(p->am_reg[i].val & p->am_reg[i].mask),(p->am_reg[i].val & p->am_reg[i].mask),
p->am_reg[i].val,p->am_reg[i].val,p->am_reg[i].mask,p->am_reg[i].mask);
#endif
break;
case REG_TYPE_INDEX_VPPCHROMA:
WRITE_CBUS_REG(VPP_CHROMA_ADDR_PORT, p->am_reg[i].addr);
if (p->am_reg[i].mask == 0xffffffff)
{
WRITE_CBUS_REG(VPP_CHROMA_DATA_PORT, p->am_reg[i].val);
}
else
{
temp = READ_CBUS_REG(VPP_CHROMA_DATA_PORT);
WRITE_CBUS_REG(VPP_CHROMA_ADDR_PORT, p->am_reg[i].addr);
WRITE_CBUS_REG(VPP_CHROMA_DATA_PORT, (temp & (~(p->am_reg[i].mask))) | (p->am_reg[i].val & p->am_reg[i].mask));
}
#ifdef PQ_DEBUG_EN
pr_info("%s: chroma: Reg0x%x(%u)=0x%x(%u)val=%x(%u)mask=%x(%u)\n", __func__, p->am_reg[i].addr,p->am_reg[i].addr,
(p->am_reg[i].val & p->am_reg[i].mask),(p->am_reg[i].val & p->am_reg[i].mask),
p->am_reg[i].val,p->am_reg[i].val,p->am_reg[i].mask,p->am_reg[i].mask);
#endif
break;
case REG_TYPE_INDEX_GAMMA:
#ifdef PQ_DEBUG_EN
pr_info("%s: bus type: REG_TYPE_INDEX_GAMMA..............\n", __func__);
#endif
break;
case VALUE_TYPE_CONTRAST_BRIGHTNESS:
#ifdef PQ_DEBUG_EN
pr_info("%s: bus type: VALUE_TYPE_CONTRAST_BRIGHTNESS..............\n", __func__);
#endif
break;
case REG_TYPE_INDEX_VPP_COEF:
if (((p->am_reg[i].addr&0xf) == 0)||((p->am_reg[i].addr&0xf) == 0x8))
{
WRITE_CBUS_REG(VPP_CHROMA_ADDR_PORT, p->am_reg[i].addr);
WRITE_CBUS_REG(VPP_CHROMA_DATA_PORT, p->am_reg[i].val);
}
else
{
WRITE_CBUS_REG(VPP_CHROMA_DATA_PORT, p->am_reg[i].val);
}
#ifdef PQ_DEBUG_EN
pr_info("%s: coef: Reg0x%x(%u)=0x%x(%u)val=%x(%u)mask=%x(%u)\n", __func__, p->am_reg[i].addr,p->am_reg[i].addr,
(p->am_reg[i].val & p->am_reg[i].mask),(p->am_reg[i].val & p->am_reg[i].mask),
p->am_reg[i].val,p->am_reg[i].val,p->am_reg[i].mask,p->am_reg[i].mask);
#endif
break;
default:
#ifdef PQ_DEBUG_EN
pr_info("%s: bus type error!!!bustype = 0x%x................\n", __func__, p->am_reg[i].type);
#endif
break;
}
}
return;
}
static irqreturn_t vmpeg12_isr(int irq, void *dev_id)
{
u32 reg, info, seqinfo, offset, pts, pts_valid = 0;
vframe_t *vf;
ulong flags;
WRITE_MPEG_REG(ASSIST_MBOX1_CLR_REG, 1);
reg = READ_MPEG_REG(MREG_BUFFEROUT);
if (reg) {
info = READ_MPEG_REG(MREG_PIC_INFO);
offset = READ_MPEG_REG(MREG_FRAME_OFFSET);
info = info | PICINFO_TOP_FIRST;
if (((info & PICINFO_TYPE_MASK) == PICINFO_TYPE_I) &&
(pts_lookup_offset(PTS_TYPE_VIDEO, offset, &pts, 0) == 0)) {
pts_valid = 1;
}
/*if (frame_prog == 0)*/ {
frame_prog = info & PICINFO_PROG;
}
if ((dec_control & DEC_CONTROL_FLAG_FORCE_2500_720_576_INTERLACE) &&
(frame_width == 720) &&
(frame_height == 576) &&
(frame_dur == 3840)) {
frame_prog = 0;
}
else if ((dec_control & DEC_CONTROL_FLAG_FORCE_3000_704_480_INTERLACE) &&
(frame_width == 704) &&
(frame_height == 480) &&
(frame_dur == 3200)) {
frame_prog = 0;
}
else if ((dec_control & DEC_CONTROL_FLAG_FORCE_2500_704_576_INTERLACE) &&
(frame_width == 704) &&
(frame_height == 576) &&
(frame_dur == 3840)) {
frame_prog = 0;
}
else if ((dec_control & DEC_CONTROL_FLAG_FORCE_2500_544_576_INTERLACE) &&
(frame_width == 544) &&
(frame_height == 576) &&
(frame_dur == 3840)) {
frame_prog = 0;
}
else if ((dec_control & DEC_CONTROL_FLAG_FORCE_2500_480_576_INTERLACE) &&
(frame_width == 480) &&
(frame_height == 576) &&
(frame_dur == 3840)) {
frame_prog = 0;
}
if (frame_prog & PICINFO_PROG) {
u32 index = ((reg & 7) - 1) & 3;
seqinfo = READ_MPEG_REG(MREG_SEQ_INFO);
vf = vfq_pop(&newframe_q);
set_frame_info(vf);
vf->index = index;
vf->type = VIDTYPE_PROGRESSIVE | VIDTYPE_VIU_FIELD;
if ((seqinfo & SEQINFO_EXT_AVAILABLE) && (seqinfo & SEQINFO_PROG)) {
if (info & PICINFO_RPT_FIRST) {
if (info & PICINFO_TOP_FIRST) {
vf->duration = vf->duration * 3; // repeat three times
} else {
vf->duration = vf->duration * 2; // repeat two times
}
}
vf->duration_pulldown = 0; // no pull down
} else {
vf->duration_pulldown = (info & PICINFO_RPT_FIRST) ?
vf->duration >> 1 : 0;
}
vf->duration += vf->duration_pulldown;
vf->canvas0Addr = vf->canvas1Addr = index2canvas(index);
vf->pts = (pts_valid) ? pts : 0;
vfbuf_use[index]++;
if (error_skip(info, vf)) {
spin_lock_irqsave(&lock, flags);
vfq_push(&recycle_q, vf);
spin_unlock_irqrestore(&lock, flags);
} else {
vfq_push(&display_q, vf);
}
vf_notify_receiver(PROVIDER_NAME,VFRAME_EVENT_PROVIDER_VFRAME_READY,NULL);
} else {
static irqreturn_t tsdemux_isr(int irq, void *dev_id)
{
#ifndef ENABLE_DEMUX_DRIVER
u32 int_status = READ_MPEG_REG(STB_INT_STATUS);
#else
int id = (int)dev_id;
u32 int_status = id ? READ_MPEG_REG(STB_INT_STATUS_2) : READ_MPEG_REG(STB_INT_STATUS);
#endif
if (int_status & (1 << NEW_PDTS_READY)) {
#ifndef ENABLE_DEMUX_DRIVER
u32 pdts_status = READ_MPEG_REG(STB_PTS_DTS_STATUS);
if (pdts_status & (1 << VIDEO_PTS_READY))
pts_checkin_wrptr(PTS_TYPE_VIDEO,
READ_MPEG_REG(VIDEO_PDTS_WR_PTR),
READ_MPEG_REG(VIDEO_PTS_DEMUX));
if (pdts_status & (1 << AUDIO_PTS_READY))
pts_checkin_wrptr(PTS_TYPE_AUDIO,
READ_MPEG_REG(AUDIO_PDTS_WR_PTR),
READ_MPEG_REG(AUDIO_PTS_DEMUX));
WRITE_MPEG_REG(STB_PTS_DTS_STATUS, pdts_status);
#else
#define DMX_READ_REG(i,r)\
((i)?((i==1)?READ_MPEG_REG(r##_2):READ_MPEG_REG(r##_3)):READ_MPEG_REG(r))
u32 pdts_status = DMX_READ_REG(id, STB_PTS_DTS_STATUS);
if (pdts_status & (1 << VIDEO_PTS_READY))
pts_checkin_wrptr(PTS_TYPE_VIDEO,
DMX_READ_REG(id, VIDEO_PDTS_WR_PTR),
DMX_READ_REG(id, VIDEO_PTS_DEMUX));
if (pdts_status & (1 << AUDIO_PTS_READY))
pts_checkin_wrptr(PTS_TYPE_AUDIO,
DMX_READ_REG(id, AUDIO_PDTS_WR_PTR),
DMX_READ_REG(id, AUDIO_PTS_DEMUX));
if (id == 1) {
WRITE_MPEG_REG(STB_PTS_DTS_STATUS_2, pdts_status);
} else if (id == 2){
WRITE_MPEG_REG(STB_PTS_DTS_STATUS_3, pdts_status);
} else {
WRITE_MPEG_REG(STB_PTS_DTS_STATUS, pdts_status);
}
#endif
}
if (int_status & (1 << DIS_CONTINUITY_PACKET)) {
discontinued_counter++;
//printk("discontinued counter=%d\n",discontinued_counter);
}
if (int_status & (1 << SUB_PES_READY)) {
/* TODO: put data to somewhere */
//printk("subtitle pes ready\n");
wakeup_sub_poll();
}
#ifndef ENABLE_DEMUX_DRIVER
WRITE_MPEG_REG(STB_INT_STATUS, int_status);
#endif
return IRQ_HANDLED;
}
static ssize_t store_dbg(struct device * dev, struct device_attribute *attr, const char * buf, size_t count)
{
char tmpbuf[128];
int i=0;
unsigned int adr;
unsigned int value=0;
while((buf[i])&&(buf[i]!=',')&&(buf[i]!=' ')){
tmpbuf[i]=buf[i];
i++;
}
tmpbuf[i]=0;
if(strncmp(tmpbuf, "config_dvin", 11)==0){
#ifdef DEBUG_DVIN
config_dvin (hs_pol_inv,
vs_pol_inv,
de_pol_inv,
field_pol_inv,
ext_field_sel,
de_mode,
data_comp_map,
mode_422to444,
dvin_clk_inv,
vs_hs_tim_ctrl,
hs_lead_vs_odd_min,
hs_lead_vs_odd_max,
active_start_pix_fe,
active_start_pix_fo,
active_start_line_fe,
active_start_line_fo,
line_width,
field_height);
#endif
}
else if(strncmp(tmpbuf, "pause", 5)==0){
hdmirx_device.task_pause = 1;
printk("Pause %s\n", __func__);
}
else if(strncmp(tmpbuf, "start", 5)==0){
hdmirx_device.task_pause = 0;
printk("Start %s\n", __func__);
}
else if(strncmp(tmpbuf, "spdif", 5)==0){
setHDMIRX_SPDIFOutput();
}
else if(strncmp(tmpbuf, "i2s", 3)==0){
setHDMIRX_I2SOutput(0x1);
}
else if(strncmp(tmpbuf, "hpd", 3)==0){
if(tmpbuf[3]=='0'){
CLEAR_HPD;
}
else if(tmpbuf[3]=='1'){
SET_HPD;
}
}
else if(tmpbuf[0]=='w'){
adr=simple_strtoul(tmpbuf+2, NULL, 16);
value=simple_strtoul(buf+i+1, NULL, 16);
if(buf[1]=='h'){
HDMIRX_WriteI2C_Byte(adr, value);
}
else if(buf[1]=='c'){
WRITE_MPEG_REG(adr, value);
pr_info("write %x to CBUS reg[%x]\n",value,adr);
}
else if(buf[1]=='p'){
WRITE_APB_REG(adr, value);
pr_info("write %x to APB reg[%x]\n",value,adr);
}
}
else if(tmpbuf[0]=='r'){
adr=simple_strtoul(tmpbuf+2, NULL, 16);
if(buf[1]=='h'){
value = HDMIRX_ReadI2C_Byte(adr);
pr_info("HDMI reg[%x]=%x\n", adr, value);
}
else if(buf[1]=='c'){
value = READ_MPEG_REG(adr);
pr_info("CBUS reg[%x]=%x\n", adr, value);
}
else if(buf[1]=='p'){
value = READ_APB_REG(adr);
pr_info("APB reg[%x]=%x\n", adr, value);
}
}
return 16;
}
s32 tsdemux_init(u32 vid, u32 aid, u32 sid)
{
s32 r;
u32 parser_sub_start_ptr;
u32 parser_sub_end_ptr;
u32 parser_sub_rp;
#if MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON6
switch_mod_gate_by_type(MOD_DEMUX, 1);
#endif
parser_sub_start_ptr = READ_MPEG_REG(PARSER_SUB_START_PTR);
parser_sub_end_ptr = READ_MPEG_REG(PARSER_SUB_END_PTR);
parser_sub_rp = READ_MPEG_REG(PARSER_SUB_RP);
WRITE_MPEG_REG(RESET1_REGISTER, RESET_PARSER);
#ifdef ENABLE_DEMUX_DRIVER
tsdemux_reset();
#else
WRITE_MPEG_REG(RESET1_REGISTER, RESET_PARSER | RESET_DEMUXSTB);
WRITE_MPEG_REG(STB_TOP_CONFIG, 0);
WRITE_MPEG_REG(DEMUX_CONTROL, 0);
#endif
/* set PID filter */
printk("tsdemux video_pid = 0x%x, audio_pid = 0x%x, sub_pid = 0x%x\n",
vid, aid, sid);
#ifndef ENABLE_DEMUX_DRIVER
WRITE_MPEG_REG(FM_WR_DATA,
(((vid & 0x1fff) | (VIDEO_PACKET << 13)) << 16) |
((aid & 0x1fff) | (AUDIO_PACKET << 13)));
WRITE_MPEG_REG(FM_WR_ADDR, 0x8000);
while (READ_MPEG_REG(FM_WR_ADDR) & 0x8000) {
;
}
WRITE_MPEG_REG(FM_WR_DATA,
(((sid & 0x1fff) | (SUB_PACKET << 13)) << 16) | 0xffff);
WRITE_MPEG_REG(FM_WR_ADDR, 0x8001);
while (READ_MPEG_REG(FM_WR_ADDR) & 0x8000) {
;
}
WRITE_MPEG_REG(MAX_FM_COMP_ADDR, 1);
WRITE_MPEG_REG(STB_INT_MASK, 0);
WRITE_MPEG_REG(STB_INT_STATUS, 0xffff);
/* TS data path */
WRITE_MPEG_REG(FEC_INPUT_CONTROL, 0x7000);
WRITE_MPEG_REG(DEMUX_MEM_REQ_EN,
(1 << VIDEO_PACKET) |
(1 << AUDIO_PACKET) |
(1 << SUB_PACKET));
WRITE_MPEG_REG(DEMUX_ENDIAN,
(7 << OTHER_ENDIAN) |
(7 << BYPASS_ENDIAN) |
(0 << SECTION_ENDIAN));
WRITE_MPEG_REG(TS_HIU_CTL, 1 << USE_HI_BSF_INTERFACE);
WRITE_MPEG_REG(TS_FILE_CONFIG,
(demux_skipbyte << 16) |
(6 << DES_OUT_DLY) |
(3 << TRANSPORT_SCRAMBLING_CONTROL_ODD) |
(1 << TS_HIU_ENABLE) |
(4 << FEC_FILE_CLK_DIV));
/* enable TS demux */
WRITE_MPEG_REG(DEMUX_CONTROL, (1 << STB_DEMUX_ENABLE) | (1 << KEEP_DUPLICATE_PACKAGE));
#endif
if (fetchbuf == 0) {
printk("%s: no fetchbuf\n", __FUNCTION__);
return -ENOMEM;
}
/* hook stream buffer with PARSER */
WRITE_MPEG_REG(PARSER_VIDEO_START_PTR,
READ_VREG(VLD_MEM_VIFIFO_START_PTR));
WRITE_MPEG_REG(PARSER_VIDEO_END_PTR,
READ_VREG(VLD_MEM_VIFIFO_END_PTR));
CLEAR_MPEG_REG_MASK(PARSER_ES_CONTROL, ES_VID_MAN_RD_PTR);
WRITE_MPEG_REG(PARSER_AUDIO_START_PTR,
READ_MPEG_REG(AIU_MEM_AIFIFO_START_PTR));
WRITE_MPEG_REG(PARSER_AUDIO_END_PTR,
READ_MPEG_REG(AIU_MEM_AIFIFO_END_PTR));
CLEAR_MPEG_REG_MASK(PARSER_ES_CONTROL, ES_AUD_MAN_RD_PTR);
WRITE_MPEG_REG(PARSER_CONFIG,
(10 << PS_CFG_PFIFO_EMPTY_CNT_BIT) |
(1 << PS_CFG_MAX_ES_WR_CYCLE_BIT) |
(16 << PS_CFG_MAX_FETCH_CYCLE_BIT));
WRITE_VREG(VLD_MEM_VIFIFO_BUF_CNTL, MEM_BUFCTRL_INIT);
CLEAR_VREG_MASK(VLD_MEM_VIFIFO_BUF_CNTL, MEM_BUFCTRL_INIT);
WRITE_MPEG_REG(AIU_MEM_AIFIFO_BUF_CNTL, MEM_BUFCTRL_INIT);
CLEAR_MPEG_REG_MASK(AIU_MEM_AIFIFO_BUF_CNTL, MEM_BUFCTRL_INIT);
WRITE_MPEG_REG(PARSER_SUB_START_PTR, parser_sub_start_ptr);
WRITE_MPEG_REG(PARSER_SUB_END_PTR, parser_sub_end_ptr);
WRITE_MPEG_REG(PARSER_SUB_RP, parser_sub_rp);
SET_MPEG_REG_MASK(PARSER_ES_CONTROL, (7 << ES_SUB_WR_ENDIAN_BIT) | ES_SUB_MAN_RD_PTR);
if ((r = pts_start(PTS_TYPE_VIDEO)) < 0) {
printk("Video pts start failed.(%d)\n", r);
goto err1;
}
if ((r = pts_start(PTS_TYPE_AUDIO)) < 0) {
printk("Audio pts start failed.(%d)\n", r);
goto err2;
}
r = request_irq(INT_PARSER, parser_isr,
IRQF_SHARED, "tsdemux-fetch",
(void *)tsdemux_fetch_id);
if (r) {
goto err3;
}
WRITE_MPEG_REG(PARSER_INT_STATUS, 0xffff);
WRITE_MPEG_REG(PARSER_INT_ENABLE, PARSER_INTSTAT_FETCH_CMD << PARSER_INT_HOST_EN_BIT);
WRITE_MPEG_REG(PARSER_VIDEO_HOLE, 0x400);
WRITE_MPEG_REG(PARSER_AUDIO_HOLE, 0x400);
discontinued_counter = 0;
#ifndef ENABLE_DEMUX_DRIVER
r = request_irq(INT_DEMUX, tsdemux_isr,
IRQF_SHARED, "tsdemux-irq",
(void *)tsdemux_irq_id);
WRITE_MPEG_REG(STB_INT_MASK,
(1 << SUB_PES_READY)
| (1 << NEW_PDTS_READY)
| (1 << DIS_CONTINUITY_PACKET));
if (r) {
goto err4;
}
#else
tsdemux_config();
tsdemux_request_irq(tsdemux_isr, (void *)tsdemux_irq_id);
if (vid < 0x1FFF) {
tsdemux_set_vid(vid);
}
if (aid < 0x1FFF) {
tsdemux_set_aid(aid);
}
if (sid < 0x1FFF) {
tsdemux_set_sid(sid);
}
#endif
return 0;
#ifndef ENABLE_DEMUX_DRIVER
err4:
free_irq(INT_PARSER, (void *)tsdemux_fetch_id);
#endif
err3:
pts_stop(PTS_TYPE_AUDIO);
err2:
pts_stop(PTS_TYPE_VIDEO);
err1:
printk("TS Demux init failed.\n");
return -ENOENT;
}
static void enable_vsync_interrupt(void)
{
printk("enable_vsync_interrupt\n");
CLEAR_CBUS_REG_MASK(HHI_MPEG_CLK_CNTL, 1<<11);
if (READ_MPEG_REG(ENCP_VIDEO_EN) & 1) {
WRITE_MPEG_REG(VENC_INTCTRL, 0x200);
#ifdef CONFIG_ARCH_MESON1
while ((READ_MPEG_REG(VENC_INTFLAG) & 0x200) == 0) {
u32 line1, line2;
line1 = line2 = READ_MPEG_REG(VENC_ENCP_LINE);
while (line1 >= line2) {
line2 = line1;
line1 = READ_MPEG_REG(VENC_ENCP_LINE);
}
READ_MPEG_REG(VENC_INTFLAG);
READ_MPEG_REG(VENC_INTFLAG);
READ_MPEG_REG(VENC_INTFLAG);
READ_MPEG_REG(VENC_INTFLAG);
if (READ_MPEG_REG(VENC_INTFLAG) & 0x200) {
break;
}
WRITE_MPEG_REG(ENCP_VIDEO_EN, 0);
READ_MPEG_REG(VENC_INTFLAG);
READ_MPEG_REG(VENC_INTFLAG);
READ_MPEG_REG(VENC_INTFLAG);
READ_MPEG_REG(VENC_INTFLAG);
READ_MPEG_REG(VENC_INTFLAG);
WRITE_MPEG_REG(ENCP_VIDEO_EN, 1);
READ_MPEG_REG(VENC_INTFLAG);
READ_MPEG_REG(VENC_INTFLAG);
READ_MPEG_REG(VENC_INTFLAG);
READ_MPEG_REG(VENC_INTFLAG);
READ_MPEG_REG(VENC_INTFLAG);
}
#else
while ((READ_MPEG_REG(VENC_INTFLAG) & 0x200) == 0) {
mdelay(50);
WRITE_MPEG_REG(ENCP_VIDEO_EN, 0);
READ_MPEG_REG(VENC_INTFLAG);
WRITE_MPEG_REG(ENCP_VIDEO_EN, 1);
printk("recycle TV encoder\n");
}
#endif
}
else{
WRITE_MPEG_REG(VENC_INTCTRL, 0x2);
}
printk("Enable vsync done\n");
}
s32 stbuf_init(struct stream_buf_s *buf)
{
s32 r;
u32 dummy;
u32 phy_addr;
if (buf->flag & BUF_FLAG_IOMEM) {
phy_addr = buf->buf_start;
} else {
r = _stbuf_alloc(buf);
if (r < 0) {
return r;
}
phy_addr = virt_to_phys((void *)buf->buf_start);
}
init_waitqueue_head(&buf->wq);
#if MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON8
if (HAS_HEVC_VDEC && buf->type == BUF_TYPE_HEVC) {
CLEAR_VREG_MASK(HEVC_STREAM_CONTROL, 1);
WRITE_VREG(HEVC_STREAM_START_ADDR, phy_addr);
WRITE_VREG(HEVC_STREAM_END_ADDR, phy_addr + buf->buf_size);
WRITE_VREG(HEVC_STREAM_RD_PTR, phy_addr);
WRITE_VREG(HEVC_STREAM_WR_PTR, phy_addr);
return 0;
}
#endif
if (buf->type == BUF_TYPE_VIDEO) {
_WRITE_ST_REG(CONTROL, 0);
/* reset VLD before setting all pointers */
WRITE_VREG(VLD_MEM_VIFIFO_WRAP_COUNT,0);
#if MESON_CPU_TYPE >= MESON_CPU_TYPE_MESON6
WRITE_VREG(DOS_SW_RESET0, (1<<4));
WRITE_VREG(DOS_SW_RESET0, 0);
#else
WRITE_MPEG_REG(RESET0_REGISTER, RESET_VLD);
#endif
dummy = READ_MPEG_REG(RESET0_REGISTER);
WRITE_VREG(POWER_CTL_VLD, 1 << 4);
} else if (buf->type == BUF_TYPE_AUDIO) {
_WRITE_ST_REG(CONTROL, 0);
WRITE_MPEG_REG(AIU_AIFIFO_GBIT, 0x80);
}
if (buf->type == BUF_TYPE_SUBTITLE) {
WRITE_MPEG_REG(PARSER_SUB_RP, phy_addr);
WRITE_MPEG_REG(PARSER_SUB_START_PTR, phy_addr);
WRITE_MPEG_REG(PARSER_SUB_END_PTR, phy_addr + buf->buf_size - 8);
return 0;
}
_WRITE_ST_REG(START_PTR, phy_addr);
_WRITE_ST_REG(CURR_PTR, phy_addr);
_WRITE_ST_REG(END_PTR, phy_addr + buf->buf_size - 8);
_SET_ST_REG_MASK(CONTROL, MEM_BUFCTRL_INIT);
_CLR_ST_REG_MASK(CONTROL, MEM_BUFCTRL_INIT);
_WRITE_ST_REG(BUF_CTRL, MEM_BUFCTRL_MANUAL);
_WRITE_ST_REG(WP, phy_addr);
_SET_ST_REG_MASK(BUF_CTRL, MEM_BUFCTRL_INIT);
_CLR_ST_REG_MASK(BUF_CTRL, MEM_BUFCTRL_INIT);
_SET_ST_REG_MASK(CONTROL, (0x11 << 16) | MEM_FILL_ON_LEVEL | MEM_CTRL_FILL_EN | MEM_CTRL_EMPTY_EN);
return 0;
}
void timestamp_vpts_inc(s32 val)
{
WRITE_MPEG_REG(VIDEO_PTS, READ_MPEG_REG(VIDEO_PTS) + val);
}
static inline void _enable_vsync_interrupt(void)
{
if (READ_MPEG_REG(ENCP_VIDEO_EN) & 1) {
WRITE_MPEG_REG(VENC_INTCTRL, 0x200);
while ((READ_MPEG_REG(VENC_INTFLAG) & 0x200) == 0) {
u32 line1, line2;
line1 = line2 = READ_MPEG_REG(VENC_ENCP_LINE);
while (line1 >= line2) {
line2 = line1;
line1 = READ_MPEG_REG(VENC_ENCP_LINE);
}
READ_MPEG_REG(VENC_INTFLAG);
READ_MPEG_REG(VENC_INTFLAG);
READ_MPEG_REG(VENC_INTFLAG);
READ_MPEG_REG(VENC_INTFLAG);
if (READ_MPEG_REG(VENC_INTFLAG) & 0x200) {
break;
}
WRITE_MPEG_REG(ENCP_VIDEO_EN, 0);
READ_MPEG_REG(VENC_INTFLAG);
READ_MPEG_REG(VENC_INTFLAG);
READ_MPEG_REG(VENC_INTFLAG);
READ_MPEG_REG(VENC_INTFLAG);
READ_MPEG_REG(VENC_INTFLAG);
WRITE_MPEG_REG(ENCP_VIDEO_EN, 1);
READ_MPEG_REG(VENC_INTFLAG);
READ_MPEG_REG(VENC_INTFLAG);
READ_MPEG_REG(VENC_INTFLAG);
READ_MPEG_REG(VENC_INTFLAG);
READ_MPEG_REG(VENC_INTFLAG);
}
}
else{
WRITE_MPEG_REG(VENC_INTCTRL, 0x2);
}
}
u32 stbuf_sub_wp_get(void)
{
return READ_MPEG_REG(PARSER_SUB_WP);
}
int read_buffer(unsigned char *buffer,int size)
{
int bytes;
int len;
unsigned char *p=buffer;
int tmp;
int space;
int i;
int wait_times=0,fifo_ready_wait = 0;
int iii;
iii = READ_MPEG_REG(AIU_MEM_AIFIFO_LEVEL)-EXTRA_DATA_SIZE;
// adec_print("read_buffer start iii = %d!!\n", iii);
static int cc = 0;
len=0;
#if 0
while( size >= iii){
cc++ ;
amthreadpool_thread_usleep(1000);
iii = READ_MPEG_REG(AIU_MEM_AIFIFO_LEVEL)-EXTRA_DATA_SIZE;
if (cc%2000 == 0)
adec_print("read_buffer start in while iii = %d!!exit_decode_thread:%d \n", iii,exit_decode_thread);
if(exit_decode_thread)
goto out;
}
#endif
if(( size >= iii))
return 0;
// adec_print("read_buffer start while iii= %d!!\n", iii);
for(len=0;len<size;)
{
space=(size-len);
bytes=READ_MPEG_REG(AIU_MEM_AIFIFO_BYTES_AVAIL);
//adec_print("read_buffer start AIU_MEM_AIFIFO_BYTES_AVAIL bytes= %d!!\n", bytes);
wait_times=0;
while(bytes==0)
{
waiting_bits((space>128)?128*8:(space*8)); /*wait 32 bytes,if the space is less than 32 bytes,wait the space bits*/
bytes=READ_MPEG_REG(AIU_MEM_AIFIFO_BYTES_AVAIL);
adec_print("read_buffer while AIU_MEM_AIFIFO_BYTES_AVAIL = %d!!\n", bytes);
wait_times++;
if(wait_times>10 || amthreadpool_on_requare_exit(0)) {
adec_print("goto out!!\n");
goto out;
}
}
bytes=min(space,bytes);
//adec_print("read_buffer while bytes = %d!!\n", bytes);
for(i=0;i<bytes;i++)
{
while(!AIFIFO_READY){
fifo_ready_wait++;
amthreadpool_thread_usleep(1000);
if(fifo_ready_wait > 100 || amthreadpool_on_requare_exit(0)){
adec_print("FATAL err,AIFIFO is not ready,check!!\n");
return 0;
}
}
WRITE_MPEG_REG(AIU_AIFIFO_GBIT,8);
tmp=READ_MPEG_REG(AIU_AIFIFO_GBIT);
//adec_print("read_buffer while tmp = %d!!\n", tmp);
*p++=tmp&0xff;
fifo_ready_wait = 0;
}
len+=bytes;
}
out:
//stream_in_offset+=len;
return len;
}
static void init_scaler(void)
{
/* 4 point triangle */
const unsigned filt_coef[] = {
0x20402000, 0x20402000, 0x1f3f2101, 0x1f3f2101,
0x1e3e2202, 0x1e3e2202, 0x1d3d2303, 0x1d3d2303,
0x1c3c2404, 0x1c3c2404, 0x1b3b2505, 0x1b3b2505,
0x1a3a2606, 0x1a3a2606, 0x19392707, 0x19392707,
0x18382808, 0x18382808, 0x17372909, 0x17372909,
0x16362a0a, 0x16362a0a, 0x15352b0b, 0x15352b0b,
0x14342c0c, 0x14342c0c, 0x13332d0d, 0x13332d0d,
0x12322e0e, 0x12322e0e, 0x11312f0f, 0x11312f0f,
0x10303010
};
int i;
/* pscale enable, PSCALE cbus bmem enable */
WRITE_MPEG_REG(PSCALE_CTRL, 0xc000);
/* write filter coefs */
WRITE_MPEG_REG(PSCALE_BMEM_ADDR, 0);
for (i = 0; i < 33; i++) {
WRITE_MPEG_REG(PSCALE_BMEM_DAT, 0);
WRITE_MPEG_REG(PSCALE_BMEM_DAT, filt_coef[i]);
}
/* Y horizontal initial info */
WRITE_MPEG_REG(PSCALE_BMEM_ADDR, 37*2);
/* [35]: buf repeat pix0,
* [34:29] => buf receive num,
* [28:16] => buf blk x,
* [15:0] => buf phase
*/
WRITE_MPEG_REG(PSCALE_BMEM_DAT, 0x0008);
WRITE_MPEG_REG(PSCALE_BMEM_DAT, 0x60000000);
/* C horizontal initial info */
WRITE_MPEG_REG(PSCALE_BMEM_ADDR, 41*2);
WRITE_MPEG_REG(PSCALE_BMEM_DAT, 0x0008);
WRITE_MPEG_REG(PSCALE_BMEM_DAT, 0x60000000);
/* Y vertical initial info */
WRITE_MPEG_REG(PSCALE_BMEM_ADDR, 39*2);
WRITE_MPEG_REG(PSCALE_BMEM_DAT, 0x0008);
WRITE_MPEG_REG(PSCALE_BMEM_DAT, 0x60000000);
/* C vertical initial info */
WRITE_MPEG_REG(PSCALE_BMEM_ADDR, 43*2);
WRITE_MPEG_REG(PSCALE_BMEM_DAT, 0x0008);
WRITE_MPEG_REG(PSCALE_BMEM_DAT, 0x60000000);
/* Y horizontal phase step */
WRITE_MPEG_REG(PSCALE_BMEM_ADDR, 36*2 + 1);
/* [19:0] => Y horizontal phase step */
WRITE_MPEG_REG(PSCALE_BMEM_DAT, 0x10000);
/* C horizontal phase step */
WRITE_MPEG_REG(PSCALE_BMEM_ADDR, 40*2 + 1);
/* [19:0] => C horizontal phase step */
WRITE_MPEG_REG(PSCALE_BMEM_DAT, 0x10000);
/* Y vertical phase step */
WRITE_MPEG_REG(PSCALE_BMEM_ADDR, 38*2+1);
/* [19:0] => Y vertical phase step */
WRITE_MPEG_REG(PSCALE_BMEM_DAT, 0x10000);
/* C vertical phase step */
WRITE_MPEG_REG(PSCALE_BMEM_ADDR, 42*2+1);
/* [19:0] => C horizontal phase step */
WRITE_MPEG_REG(PSCALE_BMEM_DAT, 0x10000);
/* reset pscaler */
WRITE_MPEG_REG(RESET2_REGISTER, RESET_PSCALE);
READ_MPEG_REG(RESET2_REGISTER);
READ_MPEG_REG(RESET2_REGISTER);
READ_MPEG_REG(RESET2_REGISTER);
WRITE_MPEG_REG(PSCALE_RST, 0x7);
WRITE_MPEG_REG(PSCALE_RST, 0x0);
}
static void enable_vsync_interrupt(void)
{
if(used_audio_pll)
{
/* M1 chip test only, use audio PLL as video clock source */
SET_CBUS_REG_MASK(HHI_MPEG_CLK_CNTL, 1<<11);
}
else
{
/* M1 REVB , Video PLL bug fixed */
CLEAR_CBUS_REG_MASK(HHI_MPEG_CLK_CNTL, 1<<11);
}
if (READ_MPEG_REG(ENCP_VIDEO_EN) & 1) {
WRITE_MPEG_REG(VENC_INTCTRL, 0x200);
while ((READ_MPEG_REG(VENC_INTFLAG) & 0x200) == 0) {
u32 line1, line2;
line1 = line2 = READ_MPEG_REG(VENC_ENCP_LINE);
while (line1 >= line2) {
line2 = line1;
line1 = READ_MPEG_REG(VENC_ENCP_LINE);
}
READ_MPEG_REG(VENC_INTFLAG);
READ_MPEG_REG(VENC_INTFLAG);
READ_MPEG_REG(VENC_INTFLAG);
READ_MPEG_REG(VENC_INTFLAG);
if (READ_MPEG_REG(VENC_INTFLAG) & 0x200) {
break;
}
WRITE_MPEG_REG(ENCP_VIDEO_EN, 0);
READ_MPEG_REG(VENC_INTFLAG);
READ_MPEG_REG(VENC_INTFLAG);
READ_MPEG_REG(VENC_INTFLAG);
READ_MPEG_REG(VENC_INTFLAG);
READ_MPEG_REG(VENC_INTFLAG);
WRITE_MPEG_REG(ENCP_VIDEO_EN, 1);
READ_MPEG_REG(VENC_INTFLAG);
READ_MPEG_REG(VENC_INTFLAG);
READ_MPEG_REG(VENC_INTFLAG);
READ_MPEG_REG(VENC_INTFLAG);
READ_MPEG_REG(VENC_INTFLAG);
}
}
else{
WRITE_MPEG_REG(VENC_INTCTRL, 0x2);
}
}
static inline u32 buf_wp(u32 type)
{
return (type == BUF_TYPE_VIDEO) ? READ_VREG(VLD_MEM_VIFIFO_WP) :
(type == BUF_TYPE_AUDIO) ? READ_MPEG_REG(AIU_MEM_AIFIFO_MAN_WP) :
READ_MPEG_REG(PARSER_SUB_START_PTR);
}
static void amvdec_pg_enable(bool enable)
{
ulong timeout;
if (enable) {
CLK_GATE_ON(MDEC_CLK_PIC_DC);
CLK_GATE_ON(MDEC_CLK_DBLK);
CLK_GATE_ON(MC_CLK);
CLK_GATE_ON(IQIDCT_CLK);
//CLK_GATE_ON(VLD_CLK);
CLK_GATE_ON(AMRISC);
} else {
CLK_GATE_OFF(AMRISC);
timeout = jiffies + HZ / 10;
while (READ_MPEG_REG(MDEC_PIC_DC_STATUS) != 0) {
if (time_after(jiffies, timeout)) {
WRITE_MPEG_REG_BITS(MDEC_PIC_DC_CTRL, 1, 0, 1);
WRITE_MPEG_REG_BITS(MDEC_PIC_DC_CTRL, 0, 0, 1);
READ_MPEG_REG(MDEC_PIC_DC_STATUS);
READ_MPEG_REG(MDEC_PIC_DC_STATUS);
READ_MPEG_REG(MDEC_PIC_DC_STATUS);
break;
}
}
CLK_GATE_OFF(MDEC_CLK_PIC_DC);
timeout = jiffies + HZ / 10;
while (READ_MPEG_REG(DBLK_STATUS) & 1) {
if (time_after(jiffies, timeout)) {
WRITE_MPEG_REG(DBLK_CTRL, 3);
WRITE_MPEG_REG(DBLK_CTRL, 0);
READ_MPEG_REG(DBLK_STATUS);
READ_MPEG_REG(DBLK_STATUS);
READ_MPEG_REG(DBLK_STATUS);
break;
}
}
CLK_GATE_OFF(MDEC_CLK_DBLK);
timeout = jiffies + HZ / 10;
while (READ_MPEG_REG(MC_STATUS0) & 1) {
if (time_after(jiffies, timeout)) {
SET_MPEG_REG_MASK(MC_CTRL1, 0x9);
CLEAR_MPEG_REG_MASK(MC_CTRL1, 0x9);
READ_MPEG_REG(MC_STATUS0);
READ_MPEG_REG(MC_STATUS0);
READ_MPEG_REG(MC_STATUS0);
break;
}
}
CLK_GATE_OFF(MC_CLK);
timeout = jiffies + HZ / 10;
while (READ_MPEG_REG(DCAC_DMA_CTRL) & 0x8000) {
if (time_after(jiffies, timeout)) {
break;
}
}
WRITE_MPEG_REG(RESET0_REGISTER, 4);
READ_MPEG_REG(RESET0_REGISTER);
READ_MPEG_REG(RESET0_REGISTER);
READ_MPEG_REG(RESET0_REGISTER);
CLK_GATE_OFF(IQIDCT_CLK);
//CLK_GATE_OFF(VLD_CLK);
}
}
s32 rmparser_init(void)
{
s32 r;
parse_halt = 0;
if (fetchbuf == 0) {
printk("%s: no fetchbuf\n", __FUNCTION__);
return -ENOMEM;
}
WRITE_MPEG_REG(RESET1_REGISTER, RESET_PARSER);
/* TS data path */
/* Ignore FEC control for WetekPlay */
#ifndef CONFIG_WETEK
#ifndef CONFIG_AM_DVB
WRITE_MPEG_REG(FEC_INPUT_CONTROL, 0);
#else
tsdemux_set_reset_flag();
#endif
#endif
CLEAR_MPEG_REG_MASK(TS_HIU_CTL, 1 << USE_HI_BSF_INTERFACE);
CLEAR_MPEG_REG_MASK(TS_HIU_CTL_2, 1 << USE_HI_BSF_INTERFACE);
CLEAR_MPEG_REG_MASK(TS_HIU_CTL_3, 1 << USE_HI_BSF_INTERFACE);
CLEAR_MPEG_REG_MASK(TS_FILE_CONFIG, (1 << TS_HIU_ENABLE));
/* hook stream buffer with PARSER */
WRITE_MPEG_REG(PARSER_VIDEO_START_PTR,
READ_VREG(VLD_MEM_VIFIFO_START_PTR));
WRITE_MPEG_REG(PARSER_VIDEO_END_PTR,
READ_VREG(VLD_MEM_VIFIFO_END_PTR));
CLEAR_MPEG_REG_MASK(PARSER_ES_CONTROL, ES_VID_MAN_RD_PTR);
WRITE_MPEG_REG(PARSER_AUDIO_START_PTR,
READ_MPEG_REG(AIU_MEM_AIFIFO_START_PTR));
WRITE_MPEG_REG(PARSER_AUDIO_END_PTR,
READ_MPEG_REG(AIU_MEM_AIFIFO_END_PTR));
CLEAR_MPEG_REG_MASK(PARSER_ES_CONTROL, ES_AUD_MAN_RD_PTR);
WRITE_VREG(VLD_MEM_VIFIFO_BUF_CNTL, MEM_BUFCTRL_INIT);
CLEAR_VREG_MASK(VLD_MEM_VIFIFO_BUF_CNTL, MEM_BUFCTRL_INIT);
WRITE_MPEG_REG(AIU_MEM_AIFIFO_BUF_CNTL, MEM_BUFCTRL_INIT);
CLEAR_MPEG_REG_MASK(AIU_MEM_AIFIFO_BUF_CNTL, MEM_BUFCTRL_INIT);
WRITE_MPEG_REG(PFIFO_RD_PTR, 0);
WRITE_MPEG_REG(PFIFO_WR_PTR, 0);
WRITE_MPEG_REG(PARSER_SEARCH_MASK, 0);
WRITE_MPEG_REG(PARSER_CONTROL, (ES_SEARCH | ES_PARSER_START));
#ifdef MANAGE_PTS
if (pts_start(PTS_TYPE_VIDEO) < 0) {
goto Err_1;
}
if (pts_start(PTS_TYPE_AUDIO) < 0) {
goto Err_2;
}
#endif
/* enable interrupt */
r = request_irq(INT_PARSER, rm_parser_isr,
IRQF_SHARED, "rmparser", (void *)rmparser_id);
if (r) {
printk("RM parser irq register failed.\n");
goto Err_3;
}
WRITE_MPEG_REG(PARSER_INT_STATUS, 0xffff);
WRITE_MPEG_REG(PARSER_INT_ENABLE,
((PARSER_INT_ALL & (~PARSER_INTSTAT_FETCH_CMD)) << PARSER_INT_AMRISC_EN_BIT)
| (PARSER_INTSTAT_FETCH_CMD << PARSER_INT_HOST_EN_BIT));
return 0;
Err_3:
pts_stop(PTS_TYPE_AUDIO);
Err_2:
pts_stop(PTS_TYPE_VIDEO);
Err_1:
return -ENOENT;
}
void pcm_in_enable(int flag)
{
/* reset fifo */
RESET_FIFO:
WRITE_MPEG_REG_BITS(AUDIN_FIFO1_CTRL, 1, 1, 1);
WRITE_MPEG_REG(AUDIN_FIFO1_PTR, 0);
if (READ_MPEG_REG(AUDIN_FIFO1_PTR) != READ_MPEG_REG(AUDIN_FIFO1_START))
goto RESET_FIFO;
WRITE_MPEG_REG_BITS(AUDIN_FIFO1_CTRL, 0, 1, 1);
/* reset pcmin */
WRITE_MPEG_REG_BITS(PCMIN_CTRL0, 1, 30, 1);
WRITE_MPEG_REG_BITS(PCMIN_CTRL0, 0, 30, 1);
/* disable fifo */
WRITE_MPEG_REG_BITS(AUDIN_FIFO1_CTRL, 0, 0, 1);
/* disable pcmin */
WRITE_MPEG_REG_BITS(PCMIN_CTRL0, 0, 31, 1);
if (flag) {
/* set buffer start ptr end */
WRITE_MPEG_REG(AUDIN_FIFO1_START, pcmin_buffer_addr);
WRITE_MPEG_REG(AUDIN_FIFO1_PTR, pcmin_buffer_addr);
WRITE_MPEG_REG(AUDIN_FIFO1_END, pcmin_buffer_addr + pcmin_buffer_size - 8);
/* fifo control */
WRITE_MPEG_REG(AUDIN_FIFO1_CTRL, (1 << 15) | // urgent request
(1 << 11) | // channel
(6 << 8) | // endian
//(0 << 8) | // endian
(2 << 3) | // PCMIN input selection
(1 << 2) | // load address
(0 << 1) | // reset fifo
(1 << 0) // fifo enable
);
/* fifo control1 */
WRITE_MPEG_REG(AUDIN_FIFO1_CTRL1, (0 << 4) | // data destination DDR
(1 << 2) | // 16bits
(0 << 0) // data position
);
/* pcmin control1 */
WRITE_MPEG_REG(PCMIN_CTRL1, (0 << 29) | // external chip
(0 << 28) | // external chip
(1 << 27) | // using negedge of PCM clock to latch the input data
(15 << 21) | // slot bit msb 16 clocks per slot
(15 << 16) | // data msb 16bits data
(1 << 0) // slot valid
);
/* pcmin control0 */
WRITE_MPEG_REG(PCMIN_CTRL0, (1 << 31) | // pcmin enable
(1 << 29) | // sync on clock posedge
(0 << 16) | // FS SKEW
(0 << 4) | // waithing 1 system clock cycles then sample the PCMIN singals
(0 << 3) | // use clock counter to do the sample
(0 << 2) | // fs not inverted. H = left, L = right
(1 << 1) | // msb first
(1 << 0) // left justified
);
}
pcm_debug("PCMIN %s\n", flag ? "enable" : "disable");
pcm_in_register_show();
}