// Initialize UART0
// Baud rate is 115200 bits/sec
void UART_Init(void){
SYSCTL_RCGCUART_R |= 0x01; // activate UART0
SYSCTL_RCGCGPIO_R |= 0x01; // activate port A
RxFifo_Init(); // initialize empty FIFOs
TxFifo_Init();
UART0_CTL_R &= ~UART_CTL_UARTEN; // disable UART
UART0_IBRD_R = 43; // IBRD = int(80,000,000 / (16 * 115,200)) = int(43.403)
UART0_FBRD_R = 26; // FBRD = round(0.4028 * 64 ) = 26
// 8 bit word length (no parity bits, one stop bit, FIFOs)
UART0_LCRH_R = (UART_LCRH_WLEN_8|UART_LCRH_FEN);
UART0_IFLS_R &= ~0x3F; // clear TX and RX interrupt FIFO level fields
// configure interrupt for TX FIFO <= 1/8 full
// configure interrupt for RX FIFO >= 1/8 full
UART0_IFLS_R += (UART_IFLS_TX1_8|UART_IFLS_RX1_8);
// enable TX and RX FIFO interrupts and RX time-out interrupt
UART0_IM_R |= (UART_IM_RXIM|UART_IM_TXIM|UART_IM_RTIM);
UART0_CTL_R |= 0x301; // enable UART
GPIO_PORTA_AFSEL_R |= 0x03; // enable alt funct on PA1-0
GPIO_PORTA_DEN_R |= 0x03; // enable digital I/O on PA1-0
// configure PA1-0 as UART
GPIO_PORTA_PCTL_R = (GPIO_PORTA_PCTL_R&0xFFFFFF00)+0x00000011;
GPIO_PORTA_AMSEL_R = 0; // disable analog functionality on PA
// UART0=priority 2
NVIC_PRI1_R = (NVIC_PRI1_R&0xFFFF00FF)|0x00004000; // bits 13-15
NVIC_EN0_R = NVIC_EN0_INT5; // enable interrupt 5 in NVIC
}
/*
===================================================================================================
USB_UART :: USB_UART_Init
- initializes the UART to use PA0,1 at 115200 baud
===================================================================================================
*/
void USB_UART_Init(void){
TxFifo_Init();
RxFifo_Init();
// enable UART0
SYSCTL_RCGCUART_R |= SYSCTL_RCGCUART_R0; // activate UART0 clock gating
while ((SYSCTL_PRUART_R & SYSCTL_PRUART_R0) == 0) {}; // wait for UART0 to activate
// enable PORTA
SYSCTL_RCGCGPIO_R |= SYSCTL_RCGCGPIO_R0; // activate PORTA clock gating
while ((SYSCTL_PRGPIO_R & SYSCTL_PRGPIO_R0) == 0) {}; // wait for PORTA to activate
// configure PORTA pins for use with UART0
GPIO_PORTA_AFSEL_R |= 0x03;
GPIO_PORTA_DEN_R |= 0x03;
GPIO_PORTA_PCTL_R |= 0x11;
GPIO_PORTA_DR2R_R |= 0x03;
// configure UART0 for 115200bps operation
// IBRD = 80e6/(16*115200) = 43.4027 = 43
// FBRD = integer(.402777*64 + 0.5) = 26
UART0_CTL_R &= ~0x01; // clear UART0 enable bit during config
UART0_IBRD_R = 43; // set integer portion of BRD
UART0_FBRD_R = 26; // set fraction portion of BRD
UART0_LCRH_R = (UART_LCRH_WLEN_8|UART_LCRH_FEN); // 8 bit word length, 1 stop, no parity, FIFOs enabled
UART0_CC_R = 0x00; // use system clock
UART0_IFLS_R &= ~0x3F; // clear TX and RX interrupt FIFO level fields
UART0_IFLS_R |= UART_IFLS_RX1_8; // RX FIFO interrupt threshold >= 1/8th full
UART0_IFLS_R |= UART_IFLS_TX1_8; // TX FIFO interrupt threshold <= 4/8th full
UART0_IM_R |= (UART_IM_RXIM | UART_IM_RTIM); // enable interupt on RX and RX transmission end
UART0_IM_R |= UART_IM_TXIM; // enable interrupt on TX
UART0_CTL_R |= UART_CTL_UARTEN; // set UART0 enable bit
}
int main2(void){ int i;
// *************** Test #1: test transmit (index) FIFO **************
TxFifo_Init();
result = TxFifo_Get(&letter); // letter = ??, result = 0
result = TxFifo_Put('A'); // result = 1
result = TxFifo_Put('B'); // result = 1
result = TxFifo_Put('C'); // result = 1
result = TxFifo_Get(&letter); // letter = 0x41, result = 1
result = TxFifo_Get(&letter); // letter = 0x42, result = 1
result = TxFifo_Put('D'); // result = 1
result = TxFifo_Size(); // result = 2
result = TxFifo_Get(&letter); // letter = 0x43, result = 1
result = TxFifo_Get(&letter); // letter = 0x44, result = 1
result = TxFifo_Size(); // result = 0
result = TxFifo_Get(&letter); // letter = ??, result = 0
for(i='A'; i<'A'+TXFIFOSIZE; i=i+1){
result = TxFifo_Put(i); // result = 1
}
result = TxFifo_Size(); // result = 16
result = TxFifo_Get(&letter); // letter = 0x41, result = 1
result = TxFifo_Size(); // result = 15
result = TxFifo_Get(&letter); // letter = 0x42, result = 1
result = TxFifo_Size(); // result = 14
result = TxFifo_Put(' '); // result = 1
result = TxFifo_Size(); // result = 15
// *************** Test #2: test receive (pointer) FIFO *************
RxFifo_Init();
result = RxFifo_Get(&letter); // letter = ??, result = 0
result = RxFifo_Put('A'); // result = 1
result = RxFifo_Put('B'); // result = 1
result = RxFifo_Put('C'); // result = 1
result = RxFifo_Get(&letter); // letter = 0x41, result = 1
result = RxFifo_Get(&letter); // letter = 0x42, result = 1
result = RxFifo_Put('D'); // result = 1
result = RxFifo_Size(); // result = 2
result = RxFifo_Get(&letter); // letter = 0x43, result = 1
result = RxFifo_Get(&letter); // letter = 0x44, result = 1
result = RxFifo_Size(); // result = 0
result = RxFifo_Get(&letter); // letter = ??, result = 0
for(i='A'; i<'A'+RXFIFOSIZE-1; i=i+1){
result = RxFifo_Put(i); // result = 1
}
result = RxFifo_Size(); // result = 9
result = RxFifo_Get(&letter); // letter = 0x41, result = 1
result = RxFifo_Size(); // result = 8
result = RxFifo_Get(&letter); // letter = 0x42, result = 1
result = RxFifo_Size(); // result = 7
result = RxFifo_Put(' '); // result = 1
result = RxFifo_Size(); // result = 8
// *********** Test #3: test transmit (index) FIFO creator **********
Tx2Fifo_Init();
result = Tx2Fifo_Get(&letter);// letter = ??, result = 0
result = Tx2Fifo_Put('A'); // result = 1
result = Tx2Fifo_Put('B'); // result = 1
result = Tx2Fifo_Put('C'); // result = 1
result = Tx2Fifo_Get(&letter);// letter = 0x41, result = 1
result = Tx2Fifo_Get(&letter);// letter = 0x42, result = 1
result = Tx2Fifo_Put('D'); // result = 1
result = Tx2Fifo_Size(); // result = 2
result = Tx2Fifo_Get(&letter);// letter = 0x43, result = 1
result = Tx2Fifo_Get(&letter);// letter = 0x44, result = 1
result = Tx2Fifo_Size(); // result = 0
result = Tx2Fifo_Get(&letter);// letter = ??, result = 0
for(i='A'; i<'A'+TX2FIFOSIZE; i=i+1){
result = Tx2Fifo_Put(i); // result = 1
}
result = Tx2Fifo_Size(); // result = 32
result = Tx2Fifo_Get(&letter);// letter = 0x41, result = 1
result = Tx2Fifo_Size(); // result = 31
result = Tx2Fifo_Get(&letter);// letter = 0x42, result = 1
result = Tx2Fifo_Size(); // result = 30
result = Tx2Fifo_Put(' '); // result = 1
result = Tx2Fifo_Size(); // result = 31
// *********** Test #4: test receive (pointer) FIFO creator *********
Rx2Fifo_Init();
result = Rx2Fifo_Get(&letter);// letter = ??, result = 0
result = Rx2Fifo_Put('A'); // result = 1
result = Rx2Fifo_Put('B'); // result = 1
result = Rx2Fifo_Put('C'); // result = 1
result = Rx2Fifo_Get(&letter);// letter = 0x41, result = 1
result = Rx2Fifo_Get(&letter);// letter = 0x42, result = 1
result = Rx2Fifo_Put('D'); // result = 1
result = Rx2Fifo_Size(); // result = 2
result = Rx2Fifo_Get(&letter);// letter = 0x43, result = 1
result = Rx2Fifo_Get(&letter);// letter = 0x44, result = 1
result = Rx2Fifo_Size(); // result = 0
result = Rx2Fifo_Get(&letter);// letter = ??, result = 0
for(i='A'; i<'A'+RX2FIFOSIZE-1; i=i+1){
result = Rx2Fifo_Put(i); // result = 1
}
result = Rx2Fifo_Size(); // result = 26
result = Rx2Fifo_Get(&letter);// letter = 0x41, result = 1
result = Rx2Fifo_Size(); // result = 25
result = Rx2Fifo_Get(&letter);// letter = 0x42, result = 1
result = Rx2Fifo_Size(); // result = 24
result = Rx2Fifo_Put(' '); // result = 1
result = Rx2Fifo_Size(); // result = 25
while(1);
}
int main(void){
int i;
SysCtlClockSet(SYSCTL_SYSDIV_4 | SYSCTL_USE_PLL | SYSCTL_OSC_MAIN |
SYSCTL_XTAL_8MHZ); // 50 MHz
// **** general initialization ****
DisableInterrupts();
SYSCTL_RCGC1_R |= SYSCTL_RCGC1_TIMER0;// activate timer0
SYSCTL_RCGC2_R |= SYSCTL_RCGC2_GPIOF+SYSCTL_RCGC2_GPIOG; // activate ports F and G
BackData = 0; // allow time to finish activating
BackCounter = 0;
EnteredCount = 0;
ForeExpected = 0;
Errors = 0;
EnterGet = 0;
GPIO_PORTF_DIR_R |= 0x0F; // make PF3-PF0 out (connect to scope/logic analyzer)
GPIO_PORTF_DEN_R |= 0x0F; // enable digital I/O on PF3-PF0
GPIO_PORTG_DIR_R |= 0x04; // make PG2 out (PG2 built-in LED)
GPIO_PORTG_DEN_R |= 0x04; // enable digital I/O on PG2
GPIO_PORTG2 = 0x00; // clear PG2
GPIO_PORTF0 = 0x00;
GPIO_PORTF1 = 0x00;
GPIO_PORTF2 = 0x00;
TIMER0_CTL_R &= ~TIMER_CTL_TAEN; // disable timer0A during setup
TIMER0_CFG_R = TIMER_CFG_16_BIT; // configure for 16-bit timer mode
// **** timer0A initialization ****
TIMER0_TAMR_R = TIMER_TAMR_TAMR_PERIOD;// configure for periodic mode
TIMER0_TAILR_R = INTPERIOD - 1; // start value to count down from
TIMER0_IMR_R |= TIMER_IMR_TATOIM;// enable timeout (rollover) interrupt
TIMER0_ICR_R = TIMER_ICR_TATOCINT;// clear timer0A timeout flag
// **** interrupt initialization ****
// Timer0A=priority 2
NVIC_PRI4_R = (NVIC_PRI4_R&0x00FFFFFF)|0x40000000; // top 3 bits
NVIC_EN0_R |= NVIC_EN0_INT19; // enable interrupt 19 in NVIC
// *************** Test #5: test interrupt vulnerability ************
RxFifo_Init();
for(i=0; i<HISTOGRAMSIZE; i=i+1){ unsigned long returnaddress;
LineHistogram[i] = 0;
returnaddress = ((unsigned long)&RxFifo_Get + 2*i)&0xFFFFFFFE;
LineHistogramAddress[i] = returnaddress; // possible places in Get that could be interrupted
}
TIMER0_ICR_R = TIMER_ICR_TATOCINT;// clear timer0A timeout flag
TIMER0_CTL_R |= TIMER_CTL_TAEN; // enable timer0A 16-b, periodic, interrupts
EnableInterrupts();
while(1){
do{
GPIO_PORTF0 = 1; // profile of main program
EnterGet = 1;
i = RxFifo_Get(&ForeActual); // i = 0 (FIFOFAIL) if error
EnterGet = 0;
GPIO_PORTF0 = 0;
}
while(!i);
GPIO_PORTF1 = 2; // profile of main program
if(ForeExpected != ForeActual){
Errors = Errors + 1; // critical section found
ForeExpected = ForeActual + 1; // resych to lost/bad data
GPIO_PORTG2 = 0x04; // set PG2, means error
}
else{
ForeExpected = ForeExpected + 1;// sequence is 0,1,2,3,...,254,255,0,1,...
}
GPIO_PORTF1 = 0;
}
}
//-------------------------SCI_Init------------------------
// Initialize Serial port
// Input: baudRate is the baud rate in bits/sec
// Output: none
// SCI0BDL=1500000/baudRate, for example
// baudRate = 9600 bits/sec SCI0BDL=156
// baudRate = 19200 bits/sec SCI0BDL=78
// baudRate = 38400 bits/sec SCI0BDL=39
// baudRate = 115200 bits/sec SCI0BDL=13
// assumes a module clock frequency of 24 MHz
// baud rate must be faster than 5900 bits/sec
void SCI_Init(unsigned char port, unsigned long baudRate){
if(port==0) {
RxFifo_Init(port);
TxFifo_Init(port);
//SCI0BDH = 0; // br=MCLK/(16*BaudRate)
//SCI0BDL = 500000L/baudRate; //ECLK = 8mhz
SCI0BD = 1500000L/baudRate; //ECLK = 24mhz
//SCI0BDL = 2000000L/baudRate; //ECLK = 32mhz
SCI0CR1 = 0;
/* bit value meaning
7 0 LOOPS, no looping, normal
6 0 WOMS, normal high/low outputs
5 0 RSRC, not appliable with LOOPS=0
4 0 M, 1 start, 8 data, 1 stop
3 0 WAKE, wake by idle (not applicable)
2 0 ILT, short idle time (not applicable)
1 0 PE, no parity
0 0 PT, parity type (not applicable with PE=0) */
SCI0CR2 = 0x2C;
/* bit value meaning
7 0 TIE, no transmit interrupts on TDRE
6 0 TCIE, no transmit interrupts on TC
5 1 RIE, no receive interrupts on RDRF
4 0 ILIE, no interrupts on idle
3 1 TE, enable transmitter
2 1 RE, enable receiver
1 0 RWU, no receiver wakeup
0 0 SBK, no send break */
}
if(port==1) {
RxFifo_Init(port);
TxFifo_Init(port);
//SCI1BDH = 0; // br=MCLK/(16*BaudRate)
//SCI0BDL = 500000L/baudRate; //ECLK = 8mhz
SCI1BD = 1500000L/baudRate; //ECLK = 24mhz
//SCI0BDL = 2000000L/baudRate; //ECLK = 32mhz
SCI1CR1 = 0;
/* bit value meaning
7 0 LOOPS, no looping, normal
6 0 WOMS, normal high/low outputs
5 0 RSRC, not appliable with LOOPS=0
4 0 M, 1 start, 8 data, 1 stop
3 0 WAKE, wake by idle (not applicable)
2 0 ILT, short idle time (not applicable)
1 0 PE, no parity
0 0 PT, parity type (not applicable with PE=0) */
//SCI1CR2 = 0x2C;
//SCI1CR2 = 0x0C;
/* bit value meaning
7 0 TIE, no transmit interrupts on TDRE
6 0 TCIE, no transmit interrupts on TC
5 1 RIE, no receive interrupts on RDRF
4 0 ILIE, no interrupts on idle
3 1 TE, enable transmitter
2 1 RE, enable receiver
1 0 RWU, no receiver wakeup
0 0 SBK, no send break */
}
asm cli /* enable interrupts */
}
