void enable_board_pin_mux(void) { configure_module_pin_mux(mmc0_pin_mux); configure_module_pin_mux(i2c0_pin_mux); configure_module_pin_mux(mdio_pin_mux); if (board_is_gpevm()) { configure_module_pin_mux(gpio5_7_pin_mux); configure_module_pin_mux(rgmii1_pin_mux); #if defined(CONFIG_NAND) configure_module_pin_mux(nand_pin_mux); #endif } else if (board_is_sk() || board_is_idk()) { configure_module_pin_mux(rgmii1_pin_mux); #if defined(CONFIG_NAND) printf("Error: NAND flash not present on this board\n"); #endif configure_module_pin_mux(qspi_pin_mux); } else if (board_is_eposevm()) { configure_module_pin_mux(rmii1_pin_mux); #if defined(CONFIG_NAND) configure_module_pin_mux(nand_pin_mux); #else configure_module_pin_mux(qspi_pin_mux); #endif } }
const struct dpll_params *get_dpll_ddr_params(void) { if (board_is_eposevm()) return &epos_evm_dpll_ddr; else if (board_is_gpevm() || board_is_sk()) return &gp_evm_dpll_ddr; printf(" Board '%s' not supported\n", am43xx_board_name); return NULL; }
void emif_get_ext_phy_ctrl_const_regs(const u32 **regs, u32 *size) { if (board_is_eposevm()) { *regs = ext_phy_ctrl_const_base_lpddr2; *size = ARRAY_SIZE(ext_phy_ctrl_const_base_lpddr2); } else if (board_is_gpevm()) { *regs = ext_phy_ctrl_const_base_ddr3; *size = ARRAY_SIZE(ext_phy_ctrl_const_base_ddr3); } return; }
void enable_board_pin_mux(void) { configure_module_pin_mux(mmc0_pin_mux); configure_module_pin_mux(i2c0_pin_mux); configure_module_pin_mux(mdio_pin_mux); if (board_is_gpevm()) { configure_module_pin_mux(gpio5_7_pin_mux); configure_module_pin_mux(rgmii1_pin_mux); } else if (board_is_eposevm()) { configure_module_pin_mux(rmii1_pin_mux); configure_module_pin_mux(qspi_pin_mux); } }
u32 rtc_only_get_board_type(void) { if (board_is_eposevm()) return RTC_BOARD_EPOS; else if (board_is_evm_14_or_later()) return RTC_BOARD_EVM14; else if (board_is_evm_12_or_later()) return RTC_BOARD_EVM12; else if (board_is_gpevm()) return RTC_BOARD_GPEVM; else if (board_is_sk()) return RTC_BOARD_SK; return 0; }
const struct dpll_params *get_dpll_ddr_params(void) { struct am43xx_board_id header; enable_i2c0_pin_mux(); i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE); if (read_eeprom(&header) < 0) puts("Could not get board ID.\n"); if (board_is_eposevm()) return &epos_evm_dpll_ddr; else if (board_is_gpevm()) return &gp_evm_dpll_ddr; puts(" Board not supported\n"); return NULL; }
void emif_get_ext_phy_ctrl_const_regs(const u32 **regs, u32 *size) { if (board_is_eposevm()) { *regs = ext_phy_ctrl_const_base_lpddr2; *size = ARRAY_SIZE(ext_phy_ctrl_const_base_lpddr2); } else if (board_is_evm_14_or_later()) { *regs = ext_phy_ctrl_const_base_ddr3_production; *size = ARRAY_SIZE(ext_phy_ctrl_const_base_ddr3_production); } else if (board_is_evm_12_or_later()) { *regs = ext_phy_ctrl_const_base_ddr3_beta; *size = ARRAY_SIZE(ext_phy_ctrl_const_base_ddr3_beta); } else if (board_is_gpevm()) { *regs = ext_phy_ctrl_const_base_ddr3; *size = ARRAY_SIZE(ext_phy_ctrl_const_base_ddr3); } else if (board_is_sk()) { *regs = ext_phy_ctrl_const_base_ddr3_sk; *size = ARRAY_SIZE(ext_phy_ctrl_const_base_ddr3_sk); } return; }