/* C code entry point for the boot block */
void bootblock_main(const uint64_t reg_x0,
const uint64_t reg_pc)
{
uint64_t base_timestamp = 0;
init_timer();
if (IS_ENABLED(CONFIG_COLLECT_TIMESTAMPS))
base_timestamp = timestamp_get();
/* Initialize timestamps if we have TIMESTAMP region in memlayout.ld. */
if (IS_ENABLED(CONFIG_COLLECT_TIMESTAMPS) && _timestamp_size > 0)
timestamp_init(base_timestamp);
bootblock_soc_early_init();
bootblock_mainboard_early_init();
if (IS_ENABLED(CONFIG_BOOTBLOCK_CONSOLE)) {
console_init();
exception_init();
if (reg_x0)
printk(BIOS_ERR,
"BOOTBLOCK: RST Boot Failure Code %lld\n",
reg_x0);
}
bootblock_soc_init();
bootblock_mainboard_init();
run_romstage();
}
void main(void)
{
bootblock_cpu_init();
bootblock_mainboard_init();
#if CONFIG_BOOTBLOCK_CONSOLE
console_init();
#endif
bootblock_mmu_init();
run_romstage();
}
void main(void)
{
init_timer();
if (IS_ENABLED(CONFIG_HAS_PRECBMEM_TIMESTAMP_REGION))
timestamp_init(timestamp_get());
bootblock_mainboard_early_init();
#if CONFIG_BOOTBLOCK_CONSOLE
console_init();
exception_init();
#endif
bootblock_soc_init();
bootblock_mainboard_init();
run_romstage();
}
void main(void)
{
const char *stage_name = "fallback/romstage";
void *entry;
bootblock_cpu_init();
bootblock_mainboard_init();
if (CONFIG_BOOTBLOCK_CONSOLE) {
console_init();
exception_init();
}
entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, stage_name);
if (entry) stage_exit(entry);
hlt();
}
void main(void)
{
const char *stage_name = "fallback/romstage";
void *entry;
if (boot_cpu()) {
bootblock_cpu_init();
bootblock_mainboard_init();
}
console_init();
printk(BIOS_INFO, "hello from bootblock\n");
printk(BIOS_INFO, "bootblock main(): loading romstage\n");
entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, stage_name);
printk(BIOS_INFO, "bootblock main(): jumping to romstage\n");
if (entry) stage_exit(entry);
hlt();
}
static void main(unsigned long bist)
{
u8 boot_mode;
const char *default_filenames =
"normal/romstage\0fallback/romstage";
if (boot_cpu()) {
bootblock_mainboard_init();
#if CONFIG_USE_OPTION_TABLE
sanitize_cmos();
#endif
boot_mode = do_normal_boot();
} else {
/* Questionable single byte read from CMOS.
* Do not add any other CMOS access in the
* bootblock for AP CPUs.
*/
boot_mode = boot_use_normal(cmos_read(RTC_BOOT_BYTE));
}
char *normal_candidate = (char *)walkcbfs("coreboot-stages");
if (!normal_candidate)
normal_candidate = default_filenames;
unsigned long entry;
if (boot_mode) {
entry = findstage(normal_candidate);
if (entry)
call(entry, bist);
}
entry = findstage(get_fallback(normal_candidate));
if (entry)
call(entry, bist);
/* duh. we're stuck */
halt();
}
void main(void)
{
// enable pinmux clamp inputs
clamp_tristate_inputs();
// enable JTAG at the earliest stage
enable_jtag();
clock_early_uart();
// Serial out, tristate off.
pinmux_set_config(PINMUX_KB_ROW9_INDEX, PINMUX_KB_ROW9_FUNC_UA3);
// Serial in, tristate_on.
pinmux_set_config(PINMUX_KB_ROW10_INDEX, PINMUX_KB_ROW10_FUNC_UA3 |
PINMUX_PULL_UP |
PINMUX_INPUT_ENABLE);
// Mux some pins away from uart A.
pinmux_set_config(PINMUX_UART2_CTS_N_INDEX,
PINMUX_UART2_CTS_N_FUNC_UB3 |
PINMUX_INPUT_ENABLE);
pinmux_set_config(PINMUX_UART2_RTS_N_INDEX,
PINMUX_UART2_RTS_N_FUNC_UB3);
if (CONFIG_BOOTBLOCK_CONSOLE) {
console_init();
exception_init();
}
clock_init();
bootblock_mainboard_init();
pinmux_set_config(PINMUX_CORE_PWR_REQ_INDEX,
PINMUX_CORE_PWR_REQ_FUNC_PWRON);
pinmux_set_config(PINMUX_CPU_PWR_REQ_INDEX,
PINMUX_CPU_PWR_REQ_FUNC_CPU);
pinmux_set_config(PINMUX_PWR_INT_N_INDEX,
PINMUX_PWR_INT_N_FUNC_PMICINTR |
PINMUX_INPUT_ENABLE);
run_romstage();
}
void main(void)
{
bootblock_cpu_init();
/* Mainboard basic init */
bootblock_mainboard_init();
#if CONFIG_BOOTBLOCK_CONSOLE
console_init();
#endif
bootblock_mmu_init();
if (init_extra_hardware()) {
printk(BIOS_ERR, "bootblock_simple: failed to init HW.\n");
} else {
run_romstage();
}
halt();
}
asmlinkage void bootblock_main_with_timestamp(uint64_t base_timestamp)
{
/* Initialize timestamps if we have TIMESTAMP region in memlayout.ld. */
if (IS_ENABLED(CONFIG_COLLECT_TIMESTAMPS) && _timestamp_size > 0)
timestamp_init(base_timestamp);
cmos_post_init();
bootblock_soc_early_init();
bootblock_mainboard_early_init();
if (IS_ENABLED(CONFIG_BOOTBLOCK_CONSOLE)) {
console_init();
exception_init();
}
bootblock_soc_init();
bootblock_mainboard_init();
run_romstage();
}
void main(void)
{
void *entry;
clock_early_uart();
// Serial out, tristate off.
pinmux_set_config(PINMUX_KB_ROW9_INDEX, PINMUX_KB_ROW9_FUNC_UA3);
// Serial in, tristate_on.
pinmux_set_config(PINMUX_KB_ROW10_INDEX, PINMUX_KB_ROW10_FUNC_UA3 |
PINMUX_TRISTATE |
PINMUX_INPUT_ENABLE);
if (CONFIG_BOOTBLOCK_CONSOLE)
console_init();
clock_init();
bootblock_mainboard_init();
pinmux_set_config(PINMUX_CORE_PWR_REQ_INDEX,
PINMUX_CORE_PWR_REQ_FUNC_PWRON);
pinmux_set_config(PINMUX_CPU_PWR_REQ_INDEX,
PINMUX_CPU_PWR_REQ_FUNC_CPU);
pinmux_set_config(PINMUX_PWR_INT_N_INDEX,
PINMUX_PWR_INT_N_FUNC_PMICINTR |
PINMUX_TRISTATE |
PINMUX_INPUT_ENABLE);
power_enable_cpu_rail();
power_ungate_cpu();
entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, "fallback/romstage");
if (entry)
clock_cpu0_config_and_reset(entry);
hlt();
}
void main(void)
{
// enable JTAG at the earliest stage
enable_jtag();
clock_early_uart();
/* Configure mselect clock. */
clock_configure_source(mselect, PLLP, 102000);
/* Enable AVP cache, timer, APB dma, and mselect blocks. */
clock_enable_clear_reset(CLK_L_CACHE2 | CLK_L_TMR,
CLK_H_APBDMA,
0, CLK_V_MSELECT, 0, 0);
/* Find ODMDATA in IRAM and save it to scratch reg */
save_odmdata();
bootblock_mainboard_early_init();
if (CONFIG_BOOTBLOCK_CONSOLE) {
console_init();
exception_init();
printk(BIOS_INFO, "T132: Bootblock here\n");
}
clock_init();
printk(BIOS_INFO, "T132 bootblock: Clock init done\n");
pmc_print_rst_status();
bootblock_mainboard_init();
printk(BIOS_INFO, "T132 bootblock: Mainboard bootblock init done\n");
run_romstage();
}
void main(void)
{
const char *stage_name = "fallback/romstage";
void *entry;
uint32_t sctlr;
/* Globally disable MMU, caches, and branch prediction (these should
* be disabled by default on reset) */
sctlr = read_sctlr();
sctlr &= ~(SCTLR_M | SCTLR_C | SCTLR_Z | SCTLR_I);
write_sctlr(sctlr);
armv7_invalidate_caches();
/*
* Re-enable caches and branch prediction. MMU will be set up later.
* Note: If booting from USB, we need to disable branch prediction
* before copying from USB into RAM (FIXME: why?)
*/
sctlr = read_sctlr();
sctlr |= SCTLR_C | SCTLR_Z | SCTLR_I;
write_sctlr(sctlr);
if (boot_cpu()) {
bootblock_cpu_init();
bootblock_mainboard_init();
}
console_init();
printk(BIOS_INFO, "hello from bootblock\n");
printk(BIOS_INFO, "bootblock main(): loading romstage\n");
entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, stage_name);
printk(BIOS_INFO, "bootblock main(): jumping to romstage\n");
if (entry) stage_exit(entry);
hlt();
}
static void main(unsigned long bist)
{
if (boot_cpu()) {
bootblock_mainboard_init();
#if CONFIG_USE_OPTION_TABLE
sanitize_cmos();
#endif
#if CONFIG_CMOS_POST
cmos_post_init();
#endif
}
#if CONFIG_SEPARATE_VERSTAGE
const char* target1 = "fallback/verstage";
#else
const char* target1 = "fallback/romstage";
#endif
unsigned long entry;
entry = findstage(target1);
if (entry) call(entry, bist);
halt();
}
