void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { static const u16 spd_addr[] = { DIMM0, 0, 0, 0, DIMM1, 0, 0, 0, }; int needs_reset = 0; u32 bsp_apicid = 0; msr_t msr; struct cpuid_result cpuid1; struct sys_info *sysinfo = &sysinfo_car; if (!cpu_init_detectedx && boot_cpu()) { /* Nothing special needs to be done to find bus 0 */ /* Allow the HT devices to be found */ enumerate_ht_chain(); /* sb600_lpc_port80(); */ sb600_pci_port80(); } if (bist == 0) { bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); } enable_rs690_dev8(); // enable CFG access to Dev8, which is the SB P2P Bridge sb600_lpc_init(); #if defined(DUMP_CMOS_RAM) && (DUMP_CMOS_RAM == 0) check_cmos(); // rebooting in case of corrupted cmos !!!!! #endif ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); ite_kill_watchdog(GPIO_DEV); console_init(); #if defined(DUMP_CMOS_RAM) && (DUMP_CMOS_RAM == 1) check_cmos(); // rebooting in case of corrupted cmos !!!!! #endif post_code(0x03); /* Halt if there was a built in self test failure */ report_bist_failure(bist); __DEBUG__("bsp_apicid=0x%x\n", bsp_apicid); setup_sitemp_resource_map(); setup_coherent_ht_domain(); #if CONFIG_LOGICAL_CPUS /* It is said that we should start core1 after all core0 launched */ wait_all_core0_started(); start_other_cores(); #endif wait_all_aps_started(bsp_apicid); ht_setup_chains_x(sysinfo); /* run _early_setup before soft-reset. */ rs690_early_setup(); sb600_early_setup(); post_code(0x04); /* Check to see if processor is capable of changing FIDVID */ /* otherwise it will throw a GP# when reading FIDVID_STATUS */ cpuid1 = cpuid(0x80000007); if( (cpuid1.edx & 0x6) == 0x6 ) { /* Read FIDVID_STATUS */ msr=rdmsr(0xc0010042); __DEBUG__("begin msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo); enable_fid_change(); enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn); init_fidvid_bsp(bsp_apicid); /* show final fid and vid */ msr=rdmsr(0xc0010042); __DEBUG__("end msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo); } else { __DEBUG__("Changing FIDVID not supported\n"); } post_code(0x05); needs_reset = optimize_link_coherent_ht(); needs_reset |= optimize_link_incoherent_ht(sysinfo); rs690_htinit(); __DEBUG__("needs_reset=0x%x\n", needs_reset); post_code(0x06); if (needs_reset) { __INFO__("ht reset -\n"); soft_reset(); } allow_all_aps_stop(bsp_apicid); /* It's the time to set ctrl now; */ __DEBUG__("sysinfo->nodes: %2x sysinfo->ctrl: %p spd_addr: %p\n", sysinfo->nodes, sysinfo->ctrl, spd_addr); fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr); post_code(0x07); sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo); post_code(0x08); rs690_before_pci_init(); // does nothing sb600_before_pci_init(); post_cache_as_ram(); }
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { struct sys_info *sysinfo = &sysinfo_car; u32 bsp_apicid = 0, val; msr_t msr; if (!cpu_init_detectedx && boot_cpu()) { /* Nothing special needs to be done to find bus 0 */ /* Allow the HT devices to be found */ /* mov bsp to bus 0xff when > 8 nodes */ set_bsp_node_CHtExtNodeCfgEn(); enumerate_ht_chain(); bcm5785_enable_lpc(); pc87417_enable_dev(RTC_DEV); /* Enable RTC */ } post_code(0x30); if (bist == 0) bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); pilot_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); /* Halt if there was a built in self test failure */ report_bist_failure(bist); pilot_early_init(SERIAL_DEV); //config port is being taken from SERIAL_DEV val = cpuid_eax(1); printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1); printk(BIOS_DEBUG, "bsp_apicid = %02x\n", bsp_apicid); printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); /* Setup sysinfo defaults */ set_sysinfo_in_ram(0); #if CONFIG_UPDATE_CPU_MICROCODE update_microcode(val); #endif post_code(0x33); cpuSetAMDMSR(); post_code(0x34); amd_ht_init(sysinfo); post_code(0x35); /* Setup nodes PCI space and start core 0 AP init. */ finalize_node_setup(sysinfo); post_code(0x36); /* wait for all the APs core0 started by finalize_node_setup. */ /* FIXME: A bunch of cores are going to start output to serial at once. * It would be nice to fixup prink spinlocks for ROM XIP mode. * I think it could be done by putting the spinlock flag in the cache * of the BSP located right after sysinfo. */ wait_all_core0_started(); #if CONFIG_LOGICAL_CPUS /* Core0 on each node is configured. Now setup any additional cores. */ printk(BIOS_DEBUG, "start_other_cores()\n"); start_other_cores(); post_code(0x37); wait_all_other_cores_started(bsp_apicid); #endif #if CONFIG_SET_FIDVID msr = rdmsr(0xc0010071); printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); /* FIXME: The sb fid change may survive the warm reset and only * need to be done once.*/ enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn); post_code(0x39); if (!warm_reset_detect(0)) { // BSP is node 0 init_fidvid_bsp(bsp_apicid, sysinfo->nodes); } else { init_fidvid_stage2(bsp_apicid, 0); // BSP is node 0 } post_code(0x3A); /* show final fid and vid */ msr=rdmsr(0xc0010071); printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); #endif init_timer(); /* Reset for HT, FIDVID, PLL and errata changes to take affect. */ if (!warm_reset_detect(0)) { print_info("...WARM RESET...\n\n\n"); soft_reset(); die("After soft_reset_x - shouldn't see this message!!!\n"); } /* It's the time to set ctrl in sysinfo now; */ fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr); enable_smbus(); //do we need apci timer, tsc...., only debug need it for better output /* all ap stopped? */ // init_timer(); // Need to use TMICT to synconize FID/VID printk(BIOS_DEBUG, "raminit_amdmct()\n"); raminit_amdmct(sysinfo); post_code(0x41); bcm5785_early_setup(); post_cache_as_ram(); }
int _main(unsigned zero, unsigned type, unsigned tags) { const char *cmdline = 0; int n; arm11_clock_init(); /* must do this before board_init() so that we ** use the partition table in the tags if it ** already exists */ if((zero == 0) && (type != 0) && tags_okay(tags)) { linux_type = type; linux_tags = tags; cmdline = tags_get_cmdline((void*) linux_tags); tags_import_partitions((void*) linux_tags); revision = tags_get_revision((void*) linux_tags); if(revision == 1) { console_set_colors(0x03E0, 0xFFFF); } if(revision == 2) { console_set_colors(0x49B2, 0xFFFF); } /* we're running as a second-stage, so wait for interrupt */ boot_from_flash = 0; } else { linux_type = board_machtype(); linux_tags = 0; } board_init(); keypad_init(); console_init(); dprintf_set_putc(uart_putc); if(linux_tags == 0) { /* generate atags containing partitions * from the bootloader, etc */ linux_tags = ADDR_TAGS; create_atags(linux_tags, 0, 0, 0); } if (cmdline) { char *sn = strstr(cmdline, SERIALNO_STR); if (sn) { char *s = serialno; sn += SERIALNO_LEN; while (*sn && (*sn != ' ') && ((s - serialno) < 31)) { *s++ = *sn++; } *s++ = 0; } } cprintf("\n\nUSB FastBoot: V%s\n", get_fastboot_version()); cprintf("Machine ID: %d v%d\n", linux_type, revision); cprintf("Build Date: "__DATE__", "__TIME__"\n\n"); cprintf("Serial Number: %s\n\n", serialno[0] ? serialno : "UNKNOWN"); flash_dump_ptn(); flash_init(); /* scan the keyboard a bit */ for(n = 0; n < 50; n++) { boot_poll(); } if (boot_from_flash) { cprintf("\n ** BOOTING LINUX FROM FLASH **\n"); boot_linux_from_flash(); } usbloader_init(); for(;;) { usb_poll(); } return 0; }
int main(int argc, char *argv[]) { kbd_event_t ev; coord_t coord; bool new_file; spt_t pt; con = console_init(stdin, stdout); console_clear(con); console_get_size(con, &scr_columns, &scr_rows); pane.rows = scr_rows - 1; pane.columns = scr_columns; pane.sh_row = 1; pane.sh_column = 1; /* Start with an empty sheet. */ sheet_init(&doc.sh); /* Place caret at the beginning of file. */ coord.row = coord.column = 1; sheet_get_cell_pt(&doc.sh, &coord, dir_before, &pt); sheet_place_tag(&doc.sh, &pt, &pane.caret_pos); pane.ideal_column = coord.column; if (argc == 2) { doc.file_name = str_dup(argv[1]); } else if (argc > 1) { printf("Invalid arguments.\n"); return -2; } else { doc.file_name = NULL; } new_file = false; if (doc.file_name == NULL || file_insert(doc.file_name) != EOK) new_file = true; /* Move to beginning of file. */ caret_move(-ED_INFTY, -ED_INFTY, dir_before); /* Place selection start tag. */ tag_get_pt(&pane.caret_pos, &pt); sheet_place_tag(&doc.sh, &pt, &pane.sel_start); /* Initial display */ cursor_visible = true; cursor_hide(); console_clear(con); pane_text_display(); pane_status_display(); if (new_file && doc.file_name != NULL) status_display("File not found. Starting empty file."); pane_caret_display(); cursor_show(); done = false; while (!done) { console_get_kbd_event(con, &ev); pane.rflags = 0; if (ev.type == KEY_PRESS) { /* Handle key press. */ if (((ev.mods & KM_ALT) == 0) && ((ev.mods & KM_SHIFT) == 0) && (ev.mods & KM_CTRL) != 0) { key_handle_ctrl(&ev); } else if (((ev.mods & KM_ALT) == 0) && ((ev.mods & KM_CTRL) == 0) && (ev.mods & KM_SHIFT) != 0) { key_handle_shift(&ev); } else if ((ev.mods & (KM_CTRL | KM_ALT | KM_SHIFT)) == 0) { key_handle_unmod(&ev); } } /* Redraw as necessary. */ cursor_hide(); if (pane.rflags & REDRAW_TEXT) pane_text_display(); if (pane.rflags & REDRAW_ROW) pane_row_display(); if (pane.rflags & REDRAW_STATUS) pane_status_display(); if (pane.rflags & REDRAW_CARET) pane_caret_display(); cursor_show(); } console_clear(con); return 0; }
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { struct sys_info *sysinfo = &sysinfo_car; static const u8 spd_addr[] = {RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, }; u32 bsp_apicid = 0, val; msr_t msr; timestamp_init(timestamp_get()); timestamp_add_now(TS_START_ROMSTAGE); if (!cpu_init_detectedx && boot_cpu()) { /* Nothing special needs to be done to find bus 0 */ /* Allow the HT devices to be found */ /* mov bsp to bus 0xff when > 8 nodes */ set_bsp_node_CHtExtNodeCfgEn(); enumerate_ht_chain(); sb7xx_51xx_pci_port80(); } post_code(0x30); if (bist == 0) { bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); /* mmconf is inited in init_cpus */ /* All cores run this but the BSP(node0,core0) is the only core that returns. */ } post_code(0x32); enable_rs780_dev8(); sb7xx_51xx_lpc_init(); ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); it8718f_disable_reboot(GPIO_DEV); console_init(); /* Halt if there was a built in self test failure */ report_bist_failure(bist); // Load MPB val = cpuid_eax(1); printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1); printk(BIOS_DEBUG, "bsp_apicid = %02x\n", bsp_apicid); printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); /* Setup sysinfo defaults */ set_sysinfo_in_ram(0); update_microcode(val); post_code(0x33); cpuSetAMDMSR(); post_code(0x34); amd_ht_init(sysinfo); post_code(0x35); /* Setup nodes PCI space and start core 0 AP init. */ finalize_node_setup(sysinfo); /* Setup any mainboard PCI settings etc. */ setup_mb_resource_map(); post_code(0x36); /* wait for all the APs core0 started by finalize_node_setup. */ /* FIXME: A bunch of cores are going to start output to serial at once. It would be nice to fixup prink spinlocks for ROM XIP mode. I think it could be done by putting the spinlock flag in the cache of the BSP located right after sysinfo. */ wait_all_core0_started(); #if CONFIG_LOGICAL_CPUS /* Core0 on each node is configured. Now setup any additional cores. */ printk(BIOS_DEBUG, "start_other_cores()\n"); start_other_cores(); post_code(0x37); wait_all_other_cores_started(bsp_apicid); #endif post_code(0x38); /* run _early_setup before soft-reset. */ rs780_early_setup(); sb7xx_51xx_early_setup(); #if CONFIG_SET_FIDVID msr = rdmsr(0xc0010071); printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); /* FIXME: The sb fid change may survive the warm reset and only need to be done once.*/ enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn); post_code(0x39); if (!warm_reset_detect(0)) { // BSP is node 0 init_fidvid_bsp(bsp_apicid, sysinfo->nodes); } else { init_fidvid_stage2(bsp_apicid, 0); // BSP is node 0 } post_code(0x3A); /* show final fid and vid */ msr=rdmsr(0xc0010071); printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); #endif rs780_htinit(); /* Reset for HT, FIDVID, PLL and errata changes to take affect. */ if (!warm_reset_detect(0)) { printk(BIOS_INFO, "...WARM RESET...\n\n\n"); soft_reset(); die("After soft_reset_x - shouldn't see this message!!!\n"); } post_code(0x3B); /* It's the time to set ctrl in sysinfo now; */ printk(BIOS_DEBUG, "fill_mem_ctrl()\n"); fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr); post_code(0x40); // die("Die Before MCT init."); timestamp_add_now(TS_BEFORE_INITRAM); printk(BIOS_DEBUG, "raminit_amdmct()\n"); raminit_amdmct(sysinfo); timestamp_add_now(TS_AFTER_INITRAM); cbmem_initialize_empty(); post_code(0x41); amdmct_cbmem_store_info(sysinfo); /* dump_pci_device_range(PCI_DEV(0, 0x18, 0), 0, 0x200); dump_pci_device_range(PCI_DEV(0, 0x18, 1), 0, 0x200); dump_pci_device_range(PCI_DEV(0, 0x18, 2), 0, 0x200); dump_pci_device_range(PCI_DEV(0, 0x18, 3), 0, 0x200); */ // die("After MCT init before CAR disabled."); rs780_before_pci_init(); sb7xx_51xx_before_pci_init(); post_code(0x42); post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB. post_code(0x43); // Should never see this post code. }
void boardsupport_init(central_data_t *central_data) { irq_initialize_vectors(); cpu_irq_enable(); Disable_global_interrupt(); // Initialize the sleep manager sleepmgr_init(); sysclk_init(); board_init(); delay_init(sysclk_get_cpu_hz()); time_keeper_init(); INTC_init_interrupts(); // Switch on the red LED LED_On(LED2); // servo_pwm_hardware_init(); pwm_servos_init( CS_ON_SERVO_7_8 ); // Init UART 0 for XBEE communication xbee_init(UART0); // Init UART 4 for wired communication //console_init(CONSOLE_UART4); // Init USB for wired communication console_init(CONSOLE_USB); // connect abstracted aliases to hardware ports central_data->telemetry_down_stream = xbee_get_out_stream(); central_data->telemetry_up_stream = xbee_get_in_stream(); central_data->debug_out_stream = console_get_out_stream(); central_data->debug_in_stream = console_get_in_stream(); // init debug output print_util_dbg_print_init(central_data->debug_out_stream); print_util_dbg_print("Debug stream initialised\r\n"); // RC receiver initialization spektrum_satellite_init(); // init imu & compass i2c_driver_init(I2C0); lsm330dlc_init(); print_util_dbg_print("LSM330 initialised \r\n"); hmc5883l_init_slow(); print_util_dbg_print("HMC5883 initialised \r\n"); // init radar or ultrasound (not implemented yet) //i2c_driver_init(I2C1); // init 6V enable gpio_enable_gpio_pin(AVR32_PIN_PA04); gpio_set_gpio_pin(AVR32_PIN_PA04); Enable_global_interrupt(); // Init piezo speaker piezo_speaker_init_binary(); print_util_dbg_print("Board initialised\r\n"); }
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { static const uint16_t spd_addr[] = { // Node 0 DIMM0, DIMM1, DIMM2, 0, 0, 0, 0, 0, // Node 1 0, 0, 0, 0, 0, 0, 0, 0, }; unsigned bsp_apicid = 0; int needs_reset = 0; struct sys_info *sysinfo = &sysinfo_car; winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); enable_rom_decode(); print_info("now booting... fallback\n"); /* Is this a CPU only reset? Or is this a secondary CPU? */ if (!cpu_init_detectedx && boot_cpu()) { /* Nothing special needs to be done to find bus 0. */ /* Allow the HT devices to be found. */ enumerate_ht_chain(); } print_info("now booting... real_main\n"); if (bist == 0) bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); /* Halt if there was a built in self test failure. */ report_bist_failure(bist); setup_default_resource_map(); setup_coherent_ht_domain(); wait_all_core0_started(); print_info("now booting... Core0 started\n"); #if CONFIG_LOGICAL_CPUS /* It is said that we should start core1 after all core0 launched. */ start_other_cores(); wait_all_other_cores_started(bsp_apicid); #endif init_timer(); ht_setup_chains_x(sysinfo); /* Init sblnk and sbbusn, nodes, sbdn. */ needs_reset = optimize_link_coherent_ht(); needs_reset |= optimize_link_incoherent_ht(sysinfo); needs_reset |= k8t890_early_setup_ht(); if (needs_reset) { print_debug("ht reset -\n"); soft_reset(); } /* the HT settings needs to be OK, because link freq change may cause HT disconnect */ vt8237_sb_enable_fid_vid(); enable_fid_change(); init_fidvid_bsp(bsp_apicid); /* Stop the APs so we can start them later in init. */ allow_all_aps_stop(bsp_apicid); /* It's the time to set ctrl now. */ fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr); enable_smbus(); /* this seems to be some GPIO on the SMBus--in any case, setting these * two bits reduces the pullup impedance of the bus lines and is required * in order to be able to read SPD info */ smbus_write_byte(0x48, 0x07, smbus_read_byte(0x48, 0x07) | 0x80); smbus_write_byte(0x4a, 0x07, smbus_read_byte(0x4a, 0x07) | 0x10); unsigned char mask; mask = 0; // mask |= 1 /* AGP voltage 1.7 V (not verified, just vendor BIOS value) */ // mask |= 2 /* V-Link voltage 2.6 V (not verified either) */ smbus_write_byte(0x4a, 0x00, (smbus_read_byte(0x4a, 0x00) & ~0x0f) | (0x0f ^ (mask << 2))); smbus_write_byte(0x4a, 0x01, (smbus_read_byte(0x4a, 0x01) & ~0x03) | (0x03 ^ mask)); mask = 25; /* RAM voltage in decivolts, valid range from 25 to 28 */ mask = 3 - (mask - 25); smbus_write_byte(0x4a, 0x02, 0x4f | (mask << 4)); smbus_write_byte(0x4a, 0x03, 0x04 | mask); sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo); post_cache_as_ram(); }
int main(int argc, char *argv[]) { int port = 2344; const char *config = "sys161.conf"; const char *kernel = NULL; int usetcp=0; char *argstr = NULL; int j, opt; size_t argsize=0; int debugwait=0; int pass_signals=0; #ifdef USE_TRACE int profiling=0; #endif int use_second_console=0; const char *second_console = NULL; unsigned ncpus; /* This must come absolutely first so msg() can be used. */ console_earlyinit(); if (sizeof(u_int32_t)!=4) { /* * Just in case. */ msg("sys161 requires sizeof(u_int32_t)==4"); die(); } while ((opt = mygetopt(argc, argv, "c:f:p:Pst:wk:"))!=-1) { switch (opt) { case 'c': config = myoptarg; break; case 'f': #ifdef USE_TRACE set_tracefile(myoptarg); #endif break; case 'p': port = atoi(myoptarg); usetcp=1; break; case 'P': #ifdef USE_TRACE profiling = 1; #endif break; case 's': pass_signals = 1; break; case 't': #ifdef USE_TRACE set_traceflags(myoptarg); #endif break; case 'w': debugwait = 1; break; case 'k': use_second_console = 1; second_console = myoptarg; break; default: usage(); break; } } if (myoptind==argc) { usage(); } kernel = argv[myoptind++]; for (j=myoptind; j<argc; j++) { argsize += strlen(argv[j])+1; } argstr = malloc(argsize+1); if (!argstr) { msg("malloc failed"); die(); } *argstr = 0; for (j=myoptind; j<argc; j++) { strcat(argstr, argv[j]); if (j<argc-1) strcat(argstr, " "); } /* This must come before bus_config in case a network card needs it */ mkdir(".sockets", 0700); console_init(pass_signals, use_second_console, second_console); clock_init(); ncpus = bus_config(config); initstats(ncpus); cpu_init(ncpus); if (usetcp) { gdb_inet_init(port); } else { unlink(".sockets/gdb"); gdb_unix_init(".sockets/gdb"); } unlink(".sockets/meter"); meter_init(".sockets/meter"); load_kernel(kernel, argstr); msg("System/161 %s, compiled %s %s", VERSION, __DATE__, __TIME__); #ifdef USE_TRACE print_traceflags(); if (profiling) { prof_setup(); } #endif if (debugwait) { stoploop(); } run(); #ifdef USE_TRACE if (profiling) { prof_write(); } #endif bus_cleanup(); console_cleanup(); clock_cleanup(); return 0; }
extern "C" int start_raw(int argc, const char **argv) { stage2_args args; clear_bss(); // call C++ constructors before doing anything else call_ctors(); args.heap_size = HEAP_SIZE; args.arguments = NULL; args.platform.boot_tgz_data = NULL; args.platform.boot_tgz_size = 0; args.platform.fdt_data = NULL; args.platform.fdt_size = 0; if (argv) { // skip the kernel name args.arguments = ++argv; args.arguments_count = --argc; } // if we get passed a uimage, try to find the third blob // only if we do not have FDT data yet if (gUImage != NULL && !gFDT && image_multi_getimg(gUImage, 2, (uint32*)&args.platform.fdt_data, &args.platform.fdt_size)) { // found a blob, assume it is FDT data, when working on a platform // which does not have an FDT enabled U-Boot gFDT = args.platform.fdt_data; } serial_init(gFDT); console_init(); // initialize the OpenFirmware wrapper of_init(NULL); cpu_init(); if (args.platform.fdt_data) { dprintf("Found FDT from uimage @ %p, %" B_PRIu32 " bytes\n", args.platform.fdt_data, args.platform.fdt_size); } else if (gFDT) { /* Fixup args so we can pass the gFDT on to the kernel */ args.platform.fdt_data = gFDT; args.platform.fdt_size = fdt_totalsize(gFDT); } // if we get passed an FDT, check /chosen for initrd and bootargs if (gFDT != NULL) { int node = fdt_path_offset(gFDT, "/chosen"); const void *prop; int len; phys_addr_t initrd_start = 0, initrd_end = 0; if (node >= 0) { prop = fdt_getprop(gFDT, node, "linux,initrd-start", &len); if (prop && len == 4) initrd_start = fdt32_to_cpu(*(uint32_t *)prop); prop = fdt_getprop(gFDT, node, "linux,initrd-end", &len); if (prop && len == 4) initrd_end = fdt32_to_cpu(*(uint32_t *)prop); if (initrd_end > initrd_start) { args.platform.boot_tgz_data = (void *)initrd_start; args.platform.boot_tgz_size = initrd_end - initrd_start; dprintf("Found boot tgz from FDT @ %p, %" B_PRIu32 " bytes\n", args.platform.boot_tgz_data, args.platform.boot_tgz_size); } prop = fdt_getprop(gFDT, node, "bootargs", &len); if (prop) { dprintf("Found bootargs: %s\n", (const char *)prop); static const char *sArgs[] = { NULL, NULL }; sArgs[0] = (const char *)prop; args.arguments = sArgs; args.arguments_count = 1; } } } // if we get passed a uimage, try to find the second blob if (gUImage != NULL && image_multi_getimg(gUImage, 1, (uint32*)&args.platform.boot_tgz_data, &args.platform.boot_tgz_size)) { dprintf("Found boot tgz from uimage @ %p, %" B_PRIu32 " bytes\n", args.platform.boot_tgz_data, args.platform.boot_tgz_size); } { //DEBUG: int i; dprintf("argc = %d\n", argc); for (i = 0; i < argc; i++) dprintf("argv[%d] @%lx = '%s'\n", i, (uint32)argv[i], argv[i]); dprintf("os: %d\n", (int)gUBootOS); dprintf("gd @ %p\n", gUBootGlobalData); if (gUBootGlobalData) dprintf("gd->bd @ %p\n", gUBootGlobalData->bd); //dprintf("fb_base %p\n", (void*)gUBootGlobalData->fb_base); if (gUImage) dump_uimage(gUImage); if (gFDT) dump_fdt(gFDT); } mmu_init(); // wait a bit to give the user the opportunity to press a key // spin(750000); // reading the keyboard doesn't seem to work in graphics mode // (maybe a bochs problem) // sBootOptions = check_for_boot_keys(); //if (sBootOptions & BOOT_OPTION_DEBUG_OUTPUT) serial_enable(); main(&args); return 0; }
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { u32 val; msr_t msr; /* * All cores: allow caching of flash chip code and data * (there are no cache-as-ram reliability concerns with family 14h) */ msr.lo = ((0x0100000000ull - CACHE_ROM_SIZE) | 5) & 0xFFFFFFFF; msr.hi = ((0x0100000000ull - CACHE_ROM_SIZE) | 5) >> 32; wrmsr (MSR_MTRR_VARIABLE_BASE6, msr); msr.lo = ((0x1000000000ull - CACHE_ROM_SIZE) | 0x800) & 0xFFFFFFFF; msr.hi = ((0x1000000000ull - CACHE_ROM_SIZE) | 0x800) >> 32; wrmsr (MSR_MTRR_VARIABLE_MASK6, msr); /* All cores: set pstate 0 (1600 MHz) early to save a few ms of boot time */ msr.lo = 0; msr.hi = 0; wrmsr (MSR_PSTATE_CONTROL, msr); amd_initmmio(); if (!cpu_init_detectedx && boot_cpu()) { post_code(0x30); sb_Poweron_Init(); post_code(0x31); console_init(); } /* Halt if there was a built in self test failure */ post_code(0x34); report_bist_failure(bist); /* Load MPB */ val = cpuid_eax(1); printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); post_code(0x37); agesawrapper_amdinitreset(); post_code(0x39); agesawrapper_amdinitearly(); int s3resume = acpi_is_wakeup_s3(); if (!s3resume) { post_code(0x40); agesawrapper_amdinitpost(); post_code(0x42); agesawrapper_amdinitenv(); amd_initenv(); } else { /* S3 detect */ printk(BIOS_INFO, "S3 detected\n"); post_code(0x60); agesawrapper_amdinitresume(); agesawrapper_amds3laterestore(); post_code(0x61); prepare_for_resume(); } post_code(0x50); copy_and_run(); printk(BIOS_ERR, "Error: copy_and_run() returned!\n"); post_code(0x54); /* Should never see this post code. */ }
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { static const uint16_t spd_addr[] = { DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, #if CONFIG_MAX_PHYSICAL_CPUS > 1 DIMM4, DIMM6, 0, 0, DIMM5, DIMM7, 0, 0, #endif }; int needs_reset; unsigned nodes, bsp_apicid = 0; struct mem_controller ctrl[8]; if (!cpu_init_detectedx && boot_cpu()) { /* Nothing special needs to be done to find bus 0 */ /* Allow the HT devices to be found */ enumerate_ht_chain(); sio_setup(); } if (bist == 0) bsp_apicid = init_cpus(cpu_init_detectedx); it8712f_24mhz_clkin(); it8712f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); /* Halt if there was a built in self test failure */ report_bist_failure(bist); #if 0 dump_pci_device(PCI_DEV(0, 0x18, 0)); #endif needs_reset = setup_coherent_ht_domain(); wait_all_core0_started(); #if CONFIG_LOGICAL_CPUS /* It is said that we should start core1 after all core0 launched. */ start_other_cores(); wait_all_other_cores_started(bsp_apicid); #endif needs_reset |= ht_setup_chains_x(); needs_reset |= ck804_early_setup_x(); if (needs_reset) { print_info("ht reset -\n"); soft_reset(); } allow_all_aps_stop(bsp_apicid); nodes = get_nodes(); /* It's the time to set ctrl now. */ fill_mem_ctrl(nodes, ctrl, spd_addr); enable_smbus(); #if 0 dump_spd_registers(&ctrl[0]); dump_smbus_registers(); #endif sdram_initialize(nodes, ctrl); #if 0 print_pci_devices(); dump_pci_devices(); #endif post_cache_as_ram(); }
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); u32 bsp_apicid = 0; u32 val; msr_t msr; if (!cpu_init_detectedx && boot_cpu()) { /* Nothing special needs to be done to find bus 0 */ /* Allow the HT devices to be found */ /* mov bsp to bus 0xff when > 8 nodes */ set_bsp_node_CHtExtNodeCfgEn(); enumerate_ht_chain(); /* Setup the rom access for 4M */ amd8111_enable_rom(); } post_code(0x30); if (bist == 0) { bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); /* mmconf is inited in init_cpus */ /* All cores run this but the BSP(node0,core0) is the only core that returns. */ } post_code(0x32); w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); printk(BIOS_DEBUG, "\n"); // dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE); /* Halt if there was a built in self test failure */ report_bist_failure(bist); // Load MPB val = cpuid_eax(1); printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val); printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1); printk(BIOS_DEBUG, "bsp_apicid = %02x \n", bsp_apicid); printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx); /* Setup sysinfo defaults */ set_sysinfo_in_ram(0); update_microcode(val); post_code(0x33); cpuSetAMDMSR(); post_code(0x34); amd_ht_init(sysinfo); post_code(0x35); /* Setup nodes PCI space and start core 0 AP init. */ finalize_node_setup(sysinfo); /* Setup any mainboard PCI settings etc. */ setup_mb_resource_map(); post_code(0x36); /* wait for all the APs core0 started by finalize_node_setup. */ /* FIXME: A bunch of cores are going to start output to serial at once. It would be nice to fixup prink spinlocks for ROM XIP mode. I think it could be done by putting the spinlock flag in the cache of the BSP located right after sysinfo. */ wait_all_core0_started(); #if CONFIG_LOGICAL_CPUS==1 /* Core0 on each node is configured. Now setup any additional cores. */ printk(BIOS_DEBUG, "start_other_cores()\n"); start_other_cores(); post_code(0x37); wait_all_other_cores_started(bsp_apicid); #endif post_code(0x38); #if SET_FIDVID == 1 msr = rdmsr(0xc0010071); printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo); /* FIXME: The sb fid change may survive the warm reset and only need to be done once.*/ enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn); post_code(0x39); if (!warm_reset_detect(0)) { // BSP is node 0 init_fidvid_bsp(bsp_apicid, sysinfo->nodes); } else { init_fidvid_stage2(bsp_apicid, 0); // BSP is node 0 } post_code(0x3A); /* show final fid and vid */ msr=rdmsr(0xc0010071); printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo); #endif /* Reset for HT, FIDVID, PLL and errata changes to take affect. */ if (!warm_reset_detect(0)) { print_info("...WARM RESET...\n\n\n"); soft_reset_x(sysinfo->sbbusn, sysinfo->sbdn); die("After soft_reset_x - shouldn't see this message!!!\n"); } post_code(0x3B); /* FIXME: Move this to chipset init. enable cf9 for hard reset */ print_debug("enable_cf9_x()\n"); enable_cf9_x(sysinfo->sbbusn, sysinfo->sbdn); post_code(0x3C); /* It's the time to set ctrl in sysinfo now; */ printk(BIOS_DEBUG, "fill_mem_ctrl()\n"); fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr); post_code(0x3D); printk(BIOS_DEBUG, "enable_smbus()\n"); enable_smbus(); post_code(0x3E); memreset_setup(); post_code(0x40); // die("Die Before MCT init."); printk(BIOS_DEBUG, "raminit_amdmct()\n"); raminit_amdmct(sysinfo); post_code(0x41); /* dump_pci_device_range(PCI_DEV(0, 0x18, 0), 0, 0x200); dump_pci_device_range(PCI_DEV(0, 0x18, 1), 0, 0x200); dump_pci_device_range(PCI_DEV(0, 0x18, 2), 0, 0x200); dump_pci_device_range(PCI_DEV(0, 0x18, 3), 0, 0x200); */ // ram_check(0x00200000, 0x00200000 + (640 * 1024)); // ram_check(0x40200000, 0x40200000 + (640 * 1024)); // die("After MCT init before CAR disabled."); post_code(0x42); printk(BIOS_DEBUG, "\n*** Yes, the copy/decompress is taking a while, FIXME!\n"); post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB. post_code(0x43); // Should never see this post code. }
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { u32 val; /* In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for * LpcClk[1:0]". To be consistent with Parmer, setting to 4mA * even though the register is not documented in the Kabini BKDG. * Otherwise the serial output is bad code. */ outb(0xD2, 0xcd6); outb(0x00, 0xcd7); AGESAWRAPPER(amdinitmmio); hudson_lpc_port80(); if (!cpu_init_detectedx && boot_cpu()) { post_code(0x30); post_code(0x31); console_init(); } /* Halt if there was a built in self test failure */ post_code(0x34); report_bist_failure(bist); /* Load MPB */ val = cpuid_eax(1); printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val); printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx); /* On Larne, after LpcClkDrvSth is set, it needs some time to be stable, because of the buffer ICS551M */ int i; for(i = 0; i < 200000; i++) val = inb(0xcd6); post_code(0x37); AGESAWRAPPER(amdinitreset); post_code(0x38); printk(BIOS_DEBUG, "Got past yangtze_early_setup\n"); post_code(0x39); AGESAWRAPPER(amdinitearly); int s3resume = acpi_is_wakeup_early() && acpi_s3_resume_allowed(); if (!s3resume) { post_code(0x40); AGESAWRAPPER(amdinitpost); post_code(0x41); AGESAWRAPPER(amdinitenv); /* TODO: Disable cache is not ok. */ disable_cache_as_ram(); } else { /* S3 detect */ printk(BIOS_INFO, "S3 detected\n"); post_code(0x60); AGESAWRAPPER(amdinitresume); AGESAWRAPPER(amds3laterestore); post_code(0x61); prepare_for_resume(); } outb(0xEA, 0xCD6); outb(0x1, 0xcd7); post_code(0x50); copy_and_run(); post_code(0x54); /* Should never see this post code. */ }
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { u32 val; #if CONFIG_HAVE_ACPI_RESUME void *resume_backup_memory; #endif /* * All cores: allow caching of flash chip code and data * (there are no cache-as-ram reliability concerns with family 14h) */ __writemsr (0x20c, (0x0100000000ull - CONFIG_ROM_SIZE) | 5); __writemsr (0x20d, (0x1000000000ull - CONFIG_ROM_SIZE) | 0x800); /* All cores: set pstate 0 (1600 MHz) early to save a few ms of boot time */ __writemsr (0xc0010062, 0); if (!cpu_init_detectedx && boot_cpu()) { post_code(0x30); sb_Poweron_Init(); post_code(0x31); w83627dhg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); } /* Halt if there was a built in self test failure */ post_code(0x34); report_bist_failure(bist); /* Load MPB */ val = cpuid_eax(1); printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val); printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx); post_code(0x35); printk(BIOS_DEBUG, "agesawrapper_amdinitmmio "); val = agesawrapper_amdinitmmio(); if (val) printk(BIOS_DEBUG, "error level: %x \n", val); else printk(BIOS_DEBUG, "passed.\n"); post_code(0x37); printk(BIOS_DEBUG, "agesawrapper_amdinitreset "); val = agesawrapper_amdinitreset(); if (val) printk(BIOS_DEBUG, "error level: %x \n", val); else printk(BIOS_DEBUG, "passed.\n"); post_code(0x39); printk(BIOS_DEBUG, "agesawrapper_amdinitearly "); val = agesawrapper_amdinitearly (); if (val) printk(BIOS_DEBUG, "error level: %x \n", val); else printk(BIOS_DEBUG, "passed.\n"); #if CONFIG_HAVE_ACPI_RESUME if (!acpi_is_wakeup_early()) { /* Check for S3 resume */ #endif post_code(0x40); printk(BIOS_DEBUG, "agesawrapper_amdinitpost "); val = agesawrapper_amdinitpost (); /* Reboots with outb(3,0x92), outb(4,0xcf9) or triple-fault all * hang, looks like DRAM re-init goes wrong, don't know why. */ if (val == 7) /* fatal, amdinitenv below is going to hang */ outb(0x06, 0x0cf9); /* reset system harder instead */ if (val) printk(BIOS_DEBUG, "error level: %x \n", val); else printk(BIOS_DEBUG, "passed.\n"); post_code(0x42); printk(BIOS_DEBUG, "agesawrapper_amdinitenv "); val = agesawrapper_amdinitenv (); if (val) printk(BIOS_DEBUG, "error level: %x \n", val); else printk(BIOS_DEBUG, "passed.\n"); #if CONFIG_HAVE_ACPI_RESUME } else { /* S3 detect */ printk(BIOS_INFO, "S3 detected\n"); post_code(0x60); printk(BIOS_DEBUG, "agesawrapper_amdinitresume "); val = agesawrapper_amdinitresume(); if (val) printk(BIOS_DEBUG, "error level: %x \n", val); else printk(BIOS_DEBUG, "passed.\n"); printk(BIOS_DEBUG, "agesawrapper_amds3laterestore "); val = agesawrapper_amds3laterestore (); if (val) printk(BIOS_DEBUG, "error level: %x \n", val); else printk(BIOS_DEBUG, "passed.\n"); post_code(0x61); printk(BIOS_DEBUG, "Find resume memory location\n"); resume_backup_memory = backup_resume(); post_code(0x62); printk(BIOS_DEBUG, "Move CAR stack.\n"); move_stack_high_mem(); printk(BIOS_DEBUG, "stack moved to: 0x%x\n", (u32) (resume_backup_memory + HIGH_MEMORY_SAVE)); post_code(0x63); disable_cache_as_ram(); printk(BIOS_DEBUG, "CAR disabled.\n"); set_resume_cache(); /* * Copy the system memory that is in the ramstage area to the * reserved area. */ if (resume_backup_memory) memcpy(resume_backup_memory, (void *)(CONFIG_RAMBASE), HIGH_MEMORY_SAVE); printk(BIOS_DEBUG, "System memory saved. OK to load ramstage.\n"); } #endif /* Initialize i8259 pic */ post_code(0x43); setup_i8259 (); /* Initialize i8254 timers */ post_code(0x44); setup_i8254 (); post_code(0x50); copy_and_run(); printk(BIOS_ERR, "Error: copy_and_run() returned!\n"); post_code(0x54); /* Should never see this post code. */ }
/* kernel entry point called at the end of the boot sequence */ void __boot() { if (current_cpu_id() == 0) { /* core 0 boots first, and does all of the initialization */ // boot parameters are on physical page 0 bootparams = physical_to_virtual(0x00000000); // initialize console early, so output works console_init(); // output should now work printf("Welcome to my kernel!\n"); printf("Running on a %d-way multi-core machine\n", current_cpu_exists()); // initialize memory allocators mem_init(); // prepare to handle interrupts, exceptions, etc. trap_init(); // initialize keyboard late, since it isn't really used by anything else keyboard_init(); // see which cores are already on for (int i = 0; i < 32; i++) printf("CPU[%d] is %s\n", i, (current_cpu_enable() & (1<<i)) ? "on" : "off"); // turn on all other cores set_cpu_enable(0xFFFFFFFF); // see which cores got turned on busy_wait(0.1); for (int i = 0; i < 32; i++) printf("CPU[%d] is %s\n", i, (current_cpu_enable() & (1<<i)) ? "on" : "off"); } else { /* remaining cores boot after core 0 turns them on */ // nothing to initialize here... } printf("Core %d of %d is alive!\n", current_cpu_id(), current_cpu_exists()); busy_wait(current_cpu_id() * 0.1); // wait a while so messages from different cores don't get so mixed up int size = 64 * 1024 * 4; printf("about to do calloc(%d, 1)\n", size); unsigned int t0 = current_cpu_cycles(); calloc(size, 1); unsigned int t1 = current_cpu_cycles(); printf("DONE (%u cycles)!\n", t1 - t0); while (1) ; for (int i = 1; i < 30; i++) { int size = 1 << i; printf("about to do calloc(%d, 1)\n", size); calloc(size, 1); } while (1) { printf("Core %d is still running...\n", current_cpu_id()); busy_wait(4.0); // wait 4 seconds } shutdown(); }
void boardsupport_init(central_data_t *central_data) { irq_initialize_vectors(); cpu_irq_enable(); Disable_global_interrupt(); // Initialize the sleep manager sleepmgr_init(); sysclk_init(); board_init(); delay_init(sysclk_get_cpu_hz()); time_keeper_init(); INTC_init_interrupts(); // Switch on the red LED LED_On(LED2); // servo_pwm_hardware_init(); pwm_servos_init( CS_ON_SERVO_7_8 ); // Init UART 0 for XBEE communication xbee_init(UART0); // Init UART 3 for GPS communication gps_ublox_init(&(central_data->gps), UART3); // Init UART 4 for wired communication //console_init(CONSOLE_UART4); // Init USB for wired communication console_init(CONSOLE_USB); // connect abstracted aliases to hardware ports central_data->telemetry_down_stream = xbee_get_out_stream(); central_data->telemetry_up_stream = xbee_get_in_stream(); central_data->debug_out_stream = console_get_out_stream(); central_data->debug_in_stream = console_get_in_stream(); // init debug output print_util_dbg_print_init(central_data->debug_out_stream); print_util_dbg_print("Debug stream initialised\r\n"); // Bind RC receiver with remote // spektrum_satellite_bind(); // RC receiver initialization spektrum_satellite_init(); // Init analog rails analog_monitor_conf_t analog_monitor_config = analog_monitor_default_config; //analog_monitor_config.conv_factor[ANALOG_RAIL_6] = 0.00023485f * 6.6f; //analog_monitor_config.conv_factor[ANALOG_RAIL_7] = 0.00023485f * 6.6f; //analog_monitor_config.conv_factor[ANALOG_RAIL_10] = -0.0002409f * 11.0f; //analog_monitor_config.conv_factor[ANALOG_RAIL_11] = -0.0002409f * 11.0f; analog_monitor_init(¢ral_data->analog_monitor, &analog_monitor_config); // init imu & compass i2c_driver_init(I2C0); lsm330dlc_init(); print_util_dbg_print("LSM330 initialised \r\n"); hmc5883l_init_slow(); print_util_dbg_print("HMC5883 initialised \r\n"); bmp085_init(¢ral_data->pressure); // init radar or ultrasound (not implemented yet) //i2c_driver_init(I2C1); // init 6V enable gpio_enable_gpio_pin(AVR32_PIN_PA04); gpio_set_gpio_pin(AVR32_PIN_PA04); Enable_global_interrupt(); // Init piezo speaker piezo_speaker_init_binary(); print_util_dbg_print("Board initialised\r\n"); }
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { static const uint16_t spd_addr[] = { // first node DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, // second node DIMM4, DIMM6, 0, 0, DIMM5, DIMM7, 0, 0, }; struct sys_info *sysinfo = &sysinfo_car; int needs_reset; unsigned bsp_apicid = 0; if (!cpu_init_detectedx && boot_cpu()) { /* Nothing special needs to be done to find bus 0 */ /* Allow the HT devices to be found */ enumerate_ht_chain(); bcm5785_enable_lpc(); pc87417_enable_dev(RTC_DEV); /* Enable RTC */ } if (bist == 0) bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); pilot_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); /* Halt if there was a built in self test failure */ report_bist_failure(bist); // setup_early_ipmi_serial(); pilot_early_init(SERIAL_DEV); //config port is being taken from SERIAL_DEV printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1); printk(BIOS_DEBUG, "bsp_apicid=%02x\n", bsp_apicid); #if CONFIG_MEM_TRAIN_SEQ == 1 set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram #endif setup_coherent_ht_domain(); wait_all_core0_started(); #if CONFIG_LOGICAL_CPUS // It is said that we should start core1 after all core0 launched /* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain, * So here need to make sure last core0 is started, esp for two way system, * (there may be apic id conflicts in that case) */ start_other_cores(); wait_all_other_cores_started(bsp_apicid); #endif /* it will set up chains and store link pair for optimization later */ ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn bcm5785_early_setup(); #if CONFIG_SET_FIDVID { msr_t msr; msr=rdmsr(0xc0010042); printk(BIOS_DEBUG, "begin msr fid, vid %08x %08x\n", msr.hi, msr.lo); } enable_fid_change(); enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn); init_fidvid_bsp(bsp_apicid); // show final fid and vid { msr_t msr; msr=rdmsr(0xc0010042); printk(BIOS_DEBUG, "end msr fid, vid %08x %08x\n", msr.hi, msr.lo); } #endif needs_reset = optimize_link_coherent_ht(); needs_reset |= optimize_link_incoherent_ht(sysinfo); // fidvid change will issue one LDTSTOP and the HT change will be effective too if (needs_reset) { printk(BIOS_INFO, "ht reset -\n"); soft_reset(); } allow_all_aps_stop(bsp_apicid); //It's the time to set ctrl in sysinfo now; fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr); enable_smbus(); //do we need apci timer, tsc...., only debug need it for better output /* all ap stopped? */ // init_timer(); // Need to use TMICT to synconize FID/VID sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo); post_cache_as_ram(); }
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { static const uint16_t spd_addr[] = { // Node 0 DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, // Node 1 DIMM4, DIMM6, 0, 0, DIMM5, DIMM7, 0, 0, }; unsigned bsp_apicid = 0; int needs_reset = 0; struct sys_info *sysinfo = &sysinfo_car; it8712f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); it8712f_kill_watchdog(); it8712f_enable_3vsbsw(); console_init(); enable_rom_decode(); printk(BIOS_INFO, "now booting... \n"); if (bist == 0) bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); /* Halt if there was a built in self test failure. */ report_bist_failure(bist); setup_default_resource_map(); setup_coherent_ht_domain(); wait_all_core0_started(); printk(BIOS_INFO, "now booting... All core 0 started\n"); #if CONFIG_LOGICAL_CPUS /* It is said that we should start core1 after all core0 launched. */ start_other_cores(); wait_all_other_cores_started(bsp_apicid); #endif init_timer(); ht_setup_chains_x(sysinfo); /* Init sblnk and sbbusn, nodes, sbdn. */ needs_reset = optimize_link_coherent_ht(); print_debug_hex8(needs_reset); needs_reset |= optimize_link_incoherent_ht(sysinfo); print_debug_hex8(needs_reset); needs_reset |= k8t890_early_setup_ht(); print_debug_hex8(needs_reset); vt8237_early_network_init(NULL); vt8237_early_spi_init(); if (needs_reset) { printk(BIOS_DEBUG, "ht reset -\n"); soft_reset(); printk(BIOS_DEBUG, "FAILED!\n"); } /* the HT settings needs to be OK, because link freq chnage may cause HT disconnect */ /* allow LDT STOP asserts */ vt8237_sb_enable_fid_vid(); enable_fid_change(); print_debug("after enable_fid_change\n"); init_fidvid_bsp(bsp_apicid); /* Stop the APs so we can start them later in init. */ allow_all_aps_stop(bsp_apicid); /* It's the time to set ctrl now. */ fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr); enable_smbus(); sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo); post_cache_as_ram(); }
int main() { xenon_make_it_faster(XENON_SPEED_FULL); xenos_init(VIDEO_MODE_AUTO); console_init(); xenon_sound_init(); pAudioStart = pAudioBuffer = (uint16_t*) malloc(48000 * sizeof (uint16_t)); memset(pAudioBuffer, 0, 48000 * sizeof (uint16_t)); usb_init(); usb_do_poll(); SYSVideoInit(); // Allocates and initializes memory. Should only be called once, before // any calls to other FCEU functions. FCEUI_Initialize(); //------------------------------------------------------------------------------------- // Set some setting //------------------------------------------------------------------------------------- // Specifies the base FCE Ultra directory. This should be called // immediately after FCEUI_Initialize() and any time afterwards. std::string base = "uda:/"; //FCEUI_SetBaseDirectory(base); // doesn't work ? newlib bug ? FCEUI_SetVidSystem(0); //Apply settings FCEUI_Sound(48000); FCEUI_SetSoundVolume(50); FCEUI_SetLowPass(0); if (FCEUI_LoadGame("uda:/Super Mario Bros. (Europe) (Rev 0A).zip", 0) != NULL) { FCEUI_SetInput(0, SI_GAMEPAD, (void*) &powerpadbuf, 0); FCEUI_SetInput(1, SI_GAMEPAD, (void*) &powerpadbuf, 0); //set to ntsc extern FCEUGI * GameInfo; GameInfo->vidsys = GIV_NTSC; } int32 * snd = NULL; int32 sndsize; // Copy contents of XBuf over to video memory(or whatever needs to be // done to make the contents of XBuf visible on screen). // Each line is 256 pixels(and bytes) in width, and there can be 240 // lines. The pitch for each line is 272 bytes. // XBuf will be 0 if the symbol FRAMESKIP is defined and this frame // was skipped. uint8 * bitmap; while (1) { FCEUI_Emulate(&bitmap, &snd, &sndsize, 0); for (int i = 0; i < (256 * 240); i++) { //Make an ARGB bitmap nesBitmap[i] = ((pcpalette[bitmap[i]].r) << 16) | ((pcpalette[bitmap[i]].g) << 8) | (pcpalette[bitmap[i]].b) | (0xFF << 24); } SYSVideoUpdate(); // Add Sound update_sound(snd,sndsize); // Add Input update_input(); } return 0; }
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { u32 val; post_code(0x30); amd_initmmio(); post_code(0x31); /* Halt if there was a built in self test failure */ post_code(0x33); report_bist_failure(bist); sb7xx_51xx_enable_wideio(0, 0x1600); /* though UARTs are on the NUVOTON BMC */ wpcm450_enable_dev(WPCM450_SP1, SIO_PORT, CONFIG_TTYS0_BASE); sb7xx_51xx_disable_wideio(0); post_code(0x34); post_code(0x35); console_init(); val = cpuid_eax(1); printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); post_code(0x37); agesawrapper_amdinitreset(); if (!cpu_init_detectedx && boot_cpu()) { post_code(0x38); /* * SR5650/5670/5690 RD890 chipset, read pci config space hang at POR, * Disable all Pcie Bridges to work around It. */ sr56x0_rd890_disable_pcie_bridge(); post_code(0x39); nb_Poweron_Init(); post_code(0x3A); sb_Poweron_Init(); } post_code(0x3B); agesawrapper_amdinitearly(); post_code(0x3C); /* W83627DHG pin89,90 function select is RSTOUT3#, RSTOUT2# by default. * In order to access W83795G/ADG HWM using I2C protocol, * we select function to SDA, SCL function (or GP33, GP32 function). */ w83627dhg_enable_i2c(PNP_DEV(0x2E, W83627DHG_SPI)); nb_Ht_Init(); post_code(0x3D); /* Reset for HT, FIDVID, PLL and ucode patch(errata) changes to take affect. */ if (!warm_reset_detect(0)) { printk(BIOS_INFO, "...WARM RESET...\n\n\n"); distinguish_cpu_resets(0); soft_reset(); die("After soft_reset_x - shouldn't see this message!!!\n"); } post_code(0x40); agesawrapper_amdinitpost(); post_code(0x41); agesawrapper_amdinitenv(); post_code(0x42); post_code(0x50); printk(BIOS_DEBUG, "Disabling cache as ram "); disable_cache_as_ram(); printk(BIOS_DEBUG, "done\n"); post_code(0x51); copy_and_run(); /* We will not return, Should never see this message and post code. */ printk(BIOS_DEBUG, "should not be here -\n"); post_code(0x54); }
int main(int argc, char **argv) { console_init(Version) ; //*********************************************************** // Check for NDIR environment variable //*********************************************************** // get program filename int startIdx = 1 ; char exename[PATH_MAX] ; // for (int j = 1; j < argc; j++) { // printf("0: %s\n", argv[j]) ; // } // interesting lessons from WinNT 4.0: // If the OS is WinNT 4.0, and; // If the executable file is located in the current directory, // THEN: // argv[0] does NOT contain the fully-qualified // path of the EXE, it *only* contains the EXE name. // In all other situations, argv[0] is fully qualified!! // // P.S. While we're here, derive default INI filename also // printf("argv0=%s\n", argv[0]) ; char* strptr = strrchr(argv[0], '\\') ; // no path present if (strptr == 0) { SearchPath(NULL, argv[0], ".exe", PATH_MAX, ininame, NULL) ; strptr = strrchr(ininame, '\\') ; if (strptr != 0) strcpy(strptr, "\\ndir.ini") ; strcpy(exename, argv[0]) ; // ininame[0] = 0 ; // ONLY support current location } else { // pick up INI filename strcpy(ininame, argv[0]) ; strptr = strrchr(ininame, '\\') ; if (strptr == 0) return 1; strcpy(strptr, "\\ndir.ini") ; // now process exe name for getenv() strptr++ ; //lint !e613: skip backslash strcpy(exename, strptr) ; //lint !e613 strptr = strchr(exename, '.') ; if (strptr != 0) *strptr = 0 ; // strip the extension } char* options = getenv(exename) ; if (options != 0) { argv[0] = options ; startIdx = 0 ; } // printf("ininame=%s\n", ininame) ; // getchar() ; // for (int j = startIdx; j < argc; j++) { // printf("1: %s\n", argv[j]) ; // } //*********************************************************** // first read default settings //*********************************************************** read_config_file() ; //*********************************************************** // override defaults with command line and environment vars //*********************************************************** parse_command_args(startIdx, argc, argv) ; verify_flags() ; // this may add extensions if -x is given //*********************************************************** // Execute the requested command //*********************************************************** // output_html_header("ndir32"); display_logo() ; if (n.help) info(helptxt) ; else if (n.info) info(idtxt) ; else if (n.drive_summary) display_drive_summary() ; else { // If no filespec was given, insert current path with *.* if (tcount==0) insert_target_filespec(".") ; sort_target_paths() ; // LFN: okay process_filespecs() ; } // output_html_footer(); error_exit(DATA_OKAY, NULL) ; return 0 ; }
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { u32 val; /* * All cores: allow caching of flash chip code and data * (there are no cache-as-ram reliability concerns with family 14h) */ __writemsr (0x20c, (0x0100000000ull - CONFIG_ROM_SIZE) | 5); __writemsr (0x20d, (0x1000000000ull - CONFIG_ROM_SIZE) | 0x800); /* All cores: set pstate 0 (1600 MHz) early to save a few ms of boot time */ __writemsr (0xc0010062, 0); if (!cpu_init_detectedx && boot_cpu()) { post_code(0x30); sb_Poweron_Init(); post_code(0x31); f81865f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); } /* Halt if there was a built in self test failure */ post_code(0x34); report_bist_failure(bist); /* Load MPB */ val = cpuid_eax(1); printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val); printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx); post_code(0x35); printk(BIOS_DEBUG, "agesawrapper_amdinitmmio "); val = agesawrapper_amdinitmmio(); if (val) printk(BIOS_DEBUG, "error level: %x \n", val); else printk(BIOS_DEBUG, "passed.\n"); post_code(0x37); printk(BIOS_DEBUG, "agesawrapper_amdinitreset "); val = agesawrapper_amdinitreset(); if (val) printk(BIOS_DEBUG, "error level: %x \n", val); else printk(BIOS_DEBUG, "passed.\n"); post_code(0x39); printk(BIOS_DEBUG, "agesawrapper_amdinitearly "); val = agesawrapper_amdinitearly (); if (val) printk(BIOS_DEBUG, "error level: %x \n", val); else printk(BIOS_DEBUG, "passed.\n"); post_code(0x40); printk(BIOS_DEBUG, "agesawrapper_amdinitpost "); val = agesawrapper_amdinitpost (); if (val) printk(BIOS_DEBUG, "error level: %x \n", val); else printk(BIOS_DEBUG, "passed.\n"); post_code(0x41); printk(BIOS_DEBUG, "agesawrapper_amdinitenv "); val = agesawrapper_amdinitenv (); if (val) printk(BIOS_DEBUG, "error level: %x \n", val); else printk(BIOS_DEBUG, "passed.\n"); post_code(0x50); copy_and_run(); printk(BIOS_ERR, "Error: copy_and_run() returned!\n"); post_code(0x54); /* Should never see this post code. */ }
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { static const u16 spd_addr[] = { DIMM0, 0, 0, 0, DIMM1, 0, 0, 0, }; int needs_reset = 0; u32 bsp_apicid = 0; msr_t msr; struct cpuid_result cpuid1; struct sys_info *sysinfo = &sysinfo_car; if (!cpu_init_detectedx && boot_cpu()) { /* Nothing special needs to be done to find bus 0 */ /* Allow the HT devices to be found */ enumerate_ht_chain(); /* sb600_lpc_port80(); */ sb600_pci_port80(); } technexion_post_code_init(); technexion_post_code(LED_MESSAGE_START); if (bist == 0) bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); enable_rs690_dev8(); sb600_lpc_init(); /* it8712f_enable_serial does not use its 1st parameter. */ it8712f_enable_serial(0, CONFIG_TTYS0_BASE); it8712f_kill_watchdog(); console_init(); /* Halt if there was a built in self test failure */ report_bist_failure(bist); printk(BIOS_DEBUG, "bsp_apicid=0x%x\n", bsp_apicid); setup_tim5690_resource_map(); setup_coherent_ht_domain(); #if CONFIG_LOGICAL_CPUS /* It is said that we should start core1 after all core0 launched */ wait_all_core0_started(); start_other_cores(); #endif wait_all_aps_started(bsp_apicid); ht_setup_chains_x(sysinfo); /* run _early_setup before soft-reset. */ rs690_early_setup(); sb600_early_setup(); /* Check to see if processor is capable of changing FIDVID */ /* otherwise it will throw a GP# when reading FIDVID_STATUS */ cpuid1 = cpuid(0x80000007); if ((cpuid1.edx & 0x6) == 0x6) { /* Read FIDVID_STATUS */ msr=rdmsr(0xc0010042); printk(BIOS_DEBUG, "begin msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo); enable_fid_change(); enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn); init_fidvid_bsp(bsp_apicid); /* show final fid and vid */ msr=rdmsr(0xc0010042); printk(BIOS_DEBUG, "end msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo); } else { printk(BIOS_DEBUG, "Changing FIDVID not supported\n"); } needs_reset = optimize_link_coherent_ht(); needs_reset |= optimize_link_incoherent_ht(sysinfo); rs690_htinit(); printk(BIOS_DEBUG, "needs_reset=0x%x\n", needs_reset); if (needs_reset) { print_info("ht reset -\n"); soft_reset(); } speaker_init(255); speaker_on_nodelay(); allow_all_aps_stop(bsp_apicid); /* It's the time to set ctrl now; */ printk(BIOS_DEBUG, "sysinfo->nodes: %2x sysinfo->ctrl: %p spd_addr: %p\n", sysinfo->nodes, sysinfo->ctrl, spd_addr); fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr); technexion_post_code(LED_MESSAGE_RAM); sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo); speaker_off_nodelay(); rs690_before_pci_init(); sb600_before_pci_init(); post_cache_as_ram(); }
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { static const uint16_t spd_addr [] = { //first node RC0|DIMM0, RC0|DIMM2, 0, 0, RC0|DIMM1, RC0|DIMM3, 0, 0, #if CONFIG_MAX_PHYSICAL_CPUS > 1 //second node RC1|DIMM0, RC1|DIMM2, 0, 0, RC1|DIMM1, RC1|DIMM3, 0, 0, #endif }; struct sys_info *sysinfo = &sysinfo_car; int needs_reset = 0; unsigned bsp_apicid = 0; if (bist == 0) bsp_apicid = init_cpus(cpu_init_detectedx,sysinfo); winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); /* Halt if there was a built in self test failure */ report_bist_failure(bist); printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1); setup_dl145g1_resource_map(); //setup_default_resource_map(); setup_coherent_ht_domain(); wait_all_core0_started(); #if CONFIG_LOGICAL_CPUS // It is said that we should start core1 after all core0 launched start_other_cores(); wait_all_other_cores_started(bsp_apicid); #endif ht_setup_chains_x(sysinfo); #if CONFIG_SET_FIDVID /* Check to see if processor is capable of changing FIDVID */ /* otherwise it will throw a GP# when reading FIDVID_STATUS */ struct cpuid_result cpuid1 = cpuid(0x80000007); if ((cpuid1.edx & 0x6) == 0x6) { { /* Read FIDVID_STATUS */ msr_t msr; msr = rdmsr(0xc0010042); printk(BIOS_DEBUG, "begin msr fid, vid %08x%08x\n", msr.hi, msr.lo); } enable_fid_change(); enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn); init_fidvid_bsp(bsp_apicid); // show final fid and vid { msr_t msr; msr = rdmsr(0xc0010042); printk(BIOS_DEBUG, "end msr fid, vid %08x%08x\n", msr.hi, msr.lo); } } else { printk(BIOS_DEBUG, "Changing FIDVID not supported\n"); } #endif needs_reset |= optimize_link_coherent_ht(); needs_reset |= optimize_link_incoherent_ht(sysinfo); if (needs_reset) { printk(BIOS_INFO, "ht reset -\n"); soft_reset_x(sysinfo->sbbusn, sysinfo->sbdn); } enable_smbus(); int i; for(i = 0; i < 2; i++) { activate_spd_rom(&sysinfo->ctrl[i]); } for(i = RC0; i <= RC1; i<<=1) { change_i2c_mux(i); } //dump_spd_registers(&sysinfo->ctrl[0]); //dump_spd_registers(&sysinfo->ctrl[1]); //dump_smbus_registers(); allow_all_aps_stop(bsp_apicid); //It's the time to set ctrl now; fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr); memreset_setup(); #if CONFIG_SET_FIDVID init_timer(); // Need to use TMICT to synchronize FID/VID #endif sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo); //dump_pci_devices(); post_cache_as_ram(); }
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { static const uint16_t spd_addr[] = { // first node DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, // second node DIMM4, DIMM6, 0, 0, DIMM5, DIMM7, 0, 0, }; struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); int needs_reset; unsigned bsp_apicid = 0; if (!cpu_init_detectedx && boot_cpu()) { /* Nothing special needs to be done to find bus 0 */ /* Allow the HT devices to be found */ enumerate_ht_chain(); /* Setup the rom access for 4M */ amd8111_enable_rom(); } if (bist == 0) { bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); } w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); /* Halt if there was a built in self test failure */ report_bist_failure(bist); printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1); setup_mb_resource_map(); print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\n"); #if CONFIG_MEM_TRAIN_SEQ == 1 set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram #endif setup_coherent_ht_domain(); // routing table and start other core0 wait_all_core0_started(); #if CONFIG_LOGICAL_CPUS==1 // It is said that we should start core1 after all core0 launched /* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain, * So here need to make sure last core0 is started, esp for two way system, * (there may be apic id conflicts in that case) */ start_other_cores(); wait_all_other_cores_started(bsp_apicid); #endif /* it will set up chains and store link pair for optimization later */ ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn #if SET_FIDVID == 1 { msr_t msr; msr=rdmsr(0xc0010042); print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n"); } enable_fid_change(); enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn); init_fidvid_bsp(bsp_apicid); // show final fid and vid { msr_t msr; msr=rdmsr(0xc0010042); print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n"); } #endif needs_reset = optimize_link_coherent_ht(); needs_reset |= optimize_link_incoherent_ht(sysinfo); // fidvid change will issue one LDTSTOP and the HT change will be effective too if (needs_reset) { print_info("ht reset -\n"); soft_reset_x(sysinfo->sbbusn, sysinfo->sbdn); } allow_all_aps_stop(bsp_apicid); //It's the time to set ctrl in sysinfo now; fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr); enable_smbus(); #if 0 dump_smbus_registers(); #endif memreset_setup(); //do we need apci timer, tsc...., only debug need it for better output /* all ap stopped? */ init_timer(); // Need to use TMICT to synconize FID/VID sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo); #if 0 dump_pci_devices(); #endif post_cache_as_ram(); // bsp swtich stack to ram and copy sysinfo ram now }
int main() { led_init(); led_on(); console_init(); printf("===== APP ENTRY =====\r\n"); systime_init(); enc_init(); usb_init(); halls_init(); therm_init(); //enc_print_regs(); printf("entering blink loop...\r\n"); __enable_irq(); usb_tx(1, g_tx_buf, sizeof(g_tx_buf)); uint16_t raw_angle = 0, prev_raw_angle = 0; float raw_vel = 0; float filt_vel[3] = {0}; float filt_angle[3] = {0}; //float raw_vel = 0, filt_vel = 0, filt_angle = 0; bool filter_init = false; float unwrapped_raw = 0, prev_unwrapped_raw = 0; uint32_t t = 0, t_last_led_blink = 0; const float pos_gain[3] = { 0.9f, 0.99f, 0.999f }; const float vel_gain[3] = { 0.99f, 0.999f, 0.9999f }; int wraps = 0; uint32_t t_last_therm_reading = 0; g_therm_celsius = therm_celsius(); while (1) { if (SYSTIME - t_last_therm_reading > 1000) { g_therm_celsius = therm_celsius(); t_last_therm_reading = SYSTIME; } if (SYSTIME - t_last_led_blink > 100000) { t_last_led_blink = SYSTIME; led_toggle(); /* printf("\n\n"); printf("gintsts = 0x%08x\r\n", (unsigned)USB_OTG_FS->GINTSTS); printf("dctl = 0x%08x\r\n", (unsigned)g_usbd_dbg->DCTL); printf("dsts = 0x%08x\r\n", (unsigned)g_usbd_dbg->DSTS); printf("dtxfsts1 = 0x%08x\r\n", (unsigned)USB_INEP(1)->DTXFSTS); printf("diepctl1 = 0x%08x\r\n", (unsigned)USB_INEP(1)->DIEPCTL); printf("diepint1 = 0x%08x\r\n", (unsigned)USB_INEP(1)->DIEPINT); printf("dieptsiz1= 0x%08x\r\n", (unsigned)USB_INEP(1)->DIEPTSIZ); */ } raw_angle = enc_poll_angle(); t = SYSTIME; if (filter_init) { int diff = raw_angle - prev_raw_angle; if (diff > 8000) wraps--; else if (diff < -8000) wraps++; unwrapped_raw = (float)raw_angle + wraps * 16384; // calculate raw_vel in ticks/usec for numerical stability // TODO: use a better timebase, since we're polling @ 100 khz so there // is extreme quantization on the microsecond clock float dt_usecs = (float)(t - g_t_angle) * 1000000.0f; if (dt_usecs < 1.0f) dt_usecs = 1.0f; // todo: this leads to bad numerical stability after lots of wraps // need to re-work this crap raw_vel = (unwrapped_raw - prev_unwrapped_raw) / dt_usecs; for (int i = 0; i < 3; i++) { filt_angle[i] = pos_gain[i] * filt_angle[i] + (1.0f - pos_gain[i]) * unwrapped_raw; filt_vel[i] = vel_gain[i] * filt_vel[i] + (1.0f - vel_gain[i]) * raw_vel * 1000000.0f; } } else { filter_init = true; for (int i = 0; i < 3; i++) { filt_angle[i] = raw_angle; filt_vel[i] = 0; } } prev_raw_angle = raw_angle; prev_unwrapped_raw = unwrapped_raw; __disable_irq(); g_t_angle = t; g_raw_angle = raw_angle; for (int i = 0; i < 3; i++) { g_angle[i] = filt_angle[i]; g_vel[i] = filt_vel[i]; // * 0.000001f; // convert to ticks / sec } g_num_samp++; __enable_irq(); } return 0; }
/*-----------------------------------------------------------------------------------*/ void bordercolor(unsigned char c) { /* Presume this to be one of the first calls. */ console_init(); }
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { u32 val; if (!cpu_init_detectedx && boot_cpu()) { post_code(0x30); sch4037_early_init(0x2e); /* Detect SMSC SIO1036 LPC Debug Card status */ if (detect_sio1036_chip(0x4E)) { /* Found SMSC SIO1036 LPC Debug Card */ sio1036_early_init(0x4E); } post_code(0x31); console_init(); /* * SR5650/5670/5690 RD890 chipset, read pci config space hang at POR, * Disable all Pcie Bridges to work around It. */ sr56x0_rd890_disable_pcie_bridge(); } post_code(0x32); val = agesawrapper_amdinitmmio(); if (val) { printk(BIOS_DEBUG, "agesawrapper_amdinitmmio failed: %x \n", val); } else { printk(BIOS_DEBUG, "agesawrapper_amdinitmmio passed\n"); } /* Halt if there was a built in self test failure */ post_code(0x33); report_bist_failure(bist); // Load MPB val = cpuid_eax(1); printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val); printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx); if(boot_cpu()) { post_code(0x34); sb_Poweron_Init(); } post_code(0x35); val = agesawrapper_amdinitreset(); if (val) { printk(BIOS_DEBUG, "agesawrapper_amdinitreset failed: %x \n", val); } else { printk(BIOS_DEBUG, "agesawrapper_amdinitreset passed\n"); } post_code(0x36); val = agesawrapper_amdinitearly (); if (val) { printk(BIOS_DEBUG, "agesawrapper_amdinitearly failed: %x \n", val); } else { printk(BIOS_DEBUG, "agesawrapper_amdinitearly passed\n"); } post_code(0x37); nb_Poweron_Init(); post_code(0x38); nb_Ht_Init(); post_code(0x39); val = agesawrapper_amdinitpost (); if (val) { printk(BIOS_DEBUG, "agesawrapper_amdinitpost failed: %x \n", val); } else { printk(BIOS_DEBUG, "agesawrapper_amdinitpost passed\n"); } post_code(0x40); val = agesawrapper_amdinitenv (); if (val) { printk(BIOS_DEBUG, "agesawrapper_amdinitenv failed: %x \n", val); } else { printk(BIOS_DEBUG, "agesawrapper_amdinitenv passed\n"); } post_code(0x43); print_debug("Disabling cache as ram "); disable_cache_as_ram(); print_debug("done\n"); post_code(0x44); copy_and_run(); post_code(0x45); // Should never see this post code. }
asmlinkage void __init start_kernel(void) { char * command_line; extern struct kernel_param __start___param[], __stop___param[]; smp_setup_processor_id(); /* * Need to run as early as possible, to initialize the * lockdep hash: */ unwind_init(); lockdep_init(); debug_objects_early_init(); cgroup_init_early(); local_irq_disable(); early_boot_irqs_off(); early_init_irq_lock_class(); /* * Interrupts are still disabled. Do necessary setups, then * enable them */ lock_kernel(); tick_init(); boot_cpu_init(); page_address_init(); printk(KERN_NOTICE); printk(linux_banner); setup_arch(&command_line); mm_init_owner(&init_mm, &init_task); setup_command_line(command_line); unwind_setup(); setup_per_cpu_areas(); setup_nr_cpu_ids(); smp_prepare_boot_cpu(); /* arch-specific boot-cpu hooks */ /* * Set up the scheduler prior starting any interrupts (such as the * timer interrupt). Full topology setup happens at smp_init() * time - but meanwhile we still have a functioning scheduler. */ sched_init(); /* * Disable preemption - early bootup scheduling is extremely * fragile until we cpu_idle() for the first time. */ preempt_disable(); build_all_zonelists(); page_alloc_init(); printk(KERN_NOTICE "Kernel command line: %s\n", boot_command_line); parse_early_param(); parse_args("Booting kernel", static_command_line, __start___param, __stop___param - __start___param, &unknown_bootoption); if (!irqs_disabled()) { printk(KERN_WARNING "start_kernel(): bug: interrupts were " "enabled *very* early, fixing it\n"); local_irq_disable(); } sort_main_extable(); trap_init(); rcu_init(); init_IRQ(); pidhash_init(); init_timers(); hrtimers_init(); softirq_init(); timekeeping_init(); time_init(); sched_clock_init(); profile_init(); if (!irqs_disabled()) printk("start_kernel(): bug: interrupts were enabled early\n"); early_boot_irqs_on(); local_irq_enable(); /* * HACK ALERT! This is early. We're enabling the console before * we've done PCI setups etc, and console_init() must be aware of * this. But we do want output early, in case something goes wrong. */ console_init(); if (panic_later) panic(panic_later, panic_param); lockdep_info(); /* * Need to run this when irqs are enabled, because it wants * to self-test [hard/soft]-irqs on/off lock inversion bugs * too: */ locking_selftest(); #ifdef CONFIG_BLK_DEV_INITRD if (initrd_start && !initrd_below_start_ok && page_to_pfn(virt_to_page((void *)initrd_start)) < min_low_pfn) { printk(KERN_CRIT "initrd overwritten (0x%08lx < 0x%08lx) - " "disabling it.\n", page_to_pfn(virt_to_page((void *)initrd_start)), min_low_pfn); initrd_start = 0; } #endif vmalloc_init(); vfs_caches_init_early(); cpuset_init_early(); page_cgroup_init(); mem_init(); enable_debug_pagealloc(); cpu_hotplug_init(); kmem_cache_init(); debug_objects_mem_init(); idr_init_cache(); setup_per_cpu_pageset(); numa_policy_init(); if (late_time_init) late_time_init(); calibrate_delay(); pidmap_init(); pgtable_cache_init(); prio_tree_init(); anon_vma_init(); #ifdef CONFIG_X86 if (efi_enabled) efi_enter_virtual_mode(); #endif thread_info_cache_init(); cred_init(); fork_init(num_physpages); proc_caches_init(); buffer_init(); key_init(); security_init(); vfs_caches_init(num_physpages); radix_tree_init(); signals_init(); /* rootfs populating might need page-writeback */ page_writeback_init(); #ifdef CONFIG_PROC_FS proc_root_init(); #endif cgroup_init(); cpuset_init(); taskstats_init_early(); delayacct_init(); check_bugs(); acpi_early_init(); /* before LAPIC and SMP init */ ftrace_init(); /* Do the rest non-__init'ed, we're now alive */ rest_init(); }
void hardwaremain(int boot_complete) { struct lb_memory *lb_mem; void *payload; timestamp_stash(TS_START_RAMSTAGE); post_code(POST_ENTRY_RAMSTAGE); #if CONFIG_COVERAGE coverage_init(); #endif /* console_init() MUST PRECEDE ALL printk()! */ console_init(); post_code(POST_CONSOLE_READY); printk(BIOS_NOTICE, "coreboot-%s%s %s %s...\n", coreboot_version, coreboot_extra_version, coreboot_build, (boot_complete)?"rebooting":"booting"); post_code(POST_CONSOLE_BOOT_MSG); /* If we have already booted attempt a hard reboot */ if (boot_complete) { hard_reset(); } /* FIXME: Is there a better way to handle this? */ init_timer(); timestamp_stash(TS_DEVICE_ENUMERATE); /* Initialize chips early, they might disable unused devices. */ dev_initialize_chips(); /* Find the devices we don't have hard coded knowledge about. */ dev_enumerate(); post_code(POST_DEVICE_ENUMERATION_COMPLETE); timestamp_stash(TS_DEVICE_CONFIGURE); /* Now compute and assign the bus resources. */ dev_configure(); post_code(POST_DEVICE_CONFIGURATION_COMPLETE); timestamp_stash(TS_DEVICE_ENABLE); /* Now actually enable devices on the bus */ dev_enable(); post_code(POST_DEVICES_ENABLED); timestamp_stash(TS_DEVICE_INITIALIZE); /* And of course initialize devices on the bus */ dev_initialize(); post_code(POST_DEVICES_INITIALIZED); timestamp_stash(TS_DEVICE_DONE); cbmem_initialize(); #if CONFIG_CONSOLE_CBMEM cbmemc_reinit(); #endif timestamp_sync(); #if CONFIG_HAVE_ACPI_RESUME suspend_resume(); post_code(0x8a); #endif timestamp_add_now(TS_CBMEM_POST); if (cbmem_post_handling) cbmem_post_handling(); timestamp_add_now(TS_WRITE_TABLES); /* Now that we have collected all of our information * write our configuration tables. */ lb_mem = write_tables(); timestamp_add_now(TS_LOAD_PAYLOAD); payload = cbfs_load_payload(CBFS_DEFAULT_MEDIA, CONFIG_CBFS_PREFIX "/payload"); if (! payload) die("Could not find a payload\n"); selfboot(lb_mem, payload); printk(BIOS_EMERG, "Boot failed"); }