bool read_n230_eeprom()
{
bool status = false;
if (flash_session.device == NULL) { //Initialize flash session structure for the first time
wb_spi_init(spi_flash_device.bus);
spif_init(&flash_session, &spi_flash_device, spif_spsn_s25flxx_operations());
}
spif_read_sync(&flash_session, N230_FLASH_NV_DATA_OFFSET, &eeprom_cache, sizeof(n230_eeprom_map_t));
//Verify data format
status = (eeprom_cache.data_version_major == default_eeprom.data_version_major);
//Sanity communication info
if (eeprom_cache.eth_info[0].ip_addr == 0xFFFFFFFF)
eeprom_cache.eth_info[0].ip_addr = default_eeprom.eth_info[0].ip_addr;
if (eeprom_cache.eth_info[1].ip_addr == 0xFFFFFFFF)
eeprom_cache.eth_info[1].ip_addr = default_eeprom.eth_info[1].ip_addr;
if (eeprom_cache.eth_info[0].subnet == 0xFFFFFFFF)
eeprom_cache.eth_info[0].subnet = default_eeprom.eth_info[0].subnet;
if (eeprom_cache.eth_info[1].subnet == 0xFFFFFFFF)
eeprom_cache.eth_info[1].subnet = default_eeprom.eth_info[1].subnet;
if (!status) {
UHD_FW_TRACE(WARN, "read_n230_eeprom: Initialized cache to the default map.");
memcpy(&eeprom_cache, &default_eeprom, sizeof(n230_eeprom_map_t));
}
cache_dirty = !status;
return status;
}
int main(int argc, char *argv[]) {
//uint8_t buf[32];
//int i = 0;
hal_disable_ints(); // In case we got here via jmp 0x0
// delay(10000000);
//before anything else you might want to blinkenlights just to indicate code startup to the user.
hal_uart_init();
spif_init();
// i2c_init(); //for EEPROM
puts("USRP2+ UART firmware loader");
// puts("Debug: loading production image, 10 bytes.");
// spi_flash_read(PROD_FW_IMAGE_LOCATION_ADDR, 10, buf);
// for(i=0; i < 10; i++) {
// puthex8(buf[i]);
// }
uart_flash_loader();
//shouldn't get here. should reboot.
puts("shit happened.\n");
return 0;
}
int main(int argc, char *argv[]) {
uint16_t i, t;
uint8_t buf[260];
const uint8_t testdata[] = {0xDE, 0xAD, 0xBE, 0xEF, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0x0C};
hal_disable_ints(); // In case we got here via jmp 0x0
// spi_init();
hal_uart_init();
// clocks_init(); //set up AD9510, enable FPGA clock @ 1x divisor
puts("SPI Flash test\n");
puts("Initializing SPI\n");
spif_init();
delay(800000);
puts("Erasing sector 1\n");
spi_flash_erase(0x00010000, 256);
delay(800000);
puts("Reading back data\n");
spi_flash_read(0x00010000, 256, buf);
delay(800000);
t=1;
for(i=4; i<250; i++) {
if(buf[i] != 0xFF) t=0;
}
if(!t) puts("Data was not initialized to 0xFF. Unsuccessful erase or read\n");
else puts("Data initialized to 0xFF, erase confirmed\n");
puts("Writing test buffer\n");
spi_flash_program(0x00010000, 16, testdata);
//memset(buf, 0, 256);
delay(800000);
puts("Wrote data, reading back\n");
spi_flash_read(0x00010000, 16, buf);
if(memcmp(testdata, buf, 16)) puts("Data is not the same between read and write. Unsuccessful write or read\n");
else puts("Successful write! Flash write correct\n");
return 0;
}
